2 * Copyright (C) 2013 Texas Instruments Incorporated
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/spi-omap2-mcspi.h>
18 #include "omap_hwmod.h"
19 #include "omap_hwmod_33xx_43xx_common_data.h"
21 #include "omap_hwmod_common_data.h"
26 static struct omap_hwmod am43xx_emif_hwmod = {
28 .class = &am33xx_emif_hwmod_class,
29 .clkdm_name = "emif_clkdm",
30 .flags = HWMOD_INIT_NO_IDLE,
31 .main_clk = "dpll_ddr_m2_ck",
34 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
35 .modulemode = MODULEMODE_SWCTRL,
40 static struct omap_hwmod am43xx_l4_hs_hwmod = {
42 .class = &am33xx_l4_hwmod_class,
43 .clkdm_name = "l3_clkdm",
44 .flags = HWMOD_INIT_NO_IDLE,
45 .main_clk = "l4hs_gclk",
48 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
49 .modulemode = MODULEMODE_SWCTRL,
54 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
55 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
58 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
60 .class = &am33xx_wkup_m3_hwmod_class,
61 .clkdm_name = "l4_wkup_aon_clkdm",
62 /* Keep hardreset asserted */
63 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
64 .main_clk = "sys_clkin_ck",
67 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
68 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
69 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
70 .modulemode = MODULEMODE_SWCTRL,
73 .rst_lines = am33xx_wkup_m3_resets,
74 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
77 static struct omap_hwmod am43xx_control_hwmod = {
79 .class = &am33xx_control_hwmod_class,
80 .clkdm_name = "l4_wkup_clkdm",
81 .flags = HWMOD_INIT_NO_IDLE,
82 .main_clk = "sys_clkin_ck",
85 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
86 .modulemode = MODULEMODE_SWCTRL,
91 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
92 { .role = "dbclk", .clk = "gpio0_dbclk" },
95 static struct omap_hwmod am43xx_gpio0_hwmod = {
97 .class = &am33xx_gpio_hwmod_class,
98 .clkdm_name = "l4_wkup_clkdm",
99 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
100 .main_clk = "sys_clkin_ck",
103 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
104 .modulemode = MODULEMODE_SWCTRL,
107 .opt_clks = gpio0_opt_clks,
108 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
111 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
114 .sysc_flags = SYSC_HAS_SIDLEMODE,
115 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
116 .sysc_fields = &omap_hwmod_sysc_type1,
119 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
121 .sysc = &am43xx_synctimer_sysc,
124 static struct omap_hwmod am43xx_synctimer_hwmod = {
125 .name = "counter_32k",
126 .class = &am43xx_synctimer_hwmod_class,
127 .clkdm_name = "l4_wkup_aon_clkdm",
128 .flags = HWMOD_SWSUP_SIDLE,
129 .main_clk = "synctimer_32kclk",
132 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
133 .modulemode = MODULEMODE_SWCTRL,
138 static struct omap_hwmod am43xx_timer8_hwmod = {
140 .class = &am33xx_timer_hwmod_class,
141 .clkdm_name = "l4ls_clkdm",
142 .main_clk = "timer8_fck",
145 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
146 .modulemode = MODULEMODE_SWCTRL,
151 static struct omap_hwmod am43xx_timer9_hwmod = {
153 .class = &am33xx_timer_hwmod_class,
154 .clkdm_name = "l4ls_clkdm",
155 .main_clk = "timer9_fck",
158 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
159 .modulemode = MODULEMODE_SWCTRL,
164 static struct omap_hwmod am43xx_timer10_hwmod = {
166 .class = &am33xx_timer_hwmod_class,
167 .clkdm_name = "l4ls_clkdm",
168 .main_clk = "timer10_fck",
171 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
172 .modulemode = MODULEMODE_SWCTRL,
177 static struct omap_hwmod am43xx_timer11_hwmod = {
179 .class = &am33xx_timer_hwmod_class,
180 .clkdm_name = "l4ls_clkdm",
181 .main_clk = "timer11_fck",
184 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
185 .modulemode = MODULEMODE_SWCTRL,
190 static struct omap_hwmod am43xx_epwmss3_hwmod = {
192 .class = &am33xx_epwmss_hwmod_class,
193 .clkdm_name = "l4ls_clkdm",
194 .main_clk = "l4ls_gclk",
197 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
198 .modulemode = MODULEMODE_SWCTRL,
203 static struct omap_hwmod am43xx_epwmss4_hwmod = {
205 .class = &am33xx_epwmss_hwmod_class,
206 .clkdm_name = "l4ls_clkdm",
207 .main_clk = "l4ls_gclk",
210 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
211 .modulemode = MODULEMODE_SWCTRL,
216 static struct omap_hwmod am43xx_epwmss5_hwmod = {
218 .class = &am33xx_epwmss_hwmod_class,
219 .clkdm_name = "l4ls_clkdm",
220 .main_clk = "l4ls_gclk",
223 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
224 .modulemode = MODULEMODE_SWCTRL,
229 static struct omap_hwmod am43xx_spi2_hwmod = {
231 .class = &am33xx_spi_hwmod_class,
232 .clkdm_name = "l4ls_clkdm",
233 .main_clk = "dpll_per_m2_div4_ck",
236 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
240 .dev_attr = &mcspi_attrib,
243 static struct omap_hwmod am43xx_spi3_hwmod = {
245 .class = &am33xx_spi_hwmod_class,
246 .clkdm_name = "l4ls_clkdm",
247 .main_clk = "dpll_per_m2_div4_ck",
250 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
251 .modulemode = MODULEMODE_SWCTRL,
254 .dev_attr = &mcspi_attrib,
257 static struct omap_hwmod am43xx_spi4_hwmod = {
259 .class = &am33xx_spi_hwmod_class,
260 .clkdm_name = "l4ls_clkdm",
261 .main_clk = "dpll_per_m2_div4_ck",
264 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
265 .modulemode = MODULEMODE_SWCTRL,
268 .dev_attr = &mcspi_attrib,
271 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
272 { .role = "dbclk", .clk = "gpio4_dbclk" },
275 static struct omap_hwmod am43xx_gpio4_hwmod = {
277 .class = &am33xx_gpio_hwmod_class,
278 .clkdm_name = "l4ls_clkdm",
279 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
280 .main_clk = "l4ls_gclk",
283 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
284 .modulemode = MODULEMODE_SWCTRL,
287 .opt_clks = gpio4_opt_clks,
288 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
291 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
292 { .role = "dbclk", .clk = "gpio5_dbclk" },
295 static struct omap_hwmod am43xx_gpio5_hwmod = {
297 .class = &am33xx_gpio_hwmod_class,
298 .clkdm_name = "l4ls_clkdm",
299 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
300 .main_clk = "l4ls_gclk",
303 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
304 .modulemode = MODULEMODE_SWCTRL,
307 .opt_clks = gpio5_opt_clks,
308 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
311 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
315 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
317 .class = &am43xx_ocp2scp_hwmod_class,
318 .clkdm_name = "l4ls_clkdm",
319 .main_clk = "l4ls_gclk",
322 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
323 .modulemode = MODULEMODE_SWCTRL,
328 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
330 .class = &am43xx_ocp2scp_hwmod_class,
331 .clkdm_name = "l4ls_clkdm",
332 .main_clk = "l4ls_gclk",
335 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
336 .modulemode = MODULEMODE_SWCTRL,
341 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
344 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
346 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
347 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
348 MSTANDBY_NO | MSTANDBY_SMART |
349 MSTANDBY_SMART_WKUP),
350 .sysc_fields = &omap_hwmod_sysc_type2,
353 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
354 .name = "usb_otg_ss",
355 .sysc = &am43xx_usb_otg_ss_sysc,
358 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
359 .name = "usb_otg_ss0",
360 .class = &am43xx_usb_otg_ss_hwmod_class,
361 .clkdm_name = "l3s_clkdm",
362 .main_clk = "l3s_gclk",
365 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
371 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
372 .name = "usb_otg_ss1",
373 .class = &am43xx_usb_otg_ss_hwmod_class,
374 .clkdm_name = "l3s_clkdm",
375 .main_clk = "l3s_gclk",
378 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
379 .modulemode = MODULEMODE_SWCTRL,
384 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
386 .sysc_flags = SYSC_HAS_SIDLEMODE,
387 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
389 .sysc_fields = &omap_hwmod_sysc_type2,
392 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
394 .sysc = &am43xx_qspi_sysc,
397 static struct omap_hwmod am43xx_qspi_hwmod = {
399 .class = &am43xx_qspi_hwmod_class,
400 .clkdm_name = "l3s_clkdm",
401 .main_clk = "l3s_gclk",
404 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
405 .modulemode = MODULEMODE_SWCTRL,
412 * TouchScreen Controller (Analog-To-Digital Converter)
414 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
417 .sysc_flags = SYSC_HAS_SIDLEMODE,
418 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
420 .sysc_fields = &omap_hwmod_sysc_type2,
423 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
425 .sysc = &am43xx_adc_tsc_sysc,
428 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
430 .class = &am43xx_adc_tsc_hwmod_class,
431 .clkdm_name = "l3s_tsc_clkdm",
432 .main_clk = "adc_tsc_fck",
435 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
436 .modulemode = MODULEMODE_SWCTRL,
441 static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
445 .sysc_flags = SYSS_HAS_RESET_STATUS,
448 static struct omap_hwmod_class am43xx_des_hwmod_class = {
450 .sysc = &am43xx_des_sysc,
453 static struct omap_hwmod am43xx_des_hwmod = {
455 .class = &am43xx_des_hwmod_class,
456 .clkdm_name = "l3_clkdm",
457 .main_clk = "l3_gclk",
460 .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
461 .modulemode = MODULEMODE_SWCTRL,
468 static struct omap_hwmod am43xx_dss_core_hwmod = {
470 .class = &omap2_dss_hwmod_class,
471 .clkdm_name = "dss_clkdm",
472 .main_clk = "disp_clk",
475 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
483 static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
485 .has_framedonetv_irq = 0
488 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
494 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
496 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
497 .sysc_fields = &omap_hwmod_sysc_type1,
500 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
502 .sysc = &am43xx_dispc_sysc,
505 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
507 .class = &am43xx_dispc_hwmod_class,
508 .clkdm_name = "dss_clkdm",
509 .main_clk = "disp_clk",
512 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
515 .dev_attr = &am43xx_dss_dispc_dev_attr,
516 .parent_hwmod = &am43xx_dss_core_hwmod,
521 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
523 .class = &omap2_rfbi_hwmod_class,
524 .clkdm_name = "dss_clkdm",
525 .main_clk = "disp_clk",
528 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
531 .parent_hwmod = &am43xx_dss_core_hwmod,
535 static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
539 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
540 .sysc_fields = &omap_hwmod_sysc_type1,
543 static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
545 .sysc = &am43xx_hdq1w_sysc,
546 .reset = &omap_hdq1w_reset,
549 static struct omap_hwmod am43xx_hdq1w_hwmod = {
551 .class = &am43xx_hdq1w_hwmod_class,
552 .clkdm_name = "l4ls_clkdm",
555 .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
556 .modulemode = MODULEMODE_SWCTRL,
561 static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
564 .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
565 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
566 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
567 .sysc_fields = &omap_hwmod_sysc_type2,
570 static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
572 .sysc = &am43xx_vpfe_sysc,
575 static struct omap_hwmod am43xx_vpfe0_hwmod = {
577 .class = &am43xx_vpfe_hwmod_class,
578 .clkdm_name = "l3s_clkdm",
581 .modulemode = MODULEMODE_SWCTRL,
582 .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
587 static struct omap_hwmod am43xx_vpfe1_hwmod = {
589 .class = &am43xx_vpfe_hwmod_class,
590 .clkdm_name = "l3s_clkdm",
593 .modulemode = MODULEMODE_SWCTRL,
594 .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
600 static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
601 .master = &am33xx_l3_main_hwmod,
602 .slave = &am43xx_emif_hwmod,
603 .clk = "dpll_core_m4_ck",
604 .user = OCP_USER_MPU | OCP_USER_SDMA,
607 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
608 .master = &am33xx_l3_main_hwmod,
609 .slave = &am43xx_l4_hs_hwmod,
611 .user = OCP_USER_MPU | OCP_USER_SDMA,
614 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
615 .master = &am43xx_wkup_m3_hwmod,
616 .slave = &am33xx_l4_wkup_hwmod,
617 .clk = "sys_clkin_ck",
618 .user = OCP_USER_MPU | OCP_USER_SDMA,
621 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
622 .master = &am33xx_l4_wkup_hwmod,
623 .slave = &am43xx_wkup_m3_hwmod,
624 .clk = "sys_clkin_ck",
625 .user = OCP_USER_MPU | OCP_USER_SDMA,
628 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
629 .master = &am33xx_l3_main_hwmod,
630 .slave = &am33xx_pruss_hwmod,
631 .clk = "dpll_core_m4_ck",
632 .user = OCP_USER_MPU,
635 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
636 .master = &am33xx_l4_wkup_hwmod,
637 .slave = &am33xx_smartreflex0_hwmod,
638 .clk = "sys_clkin_ck",
639 .user = OCP_USER_MPU,
642 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
643 .master = &am33xx_l4_wkup_hwmod,
644 .slave = &am33xx_smartreflex1_hwmod,
645 .clk = "sys_clkin_ck",
646 .user = OCP_USER_MPU,
649 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
650 .master = &am33xx_l4_wkup_hwmod,
651 .slave = &am43xx_control_hwmod,
652 .clk = "sys_clkin_ck",
653 .user = OCP_USER_MPU,
656 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
657 .master = &am33xx_l4_wkup_hwmod,
658 .slave = &am33xx_i2c1_hwmod,
659 .clk = "sys_clkin_ck",
660 .user = OCP_USER_MPU,
663 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
664 .master = &am33xx_l4_wkup_hwmod,
665 .slave = &am43xx_gpio0_hwmod,
666 .clk = "sys_clkin_ck",
667 .user = OCP_USER_MPU | OCP_USER_SDMA,
670 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
671 .master = &am33xx_l4_wkup_hwmod,
672 .slave = &am43xx_adc_tsc_hwmod,
673 .clk = "dpll_core_m4_div2_ck",
674 .user = OCP_USER_MPU,
677 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
678 .master = &am43xx_l4_hs_hwmod,
679 .slave = &am33xx_cpgmac0_hwmod,
680 .clk = "cpsw_125mhz_gclk",
681 .user = OCP_USER_MPU,
684 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
685 .master = &am33xx_l4_wkup_hwmod,
686 .slave = &am33xx_timer1_hwmod,
687 .clk = "sys_clkin_ck",
688 .user = OCP_USER_MPU,
691 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
692 .master = &am33xx_l4_wkup_hwmod,
693 .slave = &am33xx_uart1_hwmod,
694 .clk = "sys_clkin_ck",
695 .user = OCP_USER_MPU,
698 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
699 .master = &am33xx_l4_wkup_hwmod,
700 .slave = &am33xx_wd_timer1_hwmod,
701 .clk = "sys_clkin_ck",
702 .user = OCP_USER_MPU,
705 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
706 .master = &am33xx_l4_wkup_hwmod,
707 .slave = &am43xx_synctimer_hwmod,
708 .clk = "sys_clkin_ck",
709 .user = OCP_USER_MPU,
712 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
713 .master = &am33xx_l4_ls_hwmod,
714 .slave = &am43xx_timer8_hwmod,
716 .user = OCP_USER_MPU,
719 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
720 .master = &am33xx_l4_ls_hwmod,
721 .slave = &am43xx_timer9_hwmod,
723 .user = OCP_USER_MPU,
726 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
727 .master = &am33xx_l4_ls_hwmod,
728 .slave = &am43xx_timer10_hwmod,
730 .user = OCP_USER_MPU,
733 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
734 .master = &am33xx_l4_ls_hwmod,
735 .slave = &am43xx_timer11_hwmod,
737 .user = OCP_USER_MPU,
740 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
741 .master = &am33xx_l4_ls_hwmod,
742 .slave = &am43xx_epwmss3_hwmod,
744 .user = OCP_USER_MPU,
747 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
748 .master = &am33xx_l4_ls_hwmod,
749 .slave = &am43xx_epwmss4_hwmod,
751 .user = OCP_USER_MPU,
754 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
755 .master = &am33xx_l4_ls_hwmod,
756 .slave = &am43xx_epwmss5_hwmod,
758 .user = OCP_USER_MPU,
761 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
762 .master = &am33xx_l4_ls_hwmod,
763 .slave = &am43xx_spi2_hwmod,
765 .user = OCP_USER_MPU,
768 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
769 .master = &am33xx_l4_ls_hwmod,
770 .slave = &am43xx_spi3_hwmod,
772 .user = OCP_USER_MPU,
775 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
776 .master = &am33xx_l4_ls_hwmod,
777 .slave = &am43xx_spi4_hwmod,
779 .user = OCP_USER_MPU,
782 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
783 .master = &am33xx_l4_ls_hwmod,
784 .slave = &am43xx_gpio4_hwmod,
786 .user = OCP_USER_MPU | OCP_USER_SDMA,
789 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
790 .master = &am33xx_l4_ls_hwmod,
791 .slave = &am43xx_gpio5_hwmod,
793 .user = OCP_USER_MPU | OCP_USER_SDMA,
796 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
797 .master = &am33xx_l4_ls_hwmod,
798 .slave = &am43xx_ocp2scp0_hwmod,
800 .user = OCP_USER_MPU,
803 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
804 .master = &am33xx_l4_ls_hwmod,
805 .slave = &am43xx_ocp2scp1_hwmod,
807 .user = OCP_USER_MPU,
810 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
811 .master = &am33xx_l3_s_hwmod,
812 .slave = &am43xx_usb_otg_ss0_hwmod,
814 .user = OCP_USER_MPU | OCP_USER_SDMA,
817 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
818 .master = &am33xx_l3_s_hwmod,
819 .slave = &am43xx_usb_otg_ss1_hwmod,
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
824 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
825 .master = &am33xx_l3_s_hwmod,
826 .slave = &am43xx_qspi_hwmod,
828 .user = OCP_USER_MPU | OCP_USER_SDMA,
831 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
832 .master = &am43xx_dss_core_hwmod,
833 .slave = &am33xx_l3_main_hwmod,
835 .user = OCP_USER_MPU | OCP_USER_SDMA,
838 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
839 .master = &am33xx_l4_ls_hwmod,
840 .slave = &am43xx_dss_core_hwmod,
842 .user = OCP_USER_MPU | OCP_USER_SDMA,
845 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
846 .master = &am33xx_l4_ls_hwmod,
847 .slave = &am43xx_dss_dispc_hwmod,
849 .user = OCP_USER_MPU | OCP_USER_SDMA,
852 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
853 .master = &am33xx_l4_ls_hwmod,
854 .slave = &am43xx_dss_rfbi_hwmod,
856 .user = OCP_USER_MPU | OCP_USER_SDMA,
859 static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
860 .master = &am33xx_l4_ls_hwmod,
861 .slave = &am43xx_hdq1w_hwmod,
863 .user = OCP_USER_MPU | OCP_USER_SDMA,
866 static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
867 .master = &am43xx_vpfe0_hwmod,
868 .slave = &am33xx_l3_main_hwmod,
870 .user = OCP_USER_MPU | OCP_USER_SDMA,
873 static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
874 .master = &am43xx_vpfe1_hwmod,
875 .slave = &am33xx_l3_main_hwmod,
877 .user = OCP_USER_MPU | OCP_USER_SDMA,
880 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
881 .master = &am33xx_l4_ls_hwmod,
882 .slave = &am43xx_vpfe0_hwmod,
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
887 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
888 .master = &am33xx_l4_ls_hwmod,
889 .slave = &am43xx_vpfe1_hwmod,
891 .user = OCP_USER_MPU | OCP_USER_SDMA,
894 static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
895 .master = &am33xx_l3_main_hwmod,
896 .slave = &am43xx_des_hwmod,
898 .user = OCP_USER_MPU,
901 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
902 &am33xx_l4_wkup__synctimer,
903 &am43xx_l4_ls__timer8,
904 &am43xx_l4_ls__timer9,
905 &am43xx_l4_ls__timer10,
906 &am43xx_l4_ls__timer11,
907 &am43xx_l4_ls__epwmss3,
908 &am43xx_l4_ls__epwmss4,
909 &am43xx_l4_ls__epwmss5,
910 &am43xx_l4_ls__mcspi2,
911 &am43xx_l4_ls__mcspi3,
912 &am43xx_l4_ls__mcspi4,
913 &am43xx_l4_ls__gpio4,
914 &am43xx_l4_ls__gpio5,
915 &am43xx_l3_main__pruss,
916 &am33xx_mpu__l3_main,
919 &am33xx_l3_s__l4_wkup,
920 &am43xx_l3_main__l4_hs,
921 &am33xx_l3_main__l3_s,
922 &am33xx_l3_main__l3_instr,
923 &am33xx_l3_main__gfx,
924 &am33xx_l3_s__l3_main,
925 &am43xx_l3_main__emif,
926 &am33xx_pruss__l3_main,
927 &am43xx_wkup_m3__l4_wkup,
928 &am33xx_gfx__l3_main,
929 &am43xx_l4_wkup__wkup_m3,
930 &am43xx_l4_wkup__control,
931 &am43xx_l4_wkup__smartreflex0,
932 &am43xx_l4_wkup__smartreflex1,
933 &am43xx_l4_wkup__uart1,
934 &am43xx_l4_wkup__timer1,
935 &am43xx_l4_wkup__i2c1,
936 &am43xx_l4_wkup__gpio0,
937 &am43xx_l4_wkup__wd_timer1,
938 &am43xx_l4_wkup__adc_tsc,
940 &am33xx_l4_per__dcan0,
941 &am33xx_l4_per__dcan1,
942 &am33xx_l4_per__gpio1,
943 &am33xx_l4_per__gpio2,
944 &am33xx_l4_per__gpio3,
945 &am33xx_l4_per__i2c2,
946 &am33xx_l4_per__i2c3,
947 &am33xx_l4_per__mailbox,
949 &am33xx_l4_ls__mcasp0,
950 &am33xx_l4_ls__mcasp1,
954 &am33xx_l4_ls__timer2,
955 &am33xx_l4_ls__timer3,
956 &am33xx_l4_ls__timer4,
957 &am33xx_l4_ls__timer5,
958 &am33xx_l4_ls__timer6,
959 &am33xx_l4_ls__timer7,
960 &am33xx_l3_main__tpcc,
961 &am33xx_l4_ls__uart2,
962 &am33xx_l4_ls__uart3,
963 &am33xx_l4_ls__uart4,
964 &am33xx_l4_ls__uart5,
965 &am33xx_l4_ls__uart6,
966 &am33xx_l4_ls__spinlock,
968 &am33xx_l4_ls__epwmss0,
969 &am33xx_l4_ls__epwmss1,
970 &am33xx_l4_ls__epwmss2,
972 &am33xx_l4_ls__mcspi0,
973 &am33xx_l4_ls__mcspi1,
974 &am33xx_l3_main__tptc0,
975 &am33xx_l3_main__tptc1,
976 &am33xx_l3_main__tptc2,
977 &am33xx_l3_main__ocmc,
978 &am43xx_l4_hs__cpgmac0,
979 &am33xx_cpgmac0__mdio,
980 &am33xx_l3_main__sha0,
981 &am33xx_l3_main__aes0,
982 &am43xx_l3_main__des,
983 &am43xx_l4_ls__ocp2scp0,
984 &am43xx_l4_ls__ocp2scp1,
985 &am43xx_l3_s__usbotgss0,
986 &am43xx_l3_s__usbotgss1,
987 &am43xx_dss__l3_main,
989 &am43xx_l4_ls__dss_dispc,
990 &am43xx_l4_ls__dss_rfbi,
991 &am43xx_l4_ls__hdq1w,
994 &am43xx_l4_ls__vpfe0,
995 &am43xx_l4_ls__vpfe1,
999 static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
1000 &am33xx_l4_wkup__rtc,
1004 int __init am43xx_hwmod_init(void)
1008 omap_hwmod_am43xx_reg();
1010 ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
1012 if (!ret && of_machine_is_compatible("ti,am4372"))
1013 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);