2 * arch/arm/mach-dove/pcie.c
4 * PCIe functions for Marvell Dove 88AP510 SoC
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/clk.h>
14 #include <video/vga.h>
15 #include <asm/mach/pci.h>
16 #include <asm/mach/arch.h>
17 #include <asm/setup.h>
18 #include <asm/delay.h>
19 #include <plat/pcie.h>
20 #include <plat/addr-map.h>
22 #include "bridge-regs.h"
30 char mem_space_name[16];
34 static struct pcie_port pcie_port[2];
35 static int num_pcie_ports;
38 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
41 struct resource realio;
43 if (nr >= num_pcie_ports)
47 sys->private_data = pp;
48 pp->root_bus_nr = sys->busnr;
51 * Generic PCIe unit setup.
53 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
55 orion_pcie_setup(pp->base);
57 realio.start = sys->busnr * SZ_64K;
58 realio.end = realio.start + SZ_64K - 1;
59 pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
60 DOVE_PCIE1_IO_PHYS_BASE);
65 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
66 "PCIe %d MEM", pp->index);
67 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
68 pp->res.name = pp->mem_space_name;
70 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
71 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
73 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
74 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
76 pp->res.flags = IORESOURCE_MEM;
77 if (request_resource(&iomem_resource, &pp->res))
78 panic("Request PCIe Memory resource failed\n");
79 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
84 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
87 * Don't go out when trying to access nonexisting devices
90 if (bus == pp->root_bus_nr && dev > 1)
96 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
99 struct pci_sys_data *sys = bus->sysdata;
100 struct pcie_port *pp = sys->private_data;
104 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
106 return PCIBIOS_DEVICE_NOT_FOUND;
109 spin_lock_irqsave(&pp->conf_lock, flags);
110 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
111 spin_unlock_irqrestore(&pp->conf_lock, flags);
116 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
117 int where, int size, u32 val)
119 struct pci_sys_data *sys = bus->sysdata;
120 struct pcie_port *pp = sys->private_data;
124 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
125 return PCIBIOS_DEVICE_NOT_FOUND;
127 spin_lock_irqsave(&pp->conf_lock, flags);
128 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
129 spin_unlock_irqrestore(&pp->conf_lock, flags);
134 static struct pci_ops pcie_ops = {
135 .read = pcie_rd_conf,
136 .write = pcie_wr_conf,
139 static void rc_pci_fixup(struct pci_dev *dev)
142 * Prevent enumeration of root complex.
144 if (dev->bus->parent == NULL && dev->devfn == 0) {
147 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
148 dev->resource[i].start = 0;
149 dev->resource[i].end = 0;
150 dev->resource[i].flags = 0;
154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
157 dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
159 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
161 if (nr >= num_pcie_ports) {
166 list_splice_init(&sys->resources, &bridge->windows);
167 bridge->dev.parent = NULL;
168 bridge->sysdata = sys;
169 bridge->busnr = sys->busnr;
170 bridge->ops = &pcie_ops;
172 return pci_scan_root_bus_bridge(bridge);
175 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
177 struct pci_sys_data *sys = dev->sysdata;
178 struct pcie_port *pp = sys->private_data;
180 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
183 static struct hw_pci dove_pci __initdata = {
185 .setup = dove_pcie_setup,
186 .scan = dove_pcie_scan_bus,
187 .map_irq = dove_pcie_map_irq,
190 static void __init add_pcie_port(int index, void __iomem *base)
192 printk(KERN_INFO "Dove PCIe port %d: ", index);
194 if (orion_pcie_link_up(base)) {
195 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
196 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
199 clk_prepare_enable(clk);
201 printk(KERN_INFO "link up\n");
204 pp->root_bus_nr = -1;
206 spin_lock_init(&pp->conf_lock);
207 memset(&pp->res, 0, sizeof(pp->res));
209 printk(KERN_INFO "link down, ignoring\n");
213 void __init dove_pcie_init(int init_port0, int init_port1)
215 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
218 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
221 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
223 pci_common_init(&dove_pci);