arch/arm/boot/dts/vf610-bk4.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2018
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 /dts-v1/;
   8 #include "vf610.dtsi"
   9
  10 / {
  11         model = "Liebherr BK4 controller";
  12         compatible = "lwn,bk4", "fsl,vf610";
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17
  18         memory@80000000 {
  19                 reg = <0x80000000 0x8000000>;
  20         };
  21
  22         audio_ext: oscillator-audio {
  23                 compatible = "fixed-clock";
  24                 #clock-cells = <0>;
  25                 clock-frequency = <24576000>;
  26         };
  27
  28         enet_ext: oscillator-ethernet {
  29                 compatible = "fixed-clock";
  30                 #clock-cells = <0>;
  31                 clock-frequency = <50000000>;
  32         };
  33
  34         leds {
  35                 compatible = "gpio-leds";
  36                 pinctrl-names = "default";
  37                 pinctrl-0 = <&pinctrl_gpio_leds>;
  38
  39                 /* LED D5 */
  40                 led0: heartbeat {
  41                         label = "heartbeat";
  42                         gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
  43                         default-state = "on";
  44                         linux,default-trigger = "heartbeat";
  45                 };
  46         };
  47
  48         reg_3p3v: regulator-3p3v {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "3P3V";
  51                 regulator-min-microvolt = <3300000>;
  52                 regulator-max-microvolt = <3300000>;
  53                 regulator-always-on;
  54         };
  55
  56         reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "vcc_3v3_mcu";
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61         };
  62 };
  63
  64 &adc0 {
  65         vref-supply = <&reg_vcc_3v3_mcu>;
  66         status = "okay";
  67 };
  68
  69 &adc1 {
  70         vref-supply = <&reg_vcc_3v3_mcu>;
  71         status = "okay";
  72 };
  73
  74 &can0 {
  75         pinctrl-names = "default";
  76         pinctrl-0 = <&pinctrl_can0>;
  77         status = "okay";
  78 };
  79
  80 &can1 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_can1>;
  83         status = "okay";
  84 };
  85
  86 &clks {
  87         clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
  88         clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
  89 };
  90
  91 &dspi0 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_dspi0>;
  94         bus-num = <0>;
  95         status = "okay";
  96
  97         spidev0@0 {
  98                 compatible = "lwn,bk4";
  99                 spi-max-frequency = <30000000>;
 100                 reg = <0>;
 101                 fsl,spi-cs-sck-delay = <200>;
 102                 fsl,spi-sck-cs-delay = <400>;
 103         };
 104 };
 105
 106 &dspi3 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_dspi3>;
 109         bus-num = <3>;
 110         status = "okay";
 111         spi-slave;
 112
 113         slave@0 {
 114                 compatible = "lwn,bk4";
 115                 spi-max-frequency = <30000000>;
 116                 reg = <0>;
 117         };
 118 };
 119
 120 &edma0 {
 121         status = "okay";
 122 };
 123
 124 &edma1 {
 125         status = "okay";
 126 };
 127
 128 &esdhc1 {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_esdhc1>;
 131         bus-width = <4>;
 132         cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
 133         status = "okay";
 134 };
 135
 136 &fec0 {
 137         phy-mode = "rmii";
 138         phy-handle = <&ethphy0>;
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_fec0>;
 141         status = "okay";
 142
 143         mdio {
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146
 147                 ethphy0: ethernet-phy@1 {
 148                         reg = <1>;
 149                         clocks = <&clks VF610_CLK_ENET_50M>;
 150                         clock-names = "rmii-ref";
 151                 };
 152         };
 153 };
 154
 155 &fec1 {
 156         phy-mode = "rmii";
 157         phy-handle = <&ethphy1>;
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_fec1>;
 160         status = "okay";
 161
 162         mdio {
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165
 166                 ethphy1: ethernet-phy@1 {
 167                         reg = <1>;
 168                         clocks = <&clks VF610_CLK_ENET_50M>;
 169                         clock-names = "rmii-ref";
 170                 };
 171         };
 172 };
 173
 174 &i2c2 {
 175         clock-frequency = <400000>;
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&pinctrl_i2c2>;
 178         status = "okay";
 179
 180         at24c256: eeprom@50 {
 181                 compatible = "atmel,24c256";
 182                 reg = <0x50>;
 183         };
 184
 185         m41t62: rtc@68 {
 186                 compatible = "st,m41t62";
 187                 reg = <0x68>;
 188         };
 189 };
 190
 191 &nfc {
 192         assigned-clocks = <&clks VF610_CLK_NFC>;
 193         assigned-clock-rates = <33000000>;
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&pinctrl_nfc>;
 196         status = "okay";
 197
 198         nand@0 {
 199                 compatible = "fsl,vf610-nfc-nandcs";
 200                 reg = <0>;
 201                 #address-cells = <1>;
 202                 #size-cells = <1>;
 203                 nand-bus-width = <16>;
 204                 nand-ecc-mode = "hw";
 205                 nand-ecc-strength = <24>;
 206                 nand-ecc-step-size = <2048>;
 207                 nand-on-flash-bbt;
 208         };
 209 };
 210
 211 &qspi0 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_qspi0>;
 214         status = "okay";
 215
 216         n25q128a13_4: flash@0 {
 217                 compatible = "n25q128a13", "jedec,spi-nor";
 218                 #address-cells = <1>;
 219                 #size-cells = <1>;
 220                 spi-max-frequency = <66000000>;
 221                 spi-rx-bus-width = <4>;
 222                 reg = <0>;
 223         };
 224
 225         n25q128a13_2: flash@1 {
 226                 compatible = "n25q128a13", "jedec,spi-nor";
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229                 spi-max-frequency = <66000000>;
 230                 spi-rx-bus-width = <2>;
 231                 reg = <1>;
 232         };
 233 };
 234
 235 &uart0 {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_uart0>;
 238         status = "okay";
 239 };
 240
 241 &uart1 {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_uart1>;
 244         status = "okay";
 245 };
 246
 247 &uart2 {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_uart2>;
 250         status = "okay";
 251 };
 252
 253 &uart3 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_uart3>;
 256         status = "okay";
 257 };
 258
 259 &usbdev0 {
 260         disable-over-current;
 261         status = "okay";
 262 };
 263
 264 &usbh1 {
 265         disable-over-current;
 266         status = "okay";
 267 };
 268
 269 &usbmisc0 {
 270         status = "okay";
 271 };
 272
 273 &usbmisc1 {
 274         status = "okay";
 275 };
 276
 277 &usbphy0 {
 278         status = "okay";
 279 };
 280
 281 &usbphy1 {
 282         status = "okay";
 283 };
 284
 285 &iomuxc {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_hog>;
 288
 289         pinctrl_hog: hoggrp {
 290                 fsl,pins = <
 291                         /* One_Wire_PSU_EN */
 292                         VF610_PAD_PTC29__GPIO_102               0x1183
 293                         /* SPI ENABLE */
 294                         VF610_PAD_PTB26__GPIO_96                0x1183
 295                         /* EB control */
 296                         VF610_PAD_PTE14__GPIO_119               0x1183
 297                         VF610_PAD_PTE4__GPIO_109                0x1181
 298                         /* Feedback_Lines */
 299                         VF610_PAD_PTC31__GPIO_104               0x1181
 300                         VF610_PAD_PTA7__GPIO_134                0x1181
 301                         VF610_PAD_PTD9__GPIO_88         0x1181
 302                         VF610_PAD_PTE1__GPIO_106                0x1183
 303                         VF610_PAD_PTB2__GPIO_24         0x1181
 304                         VF610_PAD_PTB3__GPIO_25         0x1181
 305                         VF610_PAD_PTB1__GPIO_23         0x1181
 306                         /* SDHC Enable */
 307                         VF610_PAD_PTE19__GPIO_124               0x1183
 308                         /* SDHC Overcurrent */
 309                         VF610_PAD_PTB23__GPIO_93                0x1181
 310                         /* GPI */
 311                         VF610_PAD_PTE2__GPIO_107                0x1181
 312                         VF610_PAD_PTE3__GPIO_108                0x1181
 313                         VF610_PAD_PTE5__GPIO_110                0x1181
 314                         VF610_PAD_PTE6__GPIO_111                0x1181
 315                         /* GPO */
 316                         VF610_PAD_PTE0__GPIO_105                0x1183
 317                         VF610_PAD_PTE7__GPIO_112                0x1183
 318                         /* RS485 Control */
 319                         VF610_PAD_PTB8__GPIO_30         0x1183
 320                         VF610_PAD_PTB9__GPIO_31         0x1183
 321                         VF610_PAD_PTE8__GPIO_113                0x1183
 322                         /* MPBUS MPB_EN */
 323                         VF610_PAD_PTE28__GPIO_133               0x1183
 324                         /* MISC */
 325                         VF610_PAD_PTE10__GPIO_115               0x1183
 326                         VF610_PAD_PTE11__GPIO_116               0x1183
 327                         VF610_PAD_PTE17__GPIO_122               0x1183
 328                         VF610_PAD_PTC30__GPIO_103               0x1183
 329                         VF610_PAD_PTB0__GPIO_22         0x1181
 330                         /* RESETINFO */
 331                         VF610_PAD_PTE26__GPIO_131               0x1183
 332                         VF610_PAD_PTD6__GPIO_85         0x1181
 333                         VF610_PAD_PTE27__GPIO_132               0x1181
 334                         VF610_PAD_PTE13__GPIO_118               0x1181
 335                         VF610_PAD_PTE21__GPIO_126               0x1181
 336                         VF610_PAD_PTE22__GPIO_127               0x1181
 337                         /* EE_5V_EN */
 338                         VF610_PAD_PTE18__GPIO_123               0x1183
 339                         /* EE_5V_OC_N */
 340                         VF610_PAD_PTE25__GPIO_130               0x1181
 341                 >;
 342         };
 343
 344         pinctrl_can0: can0grp {
 345                 fsl,pins = <
 346                         VF610_PAD_PTB14__CAN0_RX                0x1181
 347                         VF610_PAD_PTB15__CAN0_TX                0x1182
 348                 >;
 349         };
 350
 351         pinctrl_can1: can1grp {
 352                 fsl,pins = <
 353                         VF610_PAD_PTB16__CAN1_RX                0x1181
 354                         VF610_PAD_PTB17__CAN1_TX                0x1182
 355                 >;
 356         };
 357
 358         pinctrl_dspi0: dspi0grp {
 359                 fsl,pins = <
 360                         VF610_PAD_PTB18__DSPI0_CS1              0x1182
 361                         VF610_PAD_PTB19__DSPI0_CS0              0x1182
 362                         VF610_PAD_PTB20__DSPI0_SIN              0x1181
 363                         VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 364                         VF610_PAD_PTB22__DSPI0_SCK              0x1182
 365                 >;
 366         };
 367
 368         pinctrl_dspi3: dspi3grp {
 369                 fsl,pins = <
 370                         VF610_PAD_PTD10__DSPI3_CS0              0x1181
 371                         VF610_PAD_PTD11__DSPI3_SIN              0x1181
 372                         VF610_PAD_PTD12__DSPI3_SOUT             0x1182
 373                         VF610_PAD_PTD13__DSPI3_SCK              0x1181
 374                 >;
 375         };
 376
 377         pinctrl_esdhc1: esdhc1grp {
 378                 fsl,pins = <
 379                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 380                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 381                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 382                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 383                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 384                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 385                         VF610_PAD_PTB28__GPIO_98                0x219d
 386                 >;
 387         };
 388
 389         pinctrl_fec0: fec0grp {
 390                 fsl,pins = <
 391                         VF610_PAD_PTA6__RMII_CLKIN              0x30dd
 392                         VF610_PAD_PTC0__ENET_RMII0_MDC          0x30de
 393                         VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
 394                         VF610_PAD_PTC2__ENET_RMII0_CRS          0x30dd
 395                         VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
 396                         VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
 397                         VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
 398                         VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
 399                         VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
 400                         VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
 401                 >;
 402         };
 403
 404         pinctrl_fec1: fec1grp {
 405                 fsl,pins = <
 406                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30de
 407                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30df
 408                         VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
 409                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30dd
 410                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30dd
 411                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30dd
 412                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30de
 413                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30de
 414                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30de
 415                 >;
 416         };
 417
 418         pinctrl_gpio_leds: gpioledsgrp {
 419                 fsl,pins = <
 420                         /* Heart bit LED */
 421                         VF610_PAD_PTE12__GPIO_117       0x1183
 422                         /* LEDS */
 423                         VF610_PAD_PTE15__GPIO_120       0x1183
 424                         VF610_PAD_PTA12__GPIO_5 0x1183
 425                         VF610_PAD_PTA16__GPIO_6 0x1183
 426                         VF610_PAD_PTE9__GPIO_114        0x1183
 427                         VF610_PAD_PTE20__GPIO_125       0x1183
 428                         VF610_PAD_PTE23__GPIO_128       0x1183
 429                         VF610_PAD_PTE16__GPIO_121       0x1183
 430                 >;
 431         };
 432
 433         pinctrl_i2c2: i2c2grp {
 434                 fsl,pins = <
 435                         VF610_PAD_PTA22__I2C2_SCL               0x34df
 436                         VF610_PAD_PTA23__I2C2_SDA               0x34df
 437                 >;
 438         };
 439
 440         pinctrl_nfc: nfcgrp {
 441                 fsl,pins = <
 442                         VF610_PAD_PTD23__NF_IO7         0x28df
 443                         VF610_PAD_PTD22__NF_IO6         0x28df
 444                         VF610_PAD_PTD21__NF_IO5         0x28df
 445                         VF610_PAD_PTD20__NF_IO4         0x28df
 446                         VF610_PAD_PTD19__NF_IO3         0x28df
 447                         VF610_PAD_PTD18__NF_IO2         0x28df
 448                         VF610_PAD_PTD17__NF_IO1         0x28df
 449                         VF610_PAD_PTD16__NF_IO0         0x28df
 450                         VF610_PAD_PTB24__NF_WE_B                0x28c2
 451                         VF610_PAD_PTB25__NF_CE0_B               0x28c2
 452                         VF610_PAD_PTB27__NF_RE_B                0x28c2
 453                         VF610_PAD_PTC26__NF_RB_B                0x283d
 454                         VF610_PAD_PTC27__NF_ALE         0x28c2
 455                         VF610_PAD_PTC28__NF_CLE         0x28c2
 456                 >;
 457         };
 458
 459         pinctrl_qspi0: qspi0grp {
 460                 fsl,pins = <
 461                         VF610_PAD_PTD0__QSPI0_A_QSCK    0x397f
 462                         VF610_PAD_PTD1__QSPI0_A_CS0     0x397f
 463                         VF610_PAD_PTD2__QSPI0_A_DATA3   0x397f
 464                         VF610_PAD_PTD3__QSPI0_A_DATA2   0x397f
 465                         VF610_PAD_PTD4__QSPI0_A_DATA1   0x397f
 466                         VF610_PAD_PTD5__QSPI0_A_DATA0   0x397f
 467                         VF610_PAD_PTD7__QSPI0_B_QSCK    0x397f
 468                         VF610_PAD_PTD8__QSPI0_B_CS0     0x397f
 469                         VF610_PAD_PTD11__QSPI0_B_DATA1  0x397f
 470                         VF610_PAD_PTD12__QSPI0_B_DATA0  0x397f
 471                 >;
 472         };
 473
 474         pinctrl_uart0: uart0grp {
 475                 fsl,pins = <
 476                         VF610_PAD_PTB10__UART0_TX               0x21a2
 477                         VF610_PAD_PTB11__UART0_RX               0x21a1
 478                 >;
 479         };
 480
 481         pinctrl_uart1: uart1grp {
 482                 fsl,pins = <
 483                         VF610_PAD_PTB4__UART1_TX                0x21a2
 484                         VF610_PAD_PTB5__UART1_RX                0x21a1
 485                 >;
 486         };
 487
 488         pinctrl_uart2: uart2grp {
 489                 fsl,pins = <
 490                         VF610_PAD_PTB6__UART2_TX                0x21a2
 491                         VF610_PAD_PTB7__UART2_RX                0x21a1
 492                 >;
 493         };
 494
 495         pinctrl_uart3: uart3grp {
 496                 fsl,pins = <
 497                         VF610_PAD_PTA20__UART3_TX               0x21a2
 498                         VF610_PAD_PTA21__UART3_RX               0x21a1
 499                 >;
 500         };
 501 };