arch/arm/boot/dts/sun8i-r40.dtsi

   1 /*
   2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
   3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/clock/sun8i-de2.h>
  46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  48 #include <dt-bindings/reset/sun8i-de2.h>
  49
  50 / {
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         clocks {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 osc24M: osc24M {
  61                         #clock-cells = <0>;
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <24000000>;
  64                         clock-accuracy = <50000>;
  65                         clock-output-names = "osc24M";
  66                 };
  67
  68                 osc32k: osc32k {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                         clock-accuracy = <20000>;
  73                         clock-output-names = "ext-osc32k";
  74                 };
  75         };
  76
  77         cpus {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 cpu@0 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <0>;
  85                 };
  86
  87                 cpu@1 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <1>;
  91                 };
  92
  93                 cpu@2 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <2>;
  97                 };
  98
  99                 cpu@3 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <3>;
 103                 };
 104         };
 105
 106         de: display-engine {
 107                 compatible = "allwinner,sun8i-r40-display-engine";
 108                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 109                 status = "disabled";
 110         };
 111
 112         soc {
 113                 compatible = "simple-bus";
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 ranges;
 117
 118                 display_clocks: clock@1000000 {
 119                         compatible = "allwinner,sun8i-r40-de2-clk",
 120                                      "allwinner,sun8i-h3-de2-clk";
 121                         reg = <0x01000000 0x100000>;
 122                         clocks = <&ccu CLK_DE>,
 123                                  <&ccu CLK_BUS_DE>;
 124                         clock-names = "mod",
 125                                       "bus";
 126                         resets = <&ccu RST_BUS_DE>;
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129                 };
 130
 131                 mixer0: mixer@1100000 {
 132                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
 133                         reg = <0x01100000 0x100000>;
 134                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 135                                  <&display_clocks CLK_MIXER0>;
 136                         clock-names = "bus",
 137                                       "mod";
 138                         resets = <&display_clocks RST_MIXER0>;
 139
 140                         ports {
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143
 144                                 mixer0_out: port@1 {
 145                                         reg = <1>;
 146                                         mixer0_out_tcon_top: endpoint {
 147                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 148                                         };
 149                                 };
 150                         };
 151                 };
 152
 153                 mixer1: mixer@1200000 {
 154                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
 155                         reg = <0x01200000 0x100000>;
 156                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 157                                  <&display_clocks CLK_MIXER1>;
 158                         clock-names = "bus",
 159                                       "mod";
 160                         resets = <&display_clocks RST_WB>;
 161
 162                         ports {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165
 166                                 mixer1_out: port@1 {
 167                                         reg = <1>;
 168                                         mixer1_out_tcon_top: endpoint {
 169                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
 170                                         };
 171                                 };
 172                         };
 173                 };
 174
 175                 nmi_intc: interrupt-controller@1c00030 {
 176                         compatible = "allwinner,sun7i-a20-sc-nmi";
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                         reg = <0x01c00030 0x0c>;
 180                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 181                 };
 182
 183                 mmc0: mmc@1c0f000 {
 184                         compatible = "allwinner,sun8i-r40-mmc",
 185                                      "allwinner,sun50i-a64-mmc";
 186                         reg = <0x01c0f000 0x1000>;
 187                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 188                         clock-names = "ahb", "mmc";
 189                         resets = <&ccu RST_BUS_MMC0>;
 190                         reset-names = "ahb";
 191                         pinctrl-0 = <&mmc0_pins>;
 192                         pinctrl-names = "default";
 193                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 194                         status = "disabled";
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                 };
 198
 199                 mmc1: mmc@1c10000 {
 200                         compatible = "allwinner,sun8i-r40-mmc",
 201                                      "allwinner,sun50i-a64-mmc";
 202                         reg = <0x01c10000 0x1000>;
 203                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 204                         clock-names = "ahb", "mmc";
 205                         resets = <&ccu RST_BUS_MMC1>;
 206                         reset-names = "ahb";
 207                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 208                         status = "disabled";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                 };
 212
 213                 mmc2: mmc@1c11000 {
 214                         compatible = "allwinner,sun8i-r40-emmc",
 215                                      "allwinner,sun50i-a64-emmc";
 216                         reg = <0x01c11000 0x1000>;
 217                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 218                         clock-names = "ahb", "mmc";
 219                         resets = <&ccu RST_BUS_MMC2>;
 220                         reset-names = "ahb";
 221                         pinctrl-0 = <&mmc2_pins>;
 222                         pinctrl-names = "default";
 223                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 224                         status = "disabled";
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                 };
 228
 229                 mmc3: mmc@1c12000 {
 230                         compatible = "allwinner,sun8i-r40-mmc",
 231                                      "allwinner,sun50i-a64-mmc";
 232                         reg = <0x01c12000 0x1000>;
 233                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
 234                         clock-names = "ahb", "mmc";
 235                         resets = <&ccu RST_BUS_MMC3>;
 236                         reset-names = "ahb";
 237                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 238                         status = "disabled";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                 };
 242
 243                 usbphy: phy@1c13400 {
 244                         compatible = "allwinner,sun8i-r40-usb-phy";
 245                         reg = <0x01c13400 0x14>,
 246                               <0x01c14800 0x4>,
 247                               <0x01c19800 0x4>,
 248                               <0x01c1c800 0x4>;
 249                         reg-names = "phy_ctrl",
 250                                     "pmu0",
 251                                     "pmu1",
 252                                     "pmu2";
 253                         clocks = <&ccu CLK_USB_PHY0>,
 254                                  <&ccu CLK_USB_PHY1>,
 255                                  <&ccu CLK_USB_PHY2>;
 256                         clock-names = "usb0_phy",
 257                                       "usb1_phy",
 258                                       "usb2_phy";
 259                         resets = <&ccu RST_USB_PHY0>,
 260                                  <&ccu RST_USB_PHY1>,
 261                                  <&ccu RST_USB_PHY2>;
 262                         reset-names = "usb0_reset",
 263                                       "usb1_reset",
 264                                       "usb2_reset";
 265                         status = "disabled";
 266                         #phy-cells = <1>;
 267                 };
 268
 269                 ehci1: usb@1c19000 {
 270                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 271                         reg = <0x01c19000 0x100>;
 272                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 273                         clocks = <&ccu CLK_BUS_EHCI1>;
 274                         resets = <&ccu RST_BUS_EHCI1>;
 275                         phys = <&usbphy 1>;
 276                         status = "disabled";
 277                 };
 278
 279                 ohci1: usb@1c19400 {
 280                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 281                         reg = <0x01c19400 0x100>;
 282                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&ccu CLK_BUS_OHCI1>,
 284                                  <&ccu CLK_USB_OHCI1>;
 285                         resets = <&ccu RST_BUS_OHCI1>;
 286                         phys = <&usbphy 1>;
 287                         status = "disabled";
 288                 };
 289
 290                 ehci2: usb@1c1c000 {
 291                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 292                         reg = <0x01c1c000 0x100>;
 293                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&ccu CLK_BUS_EHCI2>;
 295                         resets = <&ccu RST_BUS_EHCI2>;
 296                         phys = <&usbphy 2>;
 297                         status = "disabled";
 298                 };
 299
 300                 ohci2: usb@1c1c400 {
 301                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 302                         reg = <0x01c1c400 0x100>;
 303                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&ccu CLK_BUS_OHCI2>,
 305                                  <&ccu CLK_USB_OHCI2>;
 306                         resets = <&ccu RST_BUS_OHCI2>;
 307                         phys = <&usbphy 2>;
 308                         status = "disabled";
 309                 };
 310
 311                 ccu: clock@1c20000 {
 312                         compatible = "allwinner,sun8i-r40-ccu";
 313                         reg = <0x01c20000 0x400>;
 314                         clocks = <&osc24M>, <&rtc 0>;
 315                         clock-names = "hosc", "losc";
 316                         #clock-cells = <1>;
 317                         #reset-cells = <1>;
 318                 };
 319
 320                 rtc: rtc@1c20400 {
 321                         compatible = "allwinner,sun8i-r40-rtc",
 322                                      "allwinner,sun8i-h3-rtc";
 323                         reg = <0x01c20400 0x400>;
 324                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 325                         clock-output-names = "osc32k", "osc32k-out";
 326                         clocks = <&osc32k>;
 327                         #clock-cells = <1>;
 328                 };
 329
 330                 pio: pinctrl@1c20800 {
 331                         compatible = "allwinner,sun8i-r40-pinctrl";
 332                         reg = <0x01c20800 0x400>;
 333                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 335                         clock-names = "apb", "hosc", "losc";
 336                         gpio-controller;
 337                         interrupt-controller;
 338                         #interrupt-cells = <3>;
 339                         #gpio-cells = <3>;
 340
 341                         clk_out_a_pin: clk-out-a-pin {
 342                                 pins = "PI12";
 343                                 function = "clk_out_a";
 344                         };
 345
 346                         gmac_rgmii_pins: gmac-rgmii-pins {
 347                                 pins = "PA0", "PA1", "PA2", "PA3",
 348                                        "PA4", "PA5", "PA6", "PA7",
 349                                        "PA8", "PA10", "PA11", "PA12",
 350                                        "PA13", "PA15", "PA16";
 351                                 function = "gmac";
 352                                 /*
 353                                  * data lines in RGMII mode use DDR mode
 354                                  * and need a higher signal drive strength
 355                                  */
 356                                 drive-strength = <40>;
 357                         };
 358
 359                         i2c0_pins: i2c0-pins {
 360                                 pins = "PB0", "PB1";
 361                                 function = "i2c0";
 362                         };
 363
 364                         mmc0_pins: mmc0-pins {
 365                                 pins = "PF0", "PF1", "PF2",
 366                                        "PF3", "PF4", "PF5";
 367                                 function = "mmc0";
 368                                 drive-strength = <30>;
 369                                 bias-pull-up;
 370                         };
 371
 372                         mmc1_pg_pins: mmc1-pg-pins {
 373                                 pins = "PG0", "PG1", "PG2",
 374                                        "PG3", "PG4", "PG5";
 375                                 function = "mmc1";
 376                                 drive-strength = <30>;
 377                                 bias-pull-up;
 378                         };
 379
 380                         mmc2_pins: mmc2-pins {
 381                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
 382                                        "PC10", "PC11", "PC12", "PC13", "PC14",
 383                                        "PC15", "PC24";
 384                                 function = "mmc2";
 385                                 drive-strength = <30>;
 386                                 bias-pull-up;
 387                         };
 388
 389                         uart0_pb_pins: uart0-pb-pins {
 390                                 pins = "PB22", "PB23";
 391                                 function = "uart0";
 392                         };
 393
 394                         uart3_pg_pins: uart3-pg-pins {
 395                                 pins = "PG6", "PG7";
 396                                 function = "uart3";
 397                         };
 398
 399                         uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 400                                 pins = "PG8", "PG9";
 401                                 function = "uart3";
 402                         };
 403                 };
 404
 405                 wdt: watchdog@1c20c90 {
 406                         compatible = "allwinner,sun4i-a10-wdt";
 407                         reg = <0x01c20c90 0x10>;
 408                 };
 409
 410                 uart0: serial@1c28000 {
 411                         compatible = "snps,dw-apb-uart";
 412                         reg = <0x01c28000 0x400>;
 413                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 414                         reg-shift = <2>;
 415                         reg-io-width = <4>;
 416                         clocks = <&ccu CLK_BUS_UART0>;
 417                         resets = <&ccu RST_BUS_UART0>;
 418                         status = "disabled";
 419                 };
 420
 421                 uart1: serial@1c28400 {
 422                         compatible = "snps,dw-apb-uart";
 423                         reg = <0x01c28400 0x400>;
 424                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 425                         reg-shift = <2>;
 426                         reg-io-width = <4>;
 427                         clocks = <&ccu CLK_BUS_UART1>;
 428                         resets = <&ccu RST_BUS_UART1>;
 429                         status = "disabled";
 430                 };
 431
 432                 uart2: serial@1c28800 {
 433                         compatible = "snps,dw-apb-uart";
 434                         reg = <0x01c28800 0x400>;
 435                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 436                         reg-shift = <2>;
 437                         reg-io-width = <4>;
 438                         clocks = <&ccu CLK_BUS_UART2>;
 439                         resets = <&ccu RST_BUS_UART2>;
 440                         status = "disabled";
 441                 };
 442
 443                 uart3: serial@1c28c00 {
 444                         compatible = "snps,dw-apb-uart";
 445                         reg = <0x01c28c00 0x400>;
 446                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 447                         reg-shift = <2>;
 448                         reg-io-width = <4>;
 449                         clocks = <&ccu CLK_BUS_UART3>;
 450                         resets = <&ccu RST_BUS_UART3>;
 451                         status = "disabled";
 452                 };
 453
 454                 uart4: serial@1c29000 {
 455                         compatible = "snps,dw-apb-uart";
 456                         reg = <0x01c29000 0x400>;
 457                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 458                         reg-shift = <2>;
 459                         reg-io-width = <4>;
 460                         clocks = <&ccu CLK_BUS_UART4>;
 461                         resets = <&ccu RST_BUS_UART4>;
 462                         status = "disabled";
 463                 };
 464
 465                 uart5: serial@1c29400 {
 466                         compatible = "snps,dw-apb-uart";
 467                         reg = <0x01c29400 0x400>;
 468                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 469                         reg-shift = <2>;
 470                         reg-io-width = <4>;
 471                         clocks = <&ccu CLK_BUS_UART5>;
 472                         resets = <&ccu RST_BUS_UART5>;
 473                         status = "disabled";
 474                 };
 475
 476                 uart6: serial@1c29800 {
 477                         compatible = "snps,dw-apb-uart";
 478                         reg = <0x01c29800 0x400>;
 479                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 480                         reg-shift = <2>;
 481                         reg-io-width = <4>;
 482                         clocks = <&ccu CLK_BUS_UART6>;
 483                         resets = <&ccu RST_BUS_UART6>;
 484                         status = "disabled";
 485                 };
 486
 487                 uart7: serial@1c29c00 {
 488                         compatible = "snps,dw-apb-uart";
 489                         reg = <0x01c29c00 0x400>;
 490                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 491                         reg-shift = <2>;
 492                         reg-io-width = <4>;
 493                         clocks = <&ccu CLK_BUS_UART7>;
 494                         resets = <&ccu RST_BUS_UART7>;
 495                         status = "disabled";
 496                 };
 497
 498                 i2c0: i2c@1c2ac00 {
 499                         compatible = "allwinner,sun6i-a31-i2c";
 500                         reg = <0x01c2ac00 0x400>;
 501                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&ccu CLK_BUS_I2C0>;
 503                         resets = <&ccu RST_BUS_I2C0>;
 504                         pinctrl-0 = <&i2c0_pins>;
 505                         pinctrl-names = "default";
 506                         status = "disabled";
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                 };
 510
 511                 i2c1: i2c@1c2b000 {
 512                         compatible = "allwinner,sun6i-a31-i2c";
 513                         reg = <0x01c2b000 0x400>;
 514                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&ccu CLK_BUS_I2C1>;
 516                         resets = <&ccu RST_BUS_I2C1>;
 517                         status = "disabled";
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                 };
 521
 522                 i2c2: i2c@1c2b400 {
 523                         compatible = "allwinner,sun6i-a31-i2c";
 524                         reg = <0x01c2b400 0x400>;
 525                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&ccu CLK_BUS_I2C2>;
 527                         resets = <&ccu RST_BUS_I2C2>;
 528                         status = "disabled";
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                 };
 532
 533                 i2c3: i2c@1c2b800 {
 534                         compatible = "allwinner,sun6i-a31-i2c";
 535                         reg = <0x01c2b800 0x400>;
 536                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&ccu CLK_BUS_I2C3>;
 538                         resets = <&ccu RST_BUS_I2C3>;
 539                         status = "disabled";
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                 };
 543
 544                 i2c4: i2c@1c2c000 {
 545                         compatible = "allwinner,sun6i-a31-i2c";
 546                         reg = <0x01c2c000 0x400>;
 547                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&ccu CLK_BUS_I2C4>;
 549                         resets = <&ccu RST_BUS_I2C4>;
 550                         status = "disabled";
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                 };
 554
 555                 ahci: sata@1c18000 {
 556                         compatible = "allwinner,sun8i-r40-ahci";
 557                         reg = <0x01c18000 0x1000>;
 558                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 559                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
 560                         resets = <&ccu RST_BUS_SATA>;
 561                         reset-names = "ahci";
 562                         status = "disabled";
 563
 564                 };
 565
 566                 gmac: ethernet@1c50000 {
 567                         compatible = "allwinner,sun8i-r40-gmac";
 568                         syscon = <&ccu>;
 569                         reg = <0x01c50000 0x10000>;
 570                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 571                         interrupt-names = "macirq";
 572                         resets = <&ccu RST_BUS_GMAC>;
 573                         reset-names = "stmmaceth";
 574                         clocks = <&ccu CLK_BUS_GMAC>;
 575                         clock-names = "stmmaceth";
 576                         status = "disabled";
 577
 578                         gmac_mdio: mdio {
 579                                 compatible = "snps,dwmac-mdio";
 580                                 #address-cells = <1>;
 581                                 #size-cells = <0>;
 582                         };
 583                 };
 584
 585                 tcon_top: tcon-top@1c70000 {
 586                         compatible = "allwinner,sun8i-r40-tcon-top";
 587                         reg = <0x01c70000 0x1000>;
 588                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 589                                  <&ccu CLK_TCON_TV0>,
 590                                  <&ccu CLK_TVE0>,
 591                                  <&ccu CLK_TCON_TV1>,
 592                                  <&ccu CLK_TVE1>,
 593                                  <&ccu CLK_DSI_DPHY>;
 594                         clock-names = "bus",
 595                                       "tcon-tv0",
 596                                       "tve0",
 597                                       "tcon-tv1",
 598                                       "tve1",
 599                                       "dsi";
 600                         clock-output-names = "tcon-top-tv0",
 601                                              "tcon-top-tv1",
 602                                              "tcon-top-dsi";
 603                         resets = <&ccu RST_BUS_TCON_TOP>;
 604                         #clock-cells = <1>;
 605
 606                         ports {
 607                                 #address-cells = <1>;
 608                                 #size-cells = <0>;
 609
 610                                 tcon_top_mixer0_in: port@0 {
 611                                         reg = <0>;
 612
 613                                         tcon_top_mixer0_in_mixer0: endpoint {
 614                                                 remote-endpoint = <&mixer0_out_tcon_top>;
 615                                         };
 616                                 };
 617
 618                                 tcon_top_mixer0_out: port@1 {
 619                                         #address-cells = <1>;
 620                                         #size-cells = <0>;
 621                                         reg = <1>;
 622
 623                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
 624                                                 reg = <0>;
 625                                         };
 626
 627                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
 628                                                 reg = <1>;
 629                                         };
 630
 631                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
 632                                                 reg = <2>;
 633                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
 634                                         };
 635
 636                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
 637                                                 reg = <3>;
 638                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
 639                                         };
 640                                 };
 641
 642                                 tcon_top_mixer1_in: port@2 {
 643                                         #address-cells = <1>;
 644                                         #size-cells = <0>;
 645                                         reg = <2>;
 646
 647                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
 648                                                 reg = <1>;
 649                                                 remote-endpoint = <&mixer1_out_tcon_top>;
 650                                         };
 651                                 };
 652
 653                                 tcon_top_mixer1_out: port@3 {
 654                                         #address-cells = <1>;
 655                                         #size-cells = <0>;
 656                                         reg = <3>;
 657
 658                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
 659                                                 reg = <0>;
 660                                         };
 661
 662                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
 663                                                 reg = <1>;
 664                                         };
 665
 666                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
 667                                                 reg = <2>;
 668                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
 669                                         };
 670
 671                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
 672                                                 reg = <3>;
 673                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
 674                                         };
 675                                 };
 676
 677                                 tcon_top_hdmi_in: port@4 {
 678                                         #address-cells = <1>;
 679                                         #size-cells = <0>;
 680                                         reg = <4>;
 681
 682                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
 683                                                 reg = <0>;
 684                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
 685                                         };
 686
 687                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
 688                                                 reg = <1>;
 689                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
 690                                         };
 691                                 };
 692
 693                                 tcon_top_hdmi_out: port@5 {
 694                                         reg = <5>;
 695
 696                                         tcon_top_hdmi_out_hdmi: endpoint {
 697                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 698                                         };
 699                                 };
 700                         };
 701                 };
 702
 703                 tcon_tv0: lcd-controller@1c73000 {
 704                         compatible = "allwinner,sun8i-r40-tcon-tv";
 705                         reg = <0x01c73000 0x1000>;
 706                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
 708                         clock-names = "ahb", "tcon-ch1";
 709                         resets = <&ccu RST_BUS_TCON_TV0>;
 710                         reset-names = "lcd";
 711                         status = "disabled";
 712
 713                         ports {
 714                                 #address-cells = <1>;
 715                                 #size-cells = <0>;
 716
 717                                 tcon_tv0_in: port@0 {
 718                                         #address-cells = <1>;
 719                                         #size-cells = <0>;
 720                                         reg = <0>;
 721
 722                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
 723                                                 reg = <0>;
 724                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
 725                                         };
 726
 727                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
 728                                                 reg = <1>;
 729                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
 730                                         };
 731                                 };
 732
 733                                 tcon_tv0_out: port@1 {
 734                                         #address-cells = <1>;
 735                                         #size-cells = <0>;
 736                                         reg = <1>;
 737
 738                                         tcon_tv0_out_tcon_top: endpoint@1 {
 739                                                 reg = <1>;
 740                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
 741                                         };
 742                                 };
 743                         };
 744                 };
 745
 746                 tcon_tv1: lcd-controller@1c74000 {
 747                         compatible = "allwinner,sun8i-r40-tcon-tv";
 748                         reg = <0x01c74000 0x1000>;
 749                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 750                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
 751                         clock-names = "ahb", "tcon-ch1";
 752                         resets = <&ccu RST_BUS_TCON_TV1>;
 753                         reset-names = "lcd";
 754                         status = "disabled";
 755
 756                         ports {
 757                                 #address-cells = <1>;
 758                                 #size-cells = <0>;
 759
 760                                 tcon_tv1_in: port@0 {
 761                                         #address-cells = <1>;
 762                                         #size-cells = <0>;
 763                                         reg = <0>;
 764
 765                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
 766                                                 reg = <0>;
 767                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
 768                                         };
 769
 770                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
 771                                                 reg = <1>;
 772                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
 773                                         };
 774                                 };
 775
 776                                 tcon_tv1_out: port@1 {
 777                                         #address-cells = <1>;
 778                                         #size-cells = <0>;
 779                                         reg = <1>;
 780
 781                                         tcon_tv1_out_tcon_top: endpoint@1 {
 782                                                 reg = <1>;
 783                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
 784                                         };
 785                                 };
 786                         };
 787                 };
 788
 789                 gic: interrupt-controller@1c81000 {
 790                         compatible = "arm,gic-400";
 791                         reg = <0x01c81000 0x1000>,
 792                               <0x01c82000 0x1000>,
 793                               <0x01c84000 0x2000>,
 794                               <0x01c86000 0x2000>;
 795                         interrupt-controller;
 796                         #interrupt-cells = <3>;
 797                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 798                 };
 799
 800                 hdmi: hdmi@1ee0000 {
 801                         compatible = "allwinner,sun8i-r40-dw-hdmi",
 802                                      "allwinner,sun8i-a83t-dw-hdmi";
 803                         reg = <0x01ee0000 0x10000>;
 804                         reg-io-width = <1>;
 805                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 806                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
 807                                  <&ccu CLK_HDMI>;
 808                         clock-names = "iahb", "isfr", "tmds";
 809                         resets = <&ccu RST_BUS_HDMI1>;
 810                         reset-names = "ctrl";
 811                         phys = <&hdmi_phy>;
 812                         phy-names = "hdmi-phy";
 813                         status = "disabled";
 814
 815                         ports {
 816                                 #address-cells = <1>;
 817                                 #size-cells = <0>;
 818
 819                                 hdmi_in: port@0 {
 820                                         reg = <0>;
 821
 822                                         hdmi_in_tcon_top: endpoint {
 823                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 824                                         };
 825                                 };
 826
 827                                 hdmi_out: port@1 {
 828                                         reg = <1>;
 829                                 };
 830                         };
 831                 };
 832
 833                 hdmi_phy: hdmi-phy@1ef0000 {
 834                         compatible = "allwinner,sun8i-r40-hdmi-phy";
 835                         reg = <0x01ef0000 0x10000>;
 836                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
 837                                  <&ccu 7>, <&ccu 16>;
 838                         clock-names = "bus", "mod", "pll-0", "pll-1";
 839                         resets = <&ccu RST_BUS_HDMI0>;
 840                         reset-names = "phy";
 841                         #phy-cells = <0>;
 842                 };
 843         };
 844
 845         timer {
 846                 compatible = "arm,armv7-timer";
 847                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 848                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 849                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 850                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 851         };
 852 };