2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "skeleton.dtsi"
49 #include "armv7-m.dtsi"
50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
51 #include <dt-bindings/clock/stm32fx-clock.h>
52 #include <dt-bindings/mfd/stm32f4-rcc.h>
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
70 compatible = "fixed-clock";
71 clock-frequency = <32000>;
74 clk_i2s_ckin: i2s-ckin {
76 compatible = "fixed-clock";
77 clock-frequency = <0>;
82 timer2: timer@40000000 {
83 compatible = "st,stm32-timer";
84 reg = <0x40000000 0x400>;
86 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 timers2: timers@40000000 {
93 compatible = "st,stm32-timers";
94 reg = <0x40000000 0x400>;
95 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
100 compatible = "st,stm32-pwm";
105 compatible = "st,stm32-timer-trigger";
111 timer3: timer@40000400 {
112 compatible = "st,stm32-timer";
113 reg = <0x40000400 0x400>;
115 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 timers3: timers@40000400 {
120 #address-cells = <1>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000400 0x400>;
124 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
129 compatible = "st,stm32-pwm";
134 compatible = "st,stm32-timer-trigger";
140 timer4: timer@40000800 {
141 compatible = "st,stm32-timer";
142 reg = <0x40000800 0x400>;
144 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 timers4: timers@40000800 {
149 #address-cells = <1>;
151 compatible = "st,stm32-timers";
152 reg = <0x40000800 0x400>;
153 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
158 compatible = "st,stm32-pwm";
163 compatible = "st,stm32-timer-trigger";
169 timer5: timer@40000c00 {
170 compatible = "st,stm32-timer";
171 reg = <0x40000c00 0x400>;
173 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 timers5: timers@40000c00 {
177 #address-cells = <1>;
179 compatible = "st,stm32-timers";
180 reg = <0x40000C00 0x400>;
181 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
186 compatible = "st,stm32-pwm";
191 compatible = "st,stm32-timer-trigger";
197 timer6: timer@40001000 {
198 compatible = "st,stm32-timer";
199 reg = <0x40001000 0x400>;
201 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 timers6: timers@40001000 {
206 #address-cells = <1>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
210 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
215 compatible = "st,stm32-timer-trigger";
221 timer7: timer@40001400 {
222 compatible = "st,stm32-timer";
223 reg = <0x40001400 0x400>;
225 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
229 timers7: timers@40001400 {
230 #address-cells = <1>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
234 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
239 compatible = "st,stm32-timer-trigger";
245 timers12: timers@40001800 {
246 #address-cells = <1>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
250 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
255 compatible = "st,stm32-pwm";
260 compatible = "st,stm32-timer-trigger";
266 timers13: timers@40001c00 {
267 #address-cells = <1>;
269 compatible = "st,stm32-timers";
270 reg = <0x40001C00 0x400>;
271 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
276 compatible = "st,stm32-pwm";
281 timers14: timers@40002000 {
282 #address-cells = <1>;
284 compatible = "st,stm32-timers";
285 reg = <0x40002000 0x400>;
286 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
291 compatible = "st,stm32-pwm";
297 compatible = "st,stm32-rtc";
298 reg = <0x40002800 0x400>;
299 clocks = <&rcc 1 CLK_RTC>;
300 clock-names = "ck_rtc";
301 assigned-clocks = <&rcc 1 CLK_RTC>;
302 assigned-clock-parents = <&rcc 1 CLK_LSE>;
303 interrupt-parent = <&exti>;
305 interrupt-names = "alarm";
306 st,syscfg = <&pwrcfg>;
310 iwdg: watchdog@40003000 {
311 compatible = "st,stm32-iwdg";
312 reg = <0x40003000 0x400>;
317 usart2: serial@40004400 {
318 compatible = "st,stm32-usart", "st,stm32-uart";
319 reg = <0x40004400 0x400>;
321 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
325 usart3: serial@40004800 {
326 compatible = "st,stm32-usart", "st,stm32-uart";
327 reg = <0x40004800 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
331 dmas = <&dma1 1 4 0x400 0x0>,
332 <&dma1 3 4 0x400 0x0>;
333 dma-names = "rx", "tx";
336 usart4: serial@40004c00 {
337 compatible = "st,stm32-uart";
338 reg = <0x40004c00 0x400>;
340 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
344 usart5: serial@40005000 {
345 compatible = "st,stm32-uart";
346 reg = <0x40005000 0x400>;
348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
353 compatible = "st,stm32f4-i2c";
354 reg = <0x40005400 0x400>;
357 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
358 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
359 #address-cells = <1>;
365 compatible = "st,stm32f4-dac-core";
366 reg = <0x40007400 0x400>;
367 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
368 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
369 clock-names = "pclk";
370 #address-cells = <1>;
375 compatible = "st,stm32-dac";
376 #io-channels-cells = <1>;
382 compatible = "st,stm32-dac";
383 #io-channels-cells = <1>;
389 usart7: serial@40007800 {
390 compatible = "st,stm32-usart", "st,stm32-uart";
391 reg = <0x40007800 0x400>;
393 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
397 usart8: serial@40007c00 {
398 compatible = "st,stm32-usart", "st,stm32-uart";
399 reg = <0x40007c00 0x400>;
401 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
405 timers1: timers@40010000 {
406 #address-cells = <1>;
408 compatible = "st,stm32-timers";
409 reg = <0x40010000 0x400>;
410 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
415 compatible = "st,stm32-pwm";
420 compatible = "st,stm32-timer-trigger";
426 timers8: timers@40010400 {
427 #address-cells = <1>;
429 compatible = "st,stm32-timers";
430 reg = <0x40010400 0x400>;
431 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
436 compatible = "st,stm32-pwm";
441 compatible = "st,stm32-timer-trigger";
447 usart1: serial@40011000 {
448 compatible = "st,stm32-usart", "st,stm32-uart";
449 reg = <0x40011000 0x400>;
451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
453 dmas = <&dma2 2 4 0x400 0x0>,
454 <&dma2 7 4 0x400 0x0>;
455 dma-names = "rx", "tx";
458 usart6: serial@40011400 {
459 compatible = "st,stm32-usart", "st,stm32-uart";
460 reg = <0x40011400 0x400>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
467 compatible = "st,stm32f4-adc-core";
468 reg = <0x40012000 0x400>;
470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
472 interrupt-controller;
473 #interrupt-cells = <1>;
474 #address-cells = <1>;
479 compatible = "st,stm32f4-adc";
480 #io-channel-cells = <1>;
482 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
483 interrupt-parent = <&adc>;
485 dmas = <&dma2 0 0 0x400 0x0>;
491 compatible = "st,stm32f4-adc";
492 #io-channel-cells = <1>;
494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
495 interrupt-parent = <&adc>;
497 dmas = <&dma2 3 1 0x400 0x0>;
503 compatible = "st,stm32f4-adc";
504 #io-channel-cells = <1>;
506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
507 interrupt-parent = <&adc>;
509 dmas = <&dma2 1 2 0x400 0x0>;
515 syscfg: system-config@40013800 {
516 compatible = "syscon";
517 reg = <0x40013800 0x400>;
520 exti: interrupt-controller@40013c00 {
521 compatible = "st,stm32-exti";
522 interrupt-controller;
523 #interrupt-cells = <2>;
524 reg = <0x40013C00 0x400>;
525 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
528 timers9: timers@40014000 {
529 #address-cells = <1>;
531 compatible = "st,stm32-timers";
532 reg = <0x40014000 0x400>;
533 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
538 compatible = "st,stm32-pwm";
543 compatible = "st,stm32-timer-trigger";
549 timers10: timers@40014400 {
550 #address-cells = <1>;
552 compatible = "st,stm32-timers";
553 reg = <0x40014400 0x400>;
554 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
559 compatible = "st,stm32-pwm";
564 timers11: timers@40014800 {
565 #address-cells = <1>;
567 compatible = "st,stm32-timers";
568 reg = <0x40014800 0x400>;
569 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
574 compatible = "st,stm32-pwm";
579 pwrcfg: power-config@40007000 {
580 compatible = "syscon";
581 reg = <0x40007000 0x400>;
584 ltdc: display-controller@40016800 {
585 compatible = "st,stm32-ltdc";
586 reg = <0x40016800 0x200>;
587 interrupts = <88>, <89>;
588 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
589 clocks = <&rcc 1 CLK_LCD>;
594 pinctrl: pin-controller {
595 #address-cells = <1>;
597 compatible = "st,stm32f429-pinctrl";
598 ranges = <0 0x40020000 0x3000>;
599 interrupt-parent = <&exti>;
600 st,syscfg = <&syscfg 0x8>;
603 gpioa: gpio@40020000 {
606 interrupt-controller;
607 #interrupt-cells = <2>;
609 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
610 st,bank-name = "GPIOA";
613 gpiob: gpio@40020400 {
616 interrupt-controller;
617 #interrupt-cells = <2>;
619 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
620 st,bank-name = "GPIOB";
623 gpioc: gpio@40020800 {
626 interrupt-controller;
627 #interrupt-cells = <2>;
629 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
630 st,bank-name = "GPIOC";
633 gpiod: gpio@40020c00 {
636 interrupt-controller;
637 #interrupt-cells = <2>;
639 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
640 st,bank-name = "GPIOD";
643 gpioe: gpio@40021000 {
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 reg = <0x1000 0x400>;
649 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
650 st,bank-name = "GPIOE";
653 gpiof: gpio@40021400 {
656 interrupt-controller;
657 #interrupt-cells = <2>;
658 reg = <0x1400 0x400>;
659 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
660 st,bank-name = "GPIOF";
663 gpiog: gpio@40021800 {
666 interrupt-controller;
667 #interrupt-cells = <2>;
668 reg = <0x1800 0x400>;
669 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
670 st,bank-name = "GPIOG";
673 gpioh: gpio@40021c00 {
676 interrupt-controller;
677 #interrupt-cells = <2>;
678 reg = <0x1c00 0x400>;
679 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
680 st,bank-name = "GPIOH";
683 gpioi: gpio@40022000 {
686 interrupt-controller;
687 #interrupt-cells = <2>;
688 reg = <0x2000 0x400>;
689 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
690 st,bank-name = "GPIOI";
693 gpioj: gpio@40022400 {
696 interrupt-controller;
697 #interrupt-cells = <2>;
698 reg = <0x2400 0x400>;
699 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
700 st,bank-name = "GPIOJ";
703 gpiok: gpio@40022800 {
706 interrupt-controller;
707 #interrupt-cells = <2>;
708 reg = <0x2800 0x400>;
709 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
710 st,bank-name = "GPIOK";
713 usart1_pins_a: usart1@0 {
715 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
721 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
726 usart3_pins_a: usart3@0 {
728 pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
734 pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
739 usbotg_fs_pins_a: usbotg_fs@0 {
741 pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
742 <STM32F429_PA11_FUNC_OTG_FS_DM>,
743 <STM32F429_PA12_FUNC_OTG_FS_DP>;
750 usbotg_fs_pins_b: usbotg_fs@1 {
752 pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
753 <STM32F429_PB14_FUNC_OTG_HS_DM>,
754 <STM32F429_PB15_FUNC_OTG_HS_DP>;
761 usbotg_hs_pins_a: usbotg_hs@0 {
763 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
764 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
765 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
766 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
767 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
768 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
769 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
770 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
771 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
772 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
773 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
774 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
781 ethernet_mii: mii@0 {
783 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
784 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
785 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
786 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
787 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
788 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
789 <STM32F429_PA2_FUNC_ETH_MDIO>,
790 <STM32F429_PC1_FUNC_ETH_MDC>,
791 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
792 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
793 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
794 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
795 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
796 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
801 adc3_in8_pin: adc@200 {
803 pinmux = <STM32F429_PF10_FUNC_ANALOG>;
809 pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
810 <STM32F429_PB13_FUNC_TIM1_CH1N>,
811 <STM32F429_PB12_FUNC_TIM1_BKIN>;
817 pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
818 <STM32F429_PB5_FUNC_TIM3_CH2>;
824 pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
825 <STM32F429_PB6_FUNC_I2C1_SCL>;
834 pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
835 <STM32F429_PI13_FUNC_LCD_VSYNC>,
836 <STM32F429_PI14_FUNC_LCD_CLK>,
837 <STM32F429_PI15_FUNC_LCD_R0>,
838 <STM32F429_PJ0_FUNC_LCD_R1>,
839 <STM32F429_PJ1_FUNC_LCD_R2>,
840 <STM32F429_PJ2_FUNC_LCD_R3>,
841 <STM32F429_PJ3_FUNC_LCD_R4>,
842 <STM32F429_PJ4_FUNC_LCD_R5>,
843 <STM32F429_PJ5_FUNC_LCD_R6>,
844 <STM32F429_PJ6_FUNC_LCD_R7>,
845 <STM32F429_PJ7_FUNC_LCD_G0>,
846 <STM32F429_PJ8_FUNC_LCD_G1>,
847 <STM32F429_PJ9_FUNC_LCD_G2>,
848 <STM32F429_PJ10_FUNC_LCD_G3>,
849 <STM32F429_PJ11_FUNC_LCD_G4>,
850 <STM32F429_PJ12_FUNC_LCD_B0>,
851 <STM32F429_PJ13_FUNC_LCD_B1>,
852 <STM32F429_PJ14_FUNC_LCD_B2>,
853 <STM32F429_PJ15_FUNC_LCD_B3>,
854 <STM32F429_PK0_FUNC_LCD_G5>,
855 <STM32F429_PK1_FUNC_LCD_G6>,
856 <STM32F429_PK2_FUNC_LCD_G7>,
857 <STM32F429_PK3_FUNC_LCD_B4>,
858 <STM32F429_PK4_FUNC_LCD_B5>,
859 <STM32F429_PK5_FUNC_LCD_B6>,
860 <STM32F429_PK6_FUNC_LCD_B7>,
861 <STM32F429_PK7_FUNC_LCD_DE>;
868 pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
869 <STM32F429_PB7_FUNC_DCMI_VSYNC>,
870 <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
871 <STM32F429_PC6_FUNC_DCMI_D0>,
872 <STM32F429_PC7_FUNC_DCMI_D1>,
873 <STM32F429_PC8_FUNC_DCMI_D2>,
874 <STM32F429_PC9_FUNC_DCMI_D3>,
875 <STM32F429_PC11_FUNC_DCMI_D4>,
876 <STM32F429_PD3_FUNC_DCMI_D5>,
877 <STM32F429_PB8_FUNC_DCMI_D6>,
878 <STM32F429_PE6_FUNC_DCMI_D7>,
879 <STM32F429_PC10_FUNC_DCMI_D8>,
880 <STM32F429_PC12_FUNC_DCMI_D9>,
881 <STM32F429_PD6_FUNC_DCMI_D10>,
882 <STM32F429_PD2_FUNC_DCMI_D11>;
891 compatible = "st,stm32f4-crc";
892 reg = <0x40023000 0x400>;
893 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
900 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
901 reg = <0x40023800 0x400>;
902 clocks = <&clk_hse>, <&clk_i2s_ckin>;
903 st,syscfg = <&pwrcfg>;
904 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
905 assigned-clock-rates = <1000000>;
908 dma1: dma-controller@40026000 {
909 compatible = "st,stm32-dma";
910 reg = <0x40026000 0x400>;
919 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
923 dma2: dma-controller@40026400 {
924 compatible = "st,stm32-dma";
925 reg = <0x40026400 0x400>;
934 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
939 mac: ethernet@40028000 {
940 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
941 reg = <0x40028000 0x8000>;
942 reg-names = "stmmaceth";
944 interrupt-names = "macirq";
945 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
946 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
947 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
948 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
949 st,syscon = <&syscfg 0x4>;
955 usbotg_hs: usb@40040000 {
956 compatible = "snps,dwc2";
957 reg = <0x40040000 0x40000>;
959 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
964 usbotg_fs: usb@50000000 {
965 compatible = "st,stm32f4x9-fsotg";
966 reg = <0x50000000 0x40000>;
968 clocks = <&rcc 0 39>;
973 dcmi: dcmi@50050000 {
974 compatible = "st,stm32-dcmi";
975 reg = <0x50050000 0x400>;
977 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
978 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
979 clock-names = "mclk";
980 pinctrl-names = "default";
981 pinctrl-0 = <&dcmi_pins>;
982 dmas = <&dma2 1 1 0x414 0x3>;
988 compatible = "st,stm32-rng";
989 reg = <0x50060800 0x400>;
991 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
998 clocks = <&rcc 1 SYSTICK>;