1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
12 model = "Qualcomm MSM8660";
13 compatible = "qcom,msm8660";
14 interrupt-parent = <&intc>;
21 compatible = "qcom,scorpion";
22 enable-method = "qcom,gcc-msm8660";
25 next-level-cache = <&L2>;
29 compatible = "qcom,scorpion";
30 enable-method = "qcom,gcc-msm8660";
33 next-level-cache = <&L2>;
43 device_type = "memory";
48 compatible = "qcom,scorpion-mp-pmu";
49 interrupts = <1 9 0x304>;
53 cxo_board: cxo-board-clk {
54 compatible = "fixed-clock";
56 clock-frequency = <19200000>;
57 clock-output-names = "cxo_board";
60 pxo_board: pxo-board-clk {
61 compatible = "fixed-clock";
63 clock-frequency = <27000000>;
64 clock-output-names = "pxo_board";
68 compatible = "fixed-clock";
70 clock-frequency = <32768>;
71 clock-output-names = "sleep_clk";
76 * These channels from the ADC are simply hardware monitors.
77 * That is why the ADC is referred to as "HKADC" - HouseKeeping
81 compatible = "iio-hwmon";
82 io-channels = <&xoadc 0x00 0x01>, /* Battery */
83 <&xoadc 0x00 0x02>, /* DC in (charger) */
84 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
85 <&xoadc 0x00 0x0b>, /* Die temperature */
86 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
87 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
88 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
95 compatible = "simple-bus";
97 intc: interrupt-controller@2080000 {
98 compatible = "qcom,msm-8660-qgic";
100 #interrupt-cells = <3>;
101 reg = < 0x02080000 0x1000 >,
102 < 0x02081000 0x1000 >;
106 compatible = "qcom,scss-timer", "qcom,msm-timer";
107 interrupts = <1 0 0x301>,
110 reg = <0x02000000 0x100>;
111 clock-frequency = <27000000>,
113 cpu-offset = <0x40000>;
116 tlmm: pinctrl@800000 {
117 compatible = "qcom,msm8660-pinctrl";
118 reg = <0x800000 0x4000>;
121 gpio-ranges = <&tlmm 0 0 173>;
123 interrupts = <0 16 0x4>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
129 gcc: clock-controller@900000 {
130 compatible = "qcom,gcc-msm8660";
132 #power-domain-cells = <1>;
134 reg = <0x900000 0x4000>;
135 clocks = <&pxo_board>, <&cxo_board>;
136 clock-names = "pxo", "cxo";
139 gsbi1: gsbi@16000000 {
140 compatible = "qcom,gsbi-v1.0.0";
142 reg = <0x16000000 0x100>;
143 clocks = <&gcc GSBI1_H_CLK>;
144 clock-names = "iface";
145 #address-cells = <1>;
149 syscon-tcsr = <&tcsr>;
153 gsbi1_spi: spi@16080000 {
154 compatible = "qcom,spi-qup-v1.1.1";
155 reg = <0x16080000 0x1000>;
156 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
158 clock-names = "core", "iface";
159 #address-cells = <1>;
165 gsbi3: gsbi@16200000 {
166 compatible = "qcom,gsbi-v1.0.0";
168 reg = <0x16200000 0x100>;
169 clocks = <&gcc GSBI3_H_CLK>;
170 clock-names = "iface";
171 #address-cells = <1>;
175 syscon-tcsr = <&tcsr>;
178 gsbi3_i2c: i2c@16280000 {
179 compatible = "qcom,i2c-qup-v1.1.1";
180 reg = <0x16280000 0x1000>;
181 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
183 clock-names = "core", "iface";
184 #address-cells = <1>;
190 gsbi6: gsbi@16500000 {
191 compatible = "qcom,gsbi-v1.0.0";
193 reg = <0x16500000 0x100>;
194 clocks = <&gcc GSBI6_H_CLK>;
195 clock-names = "iface";
196 #address-cells = <1>;
201 syscon-tcsr = <&tcsr>;
203 gsbi6_serial: serial@16540000 {
204 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
205 reg = <0x16540000 0x1000>,
207 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
209 clock-names = "core", "iface";
213 gsbi6_i2c: i2c@16580000 {
214 compatible = "qcom,i2c-qup-v1.1.1";
215 reg = <0x16580000 0x1000>;
216 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
218 clock-names = "core", "iface";
219 #address-cells = <1>;
225 gsbi7: gsbi@16600000 {
226 compatible = "qcom,gsbi-v1.0.0";
228 reg = <0x16600000 0x100>;
229 clocks = <&gcc GSBI7_H_CLK>;
230 clock-names = "iface";
231 #address-cells = <1>;
236 syscon-tcsr = <&tcsr>;
238 gsbi7_serial: serial@16640000 {
239 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
240 reg = <0x16640000 0x1000>,
242 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
244 clock-names = "core", "iface";
248 gsbi7_i2c: i2c@16680000 {
249 compatible = "qcom,i2c-qup-v1.1.1";
250 reg = <0x16680000 0x1000>;
251 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
253 clock-names = "core", "iface";
254 #address-cells = <1>;
260 gsbi8: gsbi@19800000 {
261 compatible = "qcom,gsbi-v1.0.0";
263 reg = <0x19800000 0x100>;
264 clocks = <&gcc GSBI8_H_CLK>;
265 clock-names = "iface";
266 #address-cells = <1>;
270 syscon-tcsr = <&tcsr>;
273 gsbi8_i2c: i2c@19880000 {
274 compatible = "qcom,i2c-qup-v1.1.1";
275 reg = <0x19880000 0x1000>;
276 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
278 clock-names = "core", "iface";
279 #address-cells = <1>;
285 gsbi12: gsbi@19c00000 {
286 compatible = "qcom,gsbi-v1.0.0";
288 reg = <0x19c00000 0x100>;
289 clocks = <&gcc GSBI12_H_CLK>;
290 clock-names = "iface";
291 #address-cells = <1>;
295 syscon-tcsr = <&tcsr>;
297 gsbi12_serial: serial@19c40000 {
298 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
299 reg = <0x19c40000 0x1000>,
301 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
303 clock-names = "core", "iface";
307 gsbi12_i2c: i2c@19c80000 {
308 compatible = "qcom,i2c-qup-v1.1.1";
309 reg = <0x19c80000 0x1000>;
310 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
312 clock-names = "core", "iface";
313 #address-cells = <1>;
319 ebi2: external-bus@1a100000 {
320 compatible = "qcom,msm8660-ebi2";
321 #address-cells = <2>;
323 ranges = <0 0x0 0x1a800000 0x00800000>,
324 <1 0x0 0x1b000000 0x00800000>,
325 <2 0x0 0x1b800000 0x00800000>,
326 <3 0x0 0x1d000000 0x08000000>,
327 <4 0x0 0x1c800000 0x00800000>,
328 <5 0x0 0x1c000000 0x00800000>;
329 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
330 reg-names = "ebi2", "xmem";
331 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
332 clock-names = "ebi2x", "ebi2";
337 compatible = "qcom,ssbi";
338 reg = <0x500000 0x1000>;
339 qcom,controller-type = "pmic-arbiter";
342 compatible = "qcom,pm8058";
343 interrupt-parent = <&tlmm>;
345 #interrupt-cells = <2>;
346 interrupt-controller;
347 #address-cells = <1>;
350 pm8058_gpio: gpio@150 {
351 compatible = "qcom,pm8058-gpio",
354 interrupt-controller;
355 #interrupt-cells = <2>;
357 gpio-ranges = <&pm8058_gpio 0 0 44>;
362 pm8058_mpps: mpps@50 {
363 compatible = "qcom,pm8058-mpp",
368 gpio-ranges = <&pm8058_mpps 0 0 12>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
374 compatible = "qcom,pm8058-pwrkey";
376 interrupt-parent = <&pm8058>;
377 interrupts = <50 1>, <51 1>;
382 pm8058_keypad: keypad@148 {
383 compatible = "qcom,pm8058-keypad";
385 interrupt-parent = <&pm8058>;
386 interrupts = <74 1>, <75 1>;
393 compatible = "qcom,pm8058-adc";
395 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
396 #address-cells = <2>;
398 #io-channel-cells = <2>;
400 vcoin: adc-channel@0 {
403 vbat: adc-channel@1 {
406 dcin: adc-channel@2 {
409 ichg: adc-channel@3 {
412 vph_pwr: adc-channel@4 {
415 usb_vbus: adc-channel@a {
418 die_temp: adc-channel@b {
421 ref_625mv: adc-channel@c {
424 ref_1250mv: adc-channel@d {
427 ref_325mv: adc-channel@e {
430 ref_muxoff: adc-channel@f {
436 compatible = "qcom,pm8058-rtc";
438 interrupt-parent = <&pm8058>;
444 compatible = "qcom,pm8058-vib";
448 pm8058_led48: led@48 {
449 compatible = "qcom,pm8058-keypad-led";
454 pm8058_led131: led@131 {
455 compatible = "qcom,pm8058-led";
460 pm8058_led132: led@132 {
461 compatible = "qcom,pm8058-led";
466 pm8058_led133: led@133 {
467 compatible = "qcom,pm8058-led";
475 l2cc: clock-controller@2082000 {
476 compatible = "qcom,kpss-gcc", "syscon";
477 reg = <0x02082000 0x1000>;
481 compatible = "qcom,rpm-msm8660";
482 reg = <0x00104000 0x1000>;
483 qcom,ipc = <&l2cc 0x8 2>;
485 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
486 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
487 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
488 interrupt-names = "ack", "err", "wakeup";
489 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
492 rpmcc: clock-controller {
493 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
495 clocks = <&pxo_board>;
500 compatible = "qcom,rpm-pm8901-regulators";
510 /* S0 and S1 Handled as SAW regulators by SPM */
515 pm8901_lvs0: lvs0 {};
516 pm8901_lvs1: lvs1 {};
517 pm8901_lvs2: lvs2 {};
518 pm8901_lvs3: lvs3 {};
524 compatible = "qcom,rpm-pm8058-regulators";
559 pm8058_lvs0: lvs0 {};
560 pm8058_lvs1: lvs1 {};
567 compatible = "simple-bus";
568 #address-cells = <1>;
571 sdcc1: mmc@12400000 {
573 compatible = "arm,pl18x", "arm,primecell";
574 arm,primecell-periphid = <0x00051180>;
575 reg = <0x12400000 0x8000>;
576 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "cmd_irq";
578 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
579 clock-names = "mclk", "apb_pclk";
581 max-frequency = <48000000>;
587 sdcc2: mmc@12140000 {
589 compatible = "arm,pl18x", "arm,primecell";
590 arm,primecell-periphid = <0x00051180>;
591 reg = <0x12140000 0x8000>;
592 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-names = "cmd_irq";
594 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
595 clock-names = "mclk", "apb_pclk";
597 max-frequency = <48000000>;
602 sdcc3: mmc@12180000 {
603 compatible = "arm,pl18x", "arm,primecell";
604 arm,primecell-periphid = <0x00051180>;
606 reg = <0x12180000 0x8000>;
607 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
608 interrupt-names = "cmd_irq";
609 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
610 clock-names = "mclk", "apb_pclk";
614 max-frequency = <48000000>;
618 sdcc4: mmc@121c0000 {
619 compatible = "arm,pl18x", "arm,primecell";
620 arm,primecell-periphid = <0x00051180>;
622 reg = <0x121c0000 0x8000>;
623 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "cmd_irq";
625 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
626 clock-names = "mclk", "apb_pclk";
628 max-frequency = <48000000>;
633 sdcc5: mmc@12200000 {
634 compatible = "arm,pl18x", "arm,primecell";
635 arm,primecell-periphid = <0x00051180>;
637 reg = <0x12200000 0x8000>;
638 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "cmd_irq";
640 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
641 clock-names = "mclk", "apb_pclk";
645 max-frequency = <48000000>;
649 tcsr: syscon@1a400000 {
650 compatible = "qcom,tcsr-msm8660", "syscon";
651 reg = <0x1a400000 0x100>;