arch/arm/boot/dts/nxp/imx/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          */
  17         chosen {};
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 mmc2 = &usdhc3;
  32                 mmc3 = &usdhc4;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usb0 = &usbotg1;
  43                 usb1 = &usbotg2;
  44                 usb2 = &usbh;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         compatible = "arm,cortex-a9";
  55                         device_type = "cpu";
  56                         reg = <0x0>;
  57                         next-level-cache = <&L2>;
  58                         operating-points =
  59                                 /* kHz    uV */
  60                                 <996000  1275000>,
  61                                 <792000  1175000>,
  62                                 <396000  975000>;
  63                         fsl,soc-operating-points =
  64                                 /* ARM kHz      SOC-PU uV */
  65                                 <996000         1225000>,
  66                                 <792000         1175000>,
  67                                 <396000         1175000>;
  68                         clock-latency = <61036>; /* two CLK32 periods */
  69                         #cooling-cells = <2>;
  70                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  71                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  72                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  73                         clock-names = "arm", "pll2_pfd2_396m", "step",
  74                                       "pll1_sw", "pll1_sys";
  75                         arm-supply = <&reg_arm>;
  76                         pu-supply = <&reg_pu>;
  77                         soc-supply = <&reg_soc>;
  78                         nvmem-cells = <&cpu_speed_grade>;
  79                         nvmem-cell-names = "speed_grade";
  80                 };
  81         };
  82
  83         clocks {
  84                 ckil {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89
  90                 osc {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <24000000>;
  94                 };
  95         };
  96
  97         pmu {
  98                 compatible = "arm,cortex-a9-pmu";
  99                 interrupt-parent = <&gpc>;
 100                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 101         };
 102
 103         usbphynop1: usbphynop1 {
 104                 compatible = "usb-nop-xceiv";
 105                 #phy-cells = <0>;
 106         };
 107
 108         soc {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 compatible = "simple-bus";
 112                 interrupt-parent = <&gpc>;
 113                 ranges;
 114
 115                 ocram: sram@900000 {
 116                         compatible = "mmio-sram";
 117                         reg = <0x00900000 0x20000>;
 118                         ranges = <0 0x00900000 0x20000>;
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 122                 };
 123
 124                 intc: interrupt-controller@a01000 {
 125                         compatible = "arm,cortex-a9-gic";
 126                         #interrupt-cells = <3>;
 127                         interrupt-controller;
 128                         reg = <0x00a01000 0x1000>,
 129                               <0x00a00100 0x100>;
 130                         interrupt-parent = <&intc>;
 131                 };
 132
 133                 L2: cache-controller@a02000 {
 134                         compatible = "arm,pl310-cache";
 135                         reg = <0x00a02000 0x1000>;
 136                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 137                         cache-unified;
 138                         cache-level = <2>;
 139                         arm,tag-latency = <4 2 3>;
 140                         arm,data-latency = <4 2 3>;
 141                 };
 142
 143                 aips1: bus@2000000 {
 144                         compatible = "fsl,aips-bus", "simple-bus";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         reg = <0x02000000 0x100000>;
 148                         ranges;
 149
 150                         spba: spba-bus@2000000 {
 151                                 compatible = "fsl,spba-bus", "simple-bus";
 152                                 #address-cells = <1>;
 153                                 #size-cells = <1>;
 154                                 reg = <0x02000000 0x40000>;
 155                                 ranges;
 156
 157                                 spdif: spdif@2004000 {
 158                                         compatible = "fsl,imx6sl-spdif",
 159                                                 "fsl,imx35-spdif";
 160                                         reg = <0x02004000 0x4000>;
 161                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 162                                         dmas = <&sdma 14 18 0>,
 163                                                 <&sdma 15 18 0>;
 164                                         dma-names = "rx", "tx";
 165                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 166                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 167                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 168                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 169                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 170                                         clock-names = "core", "rxtx0",
 171                                                 "rxtx1", "rxtx2",
 172                                                 "rxtx3", "rxtx4",
 173                                                 "rxtx5", "rxtx6",
 174                                                 "rxtx7", "spba";
 175                                         status = "disabled";
 176                                 };
 177
 178                                 ecspi1: spi@2008000 {
 179                                         #address-cells = <1>;
 180                                         #size-cells = <0>;
 181                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 182                                         reg = <0x02008000 0x4000>;
 183                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 184                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 185                                                  <&clks IMX6SL_CLK_ECSPI1>;
 186                                         clock-names = "ipg", "per";
 187                                         status = "disabled";
 188                                 };
 189
 190                                 ecspi2: spi@200c000 {
 191                                         #address-cells = <1>;
 192                                         #size-cells = <0>;
 193                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 194                                         reg = <0x0200c000 0x4000>;
 195                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 196                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 197                                                  <&clks IMX6SL_CLK_ECSPI2>;
 198                                         clock-names = "ipg", "per";
 199                                         status = "disabled";
 200                                 };
 201
 202                                 ecspi3: spi@2010000 {
 203                                         #address-cells = <1>;
 204                                         #size-cells = <0>;
 205                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 206                                         reg = <0x02010000 0x4000>;
 207                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 208                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 209                                                  <&clks IMX6SL_CLK_ECSPI3>;
 210                                         clock-names = "ipg", "per";
 211                                         status = "disabled";
 212                                 };
 213
 214                                 ecspi4: spi@2014000 {
 215                                         #address-cells = <1>;
 216                                         #size-cells = <0>;
 217                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 218                                         reg = <0x02014000 0x4000>;
 219                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 220                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 221                                                  <&clks IMX6SL_CLK_ECSPI4>;
 222                                         clock-names = "ipg", "per";
 223                                         status = "disabled";
 224                                 };
 225
 226                                 uart5: serial@2018000 {
 227                                         compatible = "fsl,imx6sl-uart",
 228                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 229                                         reg = <0x02018000 0x4000>;
 230                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 231                                         clocks = <&clks IMX6SL_CLK_UART>,
 232                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 233                                         clock-names = "ipg", "per";
 234                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 235                                         dma-names = "rx", "tx";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 uart1: serial@2020000 {
 240                                         compatible = "fsl,imx6sl-uart",
 241                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 242                                         reg = <0x02020000 0x4000>;
 243                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 244                                         clocks = <&clks IMX6SL_CLK_UART>,
 245                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 246                                         clock-names = "ipg", "per";
 247                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 248                                         dma-names = "rx", "tx";
 249                                         status = "disabled";
 250                                 };
 251
 252                                 uart2: serial@2024000 {
 253                                         compatible = "fsl,imx6sl-uart",
 254                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 255                                         reg = <0x02024000 0x4000>;
 256                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 257                                         clocks = <&clks IMX6SL_CLK_UART>,
 258                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 259                                         clock-names = "ipg", "per";
 260                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 261                                         dma-names = "rx", "tx";
 262                                         status = "disabled";
 263                                 };
 264
 265                                 ssi1: ssi@2028000 {
 266                                         #sound-dai-cells = <0>;
 267                                         compatible = "fsl,imx6sl-ssi",
 268                                                         "fsl,imx51-ssi";
 269                                         reg = <0x02028000 0x4000>;
 270                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 271                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 272                                                  <&clks IMX6SL_CLK_SSI1>;
 273                                         clock-names = "ipg", "baud";
 274                                         dmas = <&sdma 37 1 0>,
 275                                                <&sdma 38 1 0>;
 276                                         dma-names = "rx", "tx";
 277                                         fsl,fifo-depth = <15>;
 278                                         status = "disabled";
 279                                 };
 280
 281                                 ssi2: ssi@202c000 {
 282                                         #sound-dai-cells = <0>;
 283                                         compatible = "fsl,imx6sl-ssi",
 284                                                         "fsl,imx51-ssi";
 285                                         reg = <0x0202c000 0x4000>;
 286                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 287                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 288                                                  <&clks IMX6SL_CLK_SSI2>;
 289                                         clock-names = "ipg", "baud";
 290                                         dmas = <&sdma 41 1 0>,
 291                                                <&sdma 42 1 0>;
 292                                         dma-names = "rx", "tx";
 293                                         fsl,fifo-depth = <15>;
 294                                         status = "disabled";
 295                                 };
 296
 297                                 ssi3: ssi@2030000 {
 298                                         #sound-dai-cells = <0>;
 299                                         compatible = "fsl,imx6sl-ssi",
 300                                                         "fsl,imx51-ssi";
 301                                         reg = <0x02030000 0x4000>;
 302                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 303                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 304                                                  <&clks IMX6SL_CLK_SSI3>;
 305                                         clock-names = "ipg", "baud";
 306                                         dmas = <&sdma 45 1 0>,
 307                                                <&sdma 46 1 0>;
 308                                         dma-names = "rx", "tx";
 309                                         fsl,fifo-depth = <15>;
 310                                         status = "disabled";
 311                                 };
 312
 313                                 uart3: serial@2034000 {
 314                                         compatible = "fsl,imx6sl-uart",
 315                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 316                                         reg = <0x02034000 0x4000>;
 317                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 318                                         clocks = <&clks IMX6SL_CLK_UART>,
 319                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 320                                         clock-names = "ipg", "per";
 321                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 322                                         dma-names = "rx", "tx";
 323                                         status = "disabled";
 324                                 };
 325
 326                                 uart4: serial@2038000 {
 327                                         compatible = "fsl,imx6sl-uart",
 328                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 329                                         reg = <0x02038000 0x4000>;
 330                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 331                                         clocks = <&clks IMX6SL_CLK_UART>,
 332                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 333                                         clock-names = "ipg", "per";
 334                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 335                                         dma-names = "rx", "tx";
 336                                         status = "disabled";
 337                                 };
 338                         };
 339
 340                         pwm1: pwm@2080000 {
 341                                 #pwm-cells = <3>;
 342                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 343                                 reg = <0x02080000 0x4000>;
 344                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 345                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 346                                          <&clks IMX6SL_CLK_PWM1>;
 347                                 clock-names = "ipg", "per";
 348                         };
 349
 350                         pwm2: pwm@2084000 {
 351                                 #pwm-cells = <3>;
 352                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 353                                 reg = <0x02084000 0x4000>;
 354                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 355                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 356                                          <&clks IMX6SL_CLK_PWM2>;
 357                                 clock-names = "ipg", "per";
 358                         };
 359
 360                         pwm3: pwm@2088000 {
 361                                 #pwm-cells = <3>;
 362                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 363                                 reg = <0x02088000 0x4000>;
 364                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 365                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 366                                          <&clks IMX6SL_CLK_PWM3>;
 367                                 clock-names = "ipg", "per";
 368                         };
 369
 370                         pwm4: pwm@208c000 {
 371                                 #pwm-cells = <3>;
 372                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 373                                 reg = <0x0208c000 0x4000>;
 374                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 375                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 376                                          <&clks IMX6SL_CLK_PWM4>;
 377                                 clock-names = "ipg", "per";
 378                         };
 379
 380                         gpt: timer@2098000 {
 381                                 compatible = "fsl,imx6sl-gpt";
 382                                 reg = <0x02098000 0x4000>;
 383                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clks IMX6SL_CLK_GPT>,
 385                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 386                                 clock-names = "ipg", "per";
 387                         };
 388
 389                         gpio1: gpio@209c000 {
 390                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 391                                 reg = <0x0209c000 0x4000>;
 392                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 393                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 394                                 gpio-controller;
 395                                 #gpio-cells = <2>;
 396                                 interrupt-controller;
 397                                 #interrupt-cells = <2>;
 398                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 399                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 400                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 401                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 402                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 403                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 404                         };
 405
 406                         gpio2: gpio@20a0000 {
 407                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 408                                 reg = <0x020a0000 0x4000>;
 409                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 410                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 411                                 gpio-controller;
 412                                 #gpio-cells = <2>;
 413                                 interrupt-controller;
 414                                 #interrupt-cells = <2>;
 415                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 416                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 417                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 418                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 419                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 420                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 421                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 422                         };
 423
 424                         gpio3: gpio@20a4000 {
 425                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 426                                 reg = <0x020a4000 0x4000>;
 427                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 428                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 429                                 gpio-controller;
 430                                 #gpio-cells = <2>;
 431                                 interrupt-controller;
 432                                 #interrupt-cells = <2>;
 433                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 434                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 435                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 436                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 437                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 438                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 439                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 440                                               <&iomuxc 31 102 1>;
 441                         };
 442
 443                         gpio4: gpio@20a8000 {
 444                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 445                                 reg = <0x020a8000 0x4000>;
 446                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 447                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 448                                 gpio-controller;
 449                                 #gpio-cells = <2>;
 450                                 interrupt-controller;
 451                                 #interrupt-cells = <2>;
 452                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 453                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 454                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 455                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 456                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 457                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 458                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 459                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 460                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 461                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 462                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 463                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 464                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 465                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 466                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 467                         };
 468
 469                         gpio5: gpio@20ac000 {
 470                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 471                                 reg = <0x020ac000 0x4000>;
 472                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 473                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 474                                 gpio-controller;
 475                                 #gpio-cells = <2>;
 476                                 interrupt-controller;
 477                                 #interrupt-cells = <2>;
 478                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 479                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 480                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 481                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 482                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 483                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 484                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 485                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 486                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 487                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 488                                               <&iomuxc 21 161 1>;
 489                         };
 490
 491                         kpp: keypad@20b8000 {
 492                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 493                                 reg = <0x020b8000 0x4000>;
 494                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks IMX6SL_CLK_IPG>;
 496                                 status = "disabled";
 497                         };
 498
 499                         wdog1: watchdog@20bc000 {
 500                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 501                                 reg = <0x020bc000 0x4000>;
 502                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 503                                 clocks = <&clks IMX6SL_CLK_IPG>;
 504                         };
 505
 506                         wdog2: watchdog@20c0000 {
 507                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 508                                 reg = <0x020c0000 0x4000>;
 509                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 510                                 clocks = <&clks IMX6SL_CLK_IPG>;
 511                                 status = "disabled";
 512                         };
 513
 514                         clks: clock-controller@20c4000 {
 515                                 compatible = "fsl,imx6sl-ccm";
 516                                 reg = <0x020c4000 0x4000>;
 517                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 519                                 #clock-cells = <1>;
 520                         };
 521
 522                         anatop: anatop@20c8000 {
 523                                 compatible = "fsl,imx6sl-anatop",
 524                                              "fsl,imx6q-anatop",
 525                                              "syscon", "simple-mfd";
 526                                 reg = <0x020c8000 0x1000>;
 527                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 528                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 529                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 530
 531                                 reg_vdd1p1: regulator-1p1 {
 532                                         compatible = "fsl,anatop-regulator";
 533                                         regulator-name = "vdd1p1";
 534                                         regulator-min-microvolt = <1000000>;
 535                                         regulator-max-microvolt = <1200000>;
 536                                         regulator-always-on;
 537                                         anatop-reg-offset = <0x110>;
 538                                         anatop-vol-bit-shift = <8>;
 539                                         anatop-vol-bit-width = <5>;
 540                                         anatop-min-bit-val = <4>;
 541                                         anatop-min-voltage = <800000>;
 542                                         anatop-max-voltage = <1375000>;
 543                                         anatop-enable-bit = <0>;
 544                                 };
 545
 546                                 reg_vdd3p0: regulator-3p0 {
 547                                         compatible = "fsl,anatop-regulator";
 548                                         regulator-name = "vdd3p0";
 549                                         regulator-min-microvolt = <2800000>;
 550                                         regulator-max-microvolt = <3150000>;
 551                                         regulator-always-on;
 552                                         anatop-reg-offset = <0x120>;
 553                                         anatop-vol-bit-shift = <8>;
 554                                         anatop-vol-bit-width = <5>;
 555                                         anatop-min-bit-val = <0>;
 556                                         anatop-min-voltage = <2625000>;
 557                                         anatop-max-voltage = <3400000>;
 558                                         anatop-enable-bit = <0>;
 559                                 };
 560
 561                                 reg_vdd2p5: regulator-2p5 {
 562                                         compatible = "fsl,anatop-regulator";
 563                                         regulator-name = "vdd2p5";
 564                                         regulator-min-microvolt = <2250000>;
 565                                         regulator-max-microvolt = <2750000>;
 566                                         regulator-always-on;
 567                                         anatop-reg-offset = <0x130>;
 568                                         anatop-vol-bit-shift = <8>;
 569                                         anatop-vol-bit-width = <5>;
 570                                         anatop-min-bit-val = <0>;
 571                                         anatop-min-voltage = <2100000>;
 572                                         anatop-max-voltage = <2850000>;
 573                                         anatop-enable-bit = <0>;
 574                                 };
 575
 576                                 reg_arm: regulator-vddcore {
 577                                         compatible = "fsl,anatop-regulator";
 578                                         regulator-name = "vddarm";
 579                                         regulator-min-microvolt = <725000>;
 580                                         regulator-max-microvolt = <1450000>;
 581                                         regulator-always-on;
 582                                         anatop-reg-offset = <0x140>;
 583                                         anatop-vol-bit-shift = <0>;
 584                                         anatop-vol-bit-width = <5>;
 585                                         anatop-delay-reg-offset = <0x170>;
 586                                         anatop-delay-bit-shift = <24>;
 587                                         anatop-delay-bit-width = <2>;
 588                                         anatop-min-bit-val = <1>;
 589                                         anatop-min-voltage = <725000>;
 590                                         anatop-max-voltage = <1450000>;
 591                                 };
 592
 593                                 reg_pu: regulator-vddpu {
 594                                         compatible = "fsl,anatop-regulator";
 595                                         regulator-name = "vddpu";
 596                                         regulator-min-microvolt = <725000>;
 597                                         regulator-max-microvolt = <1450000>;
 598                                         anatop-reg-offset = <0x140>;
 599                                         anatop-vol-bit-shift = <9>;
 600                                         anatop-vol-bit-width = <5>;
 601                                         anatop-delay-reg-offset = <0x170>;
 602                                         anatop-delay-bit-shift = <26>;
 603                                         anatop-delay-bit-width = <2>;
 604                                         anatop-min-bit-val = <1>;
 605                                         anatop-min-voltage = <725000>;
 606                                         anatop-max-voltage = <1450000>;
 607                                 };
 608
 609                                 reg_soc: regulator-vddsoc {
 610                                         compatible = "fsl,anatop-regulator";
 611                                         regulator-name = "vddsoc";
 612                                         regulator-min-microvolt = <725000>;
 613                                         regulator-max-microvolt = <1450000>;
 614                                         regulator-always-on;
 615                                         anatop-reg-offset = <0x140>;
 616                                         anatop-vol-bit-shift = <18>;
 617                                         anatop-vol-bit-width = <5>;
 618                                         anatop-delay-reg-offset = <0x170>;
 619                                         anatop-delay-bit-shift = <28>;
 620                                         anatop-delay-bit-width = <2>;
 621                                         anatop-min-bit-val = <1>;
 622                                         anatop-min-voltage = <725000>;
 623                                         anatop-max-voltage = <1450000>;
 624                                 };
 625
 626                                 tempmon: tempmon {
 627                                         compatible = "fsl,imx6q-tempmon";
 628                                         interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 629                                         interrupt-parent = <&gpc>;
 630                                         fsl,tempmon = <&anatop>;
 631                                         nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 632                                         nvmem-cell-names = "calib", "temp_grade";
 633                                         clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 634                                 };
 635                         };
 636
 637                         usbphy1: usbphy@20c9000 {
 638                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 639                                 reg = <0x020c9000 0x1000>;
 640                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 641                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 642                                 fsl,anatop = <&anatop>;
 643                         };
 644
 645                         usbphy2: usbphy@20ca000 {
 646                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 647                                 reg = <0x020ca000 0x1000>;
 648                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 649                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 650                                 fsl,anatop = <&anatop>;
 651                         };
 652
 653                         snvs: snvs@20cc000 {
 654                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 655                                 reg = <0x020cc000 0x4000>;
 656
 657                                 snvs_rtc: snvs-rtc-lp {
 658                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 659                                         regmap = <&snvs>;
 660                                         offset = <0x34>;
 661                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 662                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 663                                 };
 664
 665                                 snvs_poweroff: snvs-poweroff {
 666                                         compatible = "syscon-poweroff";
 667                                         regmap = <&snvs>;
 668                                         offset = <0x38>;
 669                                         value = <0x60>;
 670                                         mask = <0x60>;
 671                                         status = "disabled";
 672                                 };
 673                         };
 674
 675                         epit1: epit@20d0000 {
 676                                 reg = <0x020d0000 0x4000>;
 677                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 678                         };
 679
 680                         epit2: epit@20d4000 {
 681                                 reg = <0x020d4000 0x4000>;
 682                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 683                         };
 684
 685                         src: reset-controller@20d8000 {
 686                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 687                                 reg = <0x020d8000 0x4000>;
 688                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 689                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 690                                 #reset-cells = <1>;
 691                         };
 692
 693                         gpc: gpc@20dc000 {
 694                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 695                                 reg = <0x020dc000 0x4000>;
 696                                 interrupt-controller;
 697                                 #interrupt-cells = <3>;
 698                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 699                                 interrupt-parent = <&intc>;
 700                                 clocks = <&clks IMX6SL_CLK_IPG>;
 701                                 clock-names = "ipg";
 702
 703                                 pgc {
 704                                         #address-cells = <1>;
 705                                         #size-cells = <0>;
 706
 707                                         power-domain@0 {
 708                                                 reg = <0>;
 709                                                 #power-domain-cells = <0>;
 710                                         };
 711
 712                                         pd_pu: power-domain@1 {
 713                                                 reg = <1>;
 714                                                 #power-domain-cells = <0>;
 715                                                 power-supply = <&reg_pu>;
 716                                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 717                                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 718                                         };
 719
 720                                         pd_disp: power-domain@2 {
 721                                                 reg = <2>;
 722                                                 #power-domain-cells = <0>;
 723                                                 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
 724                                                          <&clks IMX6SL_CLK_LCDIF_PIX>,
 725                                                          <&clks IMX6SL_CLK_EPDC_AXI>,
 726                                                          <&clks IMX6SL_CLK_EPDC_PIX>,
 727                                                          <&clks IMX6SL_CLK_PXP_AXI>;
 728                                         };
 729                                 };
 730                         };
 731
 732                         gpr: iomuxc-gpr@20e0000 {
 733                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 734                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 735                                 reg = <0x020e0000 0x38>;
 736                         };
 737
 738                         iomuxc: pinctrl@20e0000 {
 739                                 compatible = "fsl,imx6sl-iomuxc";
 740                                 reg = <0x020e0000 0x4000>;
 741                         };
 742
 743                         csi: csi@20e4000 {
 744                                 reg = <0x020e4000 0x4000>;
 745                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 746                         };
 747
 748                         spdc: spdc@20e8000 {
 749                                 reg = <0x020e8000 0x4000>;
 750                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 751                         };
 752
 753                         sdma: dma-controller@20ec000 {
 754                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 755                                 reg = <0x020ec000 0x4000>;
 756                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 758                                          <&clks IMX6SL_CLK_AHB>;
 759                                 clock-names = "ipg", "ahb";
 760                                 #dma-cells = <3>;
 761                                 /* imx6sl reuses imx6q sdma firmware */
 762                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 763                         };
 764
 765                         pxp: pxp@20f0000 {
 766                                 reg = <0x020f0000 0x4000>;
 767                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 768                         };
 769
 770                         epdc: epdc@20f4000 {
 771                                 reg = <0x020f4000 0x4000>;
 772                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 773                         };
 774
 775                         lcdif: lcdif@20f8000 {
 776                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 777                                 reg = <0x020f8000 0x4000>;
 778                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 779                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 780                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 781                                          <&clks IMX6SL_CLK_DUMMY>;
 782                                 clock-names = "pix", "axi", "disp_axi";
 783                                 status = "disabled";
 784                                 power-domains = <&pd_disp>;
 785                         };
 786
 787                         dcp: crypto@20fc000 {
 788                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 789                                 reg = <0x020fc000 0x4000>;
 790                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 791                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 792                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 793                         };
 794                 };
 795
 796                 aips2: bus@2100000 {
 797                         compatible = "fsl,aips-bus", "simple-bus";
 798                         #address-cells = <1>;
 799                         #size-cells = <1>;
 800                         reg = <0x02100000 0x100000>;
 801                         ranges;
 802
 803                         usbotg1: usb@2184000 {
 804                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 805                                 reg = <0x02184000 0x200>;
 806                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 808                                 fsl,usbphy = <&usbphy1>;
 809                                 fsl,usbmisc = <&usbmisc 0>;
 810                                 ahb-burst-config = <0x0>;
 811                                 tx-burst-size-dword = <0x10>;
 812                                 rx-burst-size-dword = <0x10>;
 813                                 status = "disabled";
 814                         };
 815
 816                         usbotg2: usb@2184200 {
 817                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 818                                 reg = <0x02184200 0x200>;
 819                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 820                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 821                                 fsl,usbphy = <&usbphy2>;
 822                                 fsl,usbmisc = <&usbmisc 1>;
 823                                 ahb-burst-config = <0x0>;
 824                                 tx-burst-size-dword = <0x10>;
 825                                 rx-burst-size-dword = <0x10>;
 826                                 status = "disabled";
 827                         };
 828
 829                         usbh: usb@2184400 {
 830                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 831                                 reg = <0x02184400 0x200>;
 832                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 834                                 fsl,usbphy = <&usbphynop1>;
 835                                 phy_type = "hsic";
 836                                 fsl,usbmisc = <&usbmisc 2>;
 837                                 dr_mode = "host";
 838                                 ahb-burst-config = <0x0>;
 839                                 tx-burst-size-dword = <0x10>;
 840                                 rx-burst-size-dword = <0x10>;
 841                                 status = "disabled";
 842                         };
 843
 844                         usbmisc: usbmisc@2184800 {
 845                                 #index-cells = <1>;
 846                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 847                                 reg = <0x02184800 0x200>;
 848                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 849                         };
 850
 851                         fec: ethernet@2188000 {
 852                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 853                                 reg = <0x02188000 0x4000>;
 854                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6SL_CLK_ENET>,
 856                                          <&clks IMX6SL_CLK_ENET_REF>;
 857                                 clock-names = "ipg", "ahb";
 858                                 status = "disabled";
 859                         };
 860
 861                         usdhc1: mmc@2190000 {
 862                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 863                                 reg = <0x02190000 0x4000>;
 864                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 866                                          <&clks IMX6SL_CLK_USDHC1>,
 867                                          <&clks IMX6SL_CLK_USDHC1>;
 868                                 clock-names = "ipg", "ahb", "per";
 869                                 bus-width = <4>;
 870                                 status = "disabled";
 871                         };
 872
 873                         usdhc2: mmc@2194000 {
 874                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 875                                 reg = <0x02194000 0x4000>;
 876                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 877                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 878                                          <&clks IMX6SL_CLK_USDHC2>,
 879                                          <&clks IMX6SL_CLK_USDHC2>;
 880                                 clock-names = "ipg", "ahb", "per";
 881                                 bus-width = <4>;
 882                                 status = "disabled";
 883                         };
 884
 885                         usdhc3: mmc@2198000 {
 886                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 887                                 reg = <0x02198000 0x4000>;
 888                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 890                                          <&clks IMX6SL_CLK_USDHC3>,
 891                                          <&clks IMX6SL_CLK_USDHC3>;
 892                                 clock-names = "ipg", "ahb", "per";
 893                                 bus-width = <4>;
 894                                 status = "disabled";
 895                         };
 896
 897                         usdhc4: mmc@219c000 {
 898                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 899                                 reg = <0x0219c000 0x4000>;
 900                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 902                                          <&clks IMX6SL_CLK_USDHC4>,
 903                                          <&clks IMX6SL_CLK_USDHC4>;
 904                                 clock-names = "ipg", "ahb", "per";
 905                                 bus-width = <4>;
 906                                 status = "disabled";
 907                         };
 908
 909                         i2c1: i2c@21a0000 {
 910                                 #address-cells = <1>;
 911                                 #size-cells = <0>;
 912                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 913                                 reg = <0x021a0000 0x4000>;
 914                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c2: i2c@21a4000 {
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 923                                 reg = <0x021a4000 0x4000>;
 924                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 925                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 926                                 status = "disabled";
 927                         };
 928
 929                         i2c3: i2c@21a8000 {
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 933                                 reg = <0x021a8000 0x4000>;
 934                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 936                                 status = "disabled";
 937                         };
 938
 939                         memory-controller@21b0000 {
 940                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 941                                 reg = <0x021b0000 0x4000>;
 942                                 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
 943                         };
 944
 945                         rngb: rngb@21b4000 {
 946                                 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
 947                                 reg = <0x021b4000 0x4000>;
 948                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 949                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 950                         };
 951
 952                         weim: weim@21b8000 {
 953                                 #address-cells = <2>;
 954                                 #size-cells = <1>;
 955                                 reg = <0x021b8000 0x4000>;
 956                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 957                                 fsl,weim-cs-gpr = <&gpr>;
 958                                 status = "disabled";
 959                         };
 960
 961                         ocotp: efuse@21bc000 {
 962                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 963                                 reg = <0x021bc000 0x4000>;
 964                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 965                                 #address-cells = <1>;
 966                                 #size-cells = <1>;
 967
 968                                 cpu_speed_grade: speed-grade@10 {
 969                                         reg = <0x10 4>;
 970                                 };
 971
 972                                 tempmon_calib: calib@38 {
 973                                         reg = <0x38 4>;
 974                                 };
 975
 976                                 tempmon_temp_grade: temp-grade@20 {
 977                                         reg = <0x20 4>;
 978                                 };
 979                         };
 980
 981                         audmux: audmux@21d8000 {
 982                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 983                                 reg = <0x021d8000 0x4000>;
 984                                 status = "disabled";
 985                         };
 986                 };
 987
 988                 gpu_2d: gpu@2200000 {
 989                         compatible = "vivante,gc";
 990                         reg = <0x02200000 0x4000>;
 991                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 992                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 993                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 994                         clock-names = "bus", "core";
 995                         power-domains = <&pd_pu>;
 996                 };
 997
 998                 gpu_vg: gpu@2204000 {
 999                         compatible = "vivante,gc";
1000                         reg = <0x02204000 0x4000>;
1001                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
1002                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
1003                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
1004                         clock-names = "bus", "core";
1005                         power-domains = <&pd_pu>;
1006                 };
1007         };
1008 };