arch/arm/boot/dts/imx7s-warp.dts

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors.
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /dts-v1/;
  45
  46 #include <dt-bindings/input/input.h>
  47 #include "imx7s.dtsi"
  48
  49 / {
  50         model = "Warp i.MX7 Board";
  51         compatible = "warp,imx7s-warp", "fsl,imx7s";
  52
  53         memory@80000000 {
  54                 reg = <0x80000000 0x20000000>;
  55         };
  56
  57         gpio-keys {
  58                 compatible = "gpio-keys";
  59                 pinctrl-0 = <&pinctrl_gpio>;
  60                 autorepeat;
  61
  62                 back {
  63                         label = "Back";
  64                         gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  65                         linux,code = <KEY_BACK>;
  66                         wakeup-source;
  67                 };
  68         };
  69
  70         reg_brcm: regulator-brcm {
  71                 compatible = "regulator-fixed";
  72                 enable-active-high;
  73                 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_brcm_reg>;
  76                 regulator-name = "brcm_reg";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 startup-delay-us = <200000>;
  80         };
  81
  82         reg_bt: regulator-bt {
  83                 compatible = "regulator-fixed";
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&pinctrl_bt_reg>;
  86                 enable-active-high;
  87                 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
  88                 regulator-name = "bt_reg";
  89                 regulator-min-microvolt = <3300000>;
  90                 regulator-max-microvolt = <3300000>;
  91                 regulator-always-on;
  92         };
  93
  94         sound {
  95                 compatible = "simple-audio-card";
  96                 simple-audio-card,name = "imx7-sgtl5000";
  97                 simple-audio-card,format = "i2s";
  98                 simple-audio-card,bitclock-master = <&dailink_master>;
  99                 simple-audio-card,frame-master = <&dailink_master>;
 100                 simple-audio-card,cpu {
 101                         sound-dai = <&sai1>;
 102                 };
 103
 104                 dailink_master: simple-audio-card,codec {
 105                         sound-dai = <&codec>;
 106                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 107                 };
 108         };
 109 };
 110
 111 &clks {
 112         assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 113         assigned-clock-rates = <884736000>;
 114 };
 115
 116 &i2c1 {
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_i2c1>;
 119         status = "okay";
 120
 121         pmic: pfuze3000@8 {
 122                 compatible = "fsl,pfuze3000";
 123                 reg = <0x08>;
 124
 125                 regulators {
 126                         sw1a_reg: sw1a {
 127                                 regulator-min-microvolt = <700000>;
 128                                 regulator-max-microvolt = <1475000>;
 129                                 regulator-boot-on;
 130                                 regulator-always-on;
 131                                 regulator-ramp-delay = <6250>;
 132                         };
 133
 134                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 135                         sw1c_reg: sw1b {
 136                                 regulator-min-microvolt = <700000>;
 137                                 regulator-max-microvolt = <1475000>;
 138                                 regulator-boot-on;
 139                                 regulator-always-on;
 140                                 regulator-ramp-delay = <6250>;
 141                         };
 142
 143                         sw2_reg: sw2 {
 144                                 regulator-min-microvolt = <1500000>;
 145                                 regulator-max-microvolt = <1850000>;
 146                                 regulator-boot-on;
 147                                 regulator-always-on;
 148                         };
 149
 150                         sw3a_reg: sw3 {
 151                                 regulator-min-microvolt = <900000>;
 152                                 regulator-max-microvolt = <1650000>;
 153                                 regulator-boot-on;
 154                                 regulator-always-on;
 155                         };
 156
 157                         swbst_reg: swbst {
 158                                 regulator-min-microvolt = <5000000>;
 159                                 regulator-max-microvolt = <5150000>;
 160                         };
 161
 162                         snvs_reg: vsnvs {
 163                                 regulator-min-microvolt = <1000000>;
 164                                 regulator-max-microvolt = <3000000>;
 165                                 regulator-boot-on;
 166                                 regulator-always-on;
 167                         };
 168
 169                         vref_reg: vrefddr {
 170                                 regulator-boot-on;
 171                                 regulator-always-on;
 172                         };
 173
 174                         vgen1_reg: vldo1 {
 175                                 regulator-min-microvolt = <1800000>;
 176                                 regulator-max-microvolt = <3300000>;
 177                                 regulator-always-on;
 178                         };
 179
 180                         vgen2_reg: vldo2 {
 181                                 regulator-min-microvolt = <800000>;
 182                                 regulator-max-microvolt = <1550000>;
 183                         };
 184
 185                         vgen3_reg: vccsd {
 186                                 regulator-min-microvolt = <2850000>;
 187                                 regulator-max-microvolt = <3300000>;
 188                                 regulator-always-on;
 189                         };
 190
 191                         vgen4_reg: v33 {
 192                                 regulator-min-microvolt = <2850000>;
 193                                 regulator-max-microvolt = <3300000>;
 194                                 regulator-always-on;
 195                         };
 196
 197                         vgen5_reg: vldo3 {
 198                                 regulator-min-microvolt = <1800000>;
 199                                 regulator-max-microvolt = <3300000>;
 200                                 regulator-always-on;
 201                         };
 202
 203                         vgen6_reg: vldo4 {
 204                                 regulator-min-microvolt = <1800000>;
 205                                 regulator-max-microvolt = <3300000>;
 206                                 regulator-always-on;
 207                         };
 208                 };
 209         };
 210 };
 211
 212 &i2c2 {
 213         clock-frequency = <100000>;
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&pinctrl_i2c2>;
 216         status = "okay";
 217 };
 218
 219 &i2c3 {
 220         clock-frequency = <100000>;
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_i2c3>;
 223         status = "okay";
 224 };
 225
 226 &i2c4 {
 227         clock-frequency = <100000>;
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_i2c4>;
 230         status = "okay";
 231
 232         codec: sgtl5000@a {
 233                 #sound-dai-cells = <0>;
 234                 reg = <0x0a>;
 235                 compatible = "fsl,sgtl5000";
 236                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 237                 pinctrl-names = "default";
 238                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 239                 VDDA-supply = <&vgen4_reg>;
 240                 VDDIO-supply = <&vgen4_reg>;
 241                 VDDD-supply = <&vgen2_reg>;
 242         };
 243
 244         mpl3115@60 {
 245                 compatible = "fsl,mpl3115";
 246                 reg = <0x60>;
 247         };
 248 };
 249
 250 &sai1 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_sai1>;
 253         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 254                           <&clks IMX7D_SAI1_ROOT_CLK>;
 255         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 256         assigned-clock-rates = <0>, <36864000>;
 257         status = "okay";
 258 };
 259
 260 &uart1 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_uart1>;
 263         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 264         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 265         status = "okay";
 266 };
 267
 268 &uart3  {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&pinctrl_uart3>;
 271         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 272         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 273         uart-has-rtscts;
 274         status = "okay";
 275 };
 276
 277 &uart6 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_uart6>;
 280         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 281         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 282         fsl,dte-mode;
 283         status = "okay";
 284 };
 285
 286 &usbotg1 {
 287         dr_mode = "peripheral";
 288         status = "okay";
 289 };
 290
 291 &usdhc1 {
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_usdhc1>;
 294         bus-width = <4>;
 295         keep-power-in-suspend;
 296         no-1-8-v;
 297         non-removable;
 298         vmmc-supply = <&reg_brcm>;
 299         status = "okay";
 300 };
 301
 302 &usdhc3 {
 303         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 304         pinctrl-0 = <&pinctrl_usdhc3>;
 305         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 306         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 307         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 308         assigned-clock-rates = <400000000>;
 309         bus-width = <8>;
 310         no-1-8-v;
 311         fsl,tuning-step = <2>;
 312         non-removable;
 313         status = "okay";
 314 };
 315
 316 &wdog1 {
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_wdog>;
 319         fsl,ext-reset-output;
 320         status = "okay";
 321 };
 322
 323 &iomuxc {
 324         pinctrl_brcm_reg: brcmreggrp {
 325                 fsl,pins = <
 326                         MX7D_PAD_SD2_WP__GPIO5_IO10     0x14 /* WL_REG_ON */
 327                 >;
 328         };
 329
 330         pinctrl_bt_reg: btreggrp {
 331                 fsl,pins = <
 332                         MX7D_PAD_SD2_DATA3__GPIO5_IO17  0x14 /* BT_REG_ON */
 333                 >;
 334         };
 335
 336         pinctrl_gpio: gpiogrp {
 337                 fsl,pins = <
 338                         MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1     0x14
 339                 >;
 340         };
 341
 342         pinctrl_i2c1: i2c1grp {
 343                 fsl,pins = <
 344                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 345                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 346                 >;
 347         };
 348
 349         pinctrl_i2c2: i2c2grp {
 350                 fsl,pins = <
 351                         MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
 352                         MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
 353                 >;
 354         };
 355
 356         pinctrl_i2c3: i2c3grp {
 357                 fsl,pins = <
 358                         MX7D_PAD_I2C3_SDA__I2C3_SDA     0x4000007f
 359                         MX7D_PAD_I2C3_SCL__I2C3_SCL     0x4000007f
 360                 >;
 361         };
 362
 363         pinctrl_i2c4: i2c4grp {
 364                 fsl,pins = <
 365                         MX7D_PAD_I2C4_SCL__I2C4_SCL     0x4000007f
 366                         MX7D_PAD_I2C4_SDA__I2C4_SDA     0x4000007f
 367                 >;
 368         };
 369
 370         pinctrl_sai1: sai1grp {
 371                 fsl,pins = <
 372                         MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
 373                         MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
 374                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 375                         MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0x30
 376                 >;
 377         };
 378
 379         pinctrl_sai1_mclk: sai1mclkgrp {
 380                 fsl,pins = <
 381                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 382                 >;
 383         };
 384
 385         pinctrl_uart1: uart1grp {
 386                 fsl,pins = <
 387                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 388                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 389                 >;
 390         };
 391
 392         pinctrl_uart3: uart3grp {
 393                 fsl,pins = <
 394                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 395                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 396                         MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
 397                         MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
 398                 >;
 399         };
 400
 401         pinctrl_uart6: uart6grp {
 402                 fsl,pins = <
 403                         MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX      0x79
 404                         MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX      0x79
 405                 >;
 406         };
 407
 408         pinctrl_usdhc1: usdhc1grp {
 409                 fsl,pins = <
 410                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 411                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 412                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 413                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 414                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 415                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 416                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
 417                 >;
 418         };
 419
 420         pinctrl_usdhc3: usdhc3grp {
 421                 fsl,pins = <
 422                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 423                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 424                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 425                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 426                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 427                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 428                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 429                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 430                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 431                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 432                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x19
 433                 >;
 434         };
 435
 436         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 437                 fsl,pins = <
 438                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 439                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 440                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 441                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 442                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 443                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 444                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 445                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 446                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 447                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 448                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1a
 449                 >;
 450         };
 451
 452         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 453                 fsl,pins = <
 454                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 455                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 456                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 457                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 458                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 459                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 460                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 461                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 462                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 463                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 464                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1b
 465                 >;
 466         };
 467 };
 468
 469 &iomuxc_lpsr {
 470         pinctrl_wdog: wdoggrp {
 471                 fsl,pins = <
 472                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x74
 473                 >;
 474         };
 475 };