arch/arm/boot/dts/en7523.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 / {
   8         interrupt-parent = <&gic>;
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 npu_binary@84000000 {
  18                         no-map;
  19                         reg = <0x84000000 0xA00000>;
  20                 };
  21
  22                 npu_flag@84B0000 {
  23                         no-map;
  24                         reg = <0x84B00000 0x100000>;
  25                 };
  26
  27                 npu_pkt@85000000 {
  28                         no-map;
  29                         reg = <0x85000000 0x1A00000>;
  30                 };
  31
  32                 npu_phyaddr@86B00000 {
  33                         no-map;
  34                         reg = <0x86B00000 0x100000>;
  35                 };
  36
  37                 npu_rxdesc@86D00000 {
  38                         no-map;
  39                         reg = <0x86D00000 0x100000>;
  40                 };
  41         };
  42
  43         psci {
  44                 compatible = "arm,psci-0.2";
  45                 method = "smc";
  46         };
  47
  48         cpus {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 cpu-map {
  53                         cluster0 {
  54                                 core0 {
  55                                         cpu = <&cpu0>;
  56                                 };
  57                                 core1 {
  58                                         cpu = <&cpu1>;
  59                                 };
  60                         };
  61                 };
  62
  63                 cpu0: cpu@0 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53";
  66                         reg = <0x0>;
  67                         enable-method = "psci";
  68                         clock-frequency = <80000000>;
  69                         next-level-cache = <&L2_0>;
  70                 };
  71
  72                 cpu1: cpu@1 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         reg = <0x1>;
  76                         enable-method = "psci";
  77                         clock-frequency = <80000000>;
  78                         next-level-cache = <&L2_0>;
  79                 };
  80
  81                 L2_0: l2-cache0 {
  82                         compatible = "cache";
  83                 };
  84         };
  85
  86         gic: interrupt-controller@9000000 {
  87                 compatible = "arm,gic-v3";
  88                 interrupt-controller;
  89                 #interrupt-cells = <3>;
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 reg = <0x09000000 0x20000>,
  93                       <0x09080000 0x80000>,
  94                       <0x09400000 0x2000>,
  95                       <0x09500000 0x2000>,
  96                       <0x09600000 0x20000>;
  97                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
  98         };
  99
 100         timer {
 101                 compatible = "arm,armv8-timer";
 102                 interrupt-parent = <&gic>;
 103                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 104                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 105                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 106                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 107         };
 108
 109         uart1: serial@1fbf0000 {
 110                 compatible = "ns16550";
 111                 reg = <0x1fbf0000 0x30>;
 112                 reg-io-width = <4>;
 113                 reg-shift = <2>;
 114                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 115                 clock-frequency = <1843200>;
 116                 status = "okay";
 117         };
 118
 119         gpio0: gpio@1fbf0200 {
 120                 compatible = "airoha,en7523-gpio";
 121                 reg = <0x1fbf0204 0x4>,
 122                       <0x1fbf0200 0x4>,
 123                       <0x1fbf0220 0x4>,
 124                       <0x1fbf0214 0x4>;
 125                 gpio-controller;
 126                 #gpio-cells = <2>;
 127         };
 128
 129         gpio1: gpio@1fbf0270 {
 130                 compatible = "airoha,en7523-gpio";
 131                 reg = <0x1fbf0270 0x4>,
 132                       <0x1fbf0260 0x4>,
 133                       <0x1fbf0264 0x4>,
 134                       <0x1fbf0278 0x4>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137         };
 138 };