arch/arm/boot/dts/broadcom/bcm63178.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 Broadcom Ltd.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8
   9 / {
  10         compatible = "brcm,bcm63178", "brcm,bcmbca";
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         interrupt-parent = <&gic>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 CA7_0: cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a7";
  23                         reg = <0x0>;
  24                         next-level-cache = <&L2_0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 CA7_1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0x1>;
  32                         next-level-cache = <&L2_0>;
  33                         enable-method = "psci";
  34                 };
  35
  36                 CA7_2: cpu@2 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a7";
  39                         reg = <0x2>;
  40                         next-level-cache = <&L2_0>;
  41                         enable-method = "psci";
  42                 };
  43
  44                 L2_0: l2-cache0 {
  45                         compatible = "cache";
  46                         cache-level = <2>;
  47                         cache-unified;
  48                 };
  49         };
  50
  51         timer {
  52                 compatible = "arm,armv7-timer";
  53                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
  54                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
  55                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
  56                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
  57                 arm,cpu-registers-not-fw-configured;
  58         };
  59
  60         pmu: pmu {
  61                 compatible = "arm,cortex-a7-pmu";
  62                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  63                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  64                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  65                 interrupt-affinity = <&CA7_0>, <&CA7_1>,
  66                         <&CA7_2>;
  67         };
  68
  69         clocks: clocks {
  70                 periph_clk: periph-clk {
  71                         compatible = "fixed-clock";
  72                         #clock-cells = <0>;
  73                         clock-frequency = <200000000>;
  74                 };
  75
  76                 uart_clk: uart-clk {
  77                         compatible = "fixed-factor-clock";
  78                         #clock-cells = <0>;
  79                         clocks = <&periph_clk>;
  80                         clock-div = <4>;
  81                         clock-mult = <1>;
  82                 };
  83
  84                 hsspi_pll: hsspi-pll {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <200000000>;
  88                 };
  89         };
  90
  91         psci {
  92                 compatible = "arm,psci-0.2";
  93                 method = "smc";
  94         };
  95
  96         axi@81000000 {
  97                 compatible = "simple-bus";
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 ranges = <0 0x81000000 0x8000>;
 101
 102                 gic: interrupt-controller@1000 {
 103                         compatible = "arm,cortex-a7-gic";
 104                         #interrupt-cells = <3>;
 105                         interrupt-controller;
 106                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
 107                         reg = <0x1000 0x1000>,
 108                                 <0x2000 0x2000>,
 109                                 <0x4000 0x2000>,
 110                                 <0x6000 0x2000>;
 111                 };
 112         };
 113
 114         bus@ff800000 {
 115                 compatible = "simple-bus";
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges = <0 0xff800000 0x800000>;
 119
 120                 hsspi: spi@1000 {
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                         compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
 124                         reg = <0x1000 0x600>;
 125                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&hsspi_pll &hsspi_pll>;
 127                         clock-names = "hsspi", "pll";
 128                         num-cs = <8>;
 129                         status = "disabled";
 130                 };
 131
 132                 nand_controller: nand-controller@1800 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
 136                         reg = <0x1800 0x600>, <0x2000 0x10>;
 137                         reg-names = "nand", "nand-int-base";
 138                         status = "disabled";
 139
 140                         nandcs: nand@0 {
 141                                 compatible = "brcm,nandcs";
 142                                 reg = <0>;
 143                         };
 144                 };
 145
 146                 uart0: serial@12000 {
 147                         compatible = "arm,pl011", "arm,primecell";
 148                         reg = <0x12000 0x1000>;
 149                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&uart_clk>, <&uart_clk>;
 151                         clock-names = "uartclk", "apb_pclk";
 152                         status = "disabled";
 153                 };
 154         };
 155 };