arch/arm/boot/dts/bcm5301x.dtsi

   1 /*
   2  * Broadcom BCM470X / BCM5301X ARM platform code.
   3  * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
   4  * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
   5  *
   6  * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <dt-bindings/clock/bcm-nsp.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20         interrupt-parent = <&gic>;
  21
  22         chipcommon-a-bus@18000000 {
  23                 compatible = "simple-bus";
  24                 ranges = <0x00000000 0x18000000 0x00001000>;
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27
  28                 uart0: serial@300 {
  29                         compatible = "ns16550";
  30                         reg = <0x0300 0x100>;
  31                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  32                         clocks = <&iprocslow>;
  33                         status = "disabled";
  34                 };
  35
  36                 uart1: serial@400 {
  37                         compatible = "ns16550";
  38                         reg = <0x0400 0x100>;
  39                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  40                         clocks = <&iprocslow>;
  41                         pinctrl-names = "default";
  42                         pinctrl-0 = <&pinmux_uart1>;
  43                         status = "disabled";
  44                 };
  45         };
  46
  47         mpcore-bus@19000000 {
  48                 compatible = "simple-bus";
  49                 ranges = <0x00000000 0x19000000 0x00023000>;
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 a9pll: arm_clk@0 {
  54                         #clock-cells = <0>;
  55                         compatible = "brcm,nsp-armpll";
  56                         clocks = <&osc>;
  57                         reg = <0x00000 0x1000>;
  58                 };
  59
  60                 scu@20000 {
  61                         compatible = "arm,cortex-a9-scu";
  62                         reg = <0x20000 0x100>;
  63                 };
  64
  65                 timer@20200 {
  66                         compatible = "arm,cortex-a9-global-timer";
  67                         reg = <0x20200 0x100>;
  68                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  69                         clocks = <&periph_clk>;
  70                 };
  71
  72                 timer@20600 {
  73                         compatible = "arm,cortex-a9-twd-timer";
  74                         reg = <0x20600 0x20>;
  75                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  76                                                   IRQ_TYPE_EDGE_RISING)>;
  77                         clocks = <&periph_clk>;
  78                 };
  79
  80                 watchdog@20620 {
  81                         compatible = "arm,cortex-a9-twd-wdt";
  82                         reg = <0x20620 0x20>;
  83                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  84                                                   IRQ_TYPE_EDGE_RISING)>;
  85                         clocks = <&periph_clk>;
  86                 };
  87
  88                 gic: interrupt-controller@21000 {
  89                         compatible = "arm,cortex-a9-gic";
  90                         #interrupt-cells = <3>;
  91                         #address-cells = <0>;
  92                         interrupt-controller;
  93                         reg = <0x21000 0x1000>,
  94                               <0x20100 0x100>;
  95                 };
  96
  97                 L2: cache-controller@22000 {
  98                         compatible = "arm,pl310-cache";
  99                         reg = <0x22000 0x1000>;
 100                         cache-unified;
 101                         arm,shared-override;
 102                         prefetch-data = <1>;
 103                         prefetch-instr = <1>;
 104                         cache-level = <2>;
 105                 };
 106         };
 107
 108         pmu {
 109                 compatible = "arm,cortex-a9-pmu";
 110                 interrupts =
 111                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 112                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 113         };
 114
 115         clocks {
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges;
 119
 120                 osc: oscillator {
 121                         #clock-cells = <0>;
 122                         compatible = "fixed-clock";
 123                         clock-frequency = <25000000>;
 124                 };
 125
 126                 iprocmed: iprocmed {
 127                         #clock-cells = <0>;
 128                         compatible = "fixed-factor-clock";
 129                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 130                         clock-div = <2>;
 131                         clock-mult = <1>;
 132                 };
 133
 134                 iprocslow: iprocslow {
 135                         #clock-cells = <0>;
 136                         compatible = "fixed-factor-clock";
 137                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 138                         clock-div = <4>;
 139                         clock-mult = <1>;
 140                 };
 141
 142                 periph_clk: periph_clk {
 143                         #clock-cells = <0>;
 144                         compatible = "fixed-factor-clock";
 145                         clocks = <&a9pll>;
 146                         clock-div = <2>;
 147                         clock-mult = <1>;
 148                 };
 149         };
 150
 151         axi@18000000 {
 152                 compatible = "brcm,bus-axi";
 153                 reg = <0x18000000 0x1000>;
 154                 ranges = <0x00000000 0x18000000 0x00100000>;
 155                 #address-cells = <1>;
 156                 #size-cells = <1>;
 157
 158                 #interrupt-cells = <1>;
 159                 interrupt-map-mask = <0x000fffff 0xffff>;
 160                 interrupt-map =
 161                         /* ChipCommon */
 162                         <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 163
 164                         /* Switch Register Access Block */
 165                         <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 166                         <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 167                         <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 168                         <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 169                         <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 170                         <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 171                         <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 172                         <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 173                         <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 174                         <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 175                         <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 176                         <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 177                         <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 178
 179                         /* PCIe Controller 0 */
 180                         <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 181                         <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 182                         <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 183                         <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 184                         <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 185                         <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 186
 187                         /* PCIe Controller 1 */
 188                         <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 189                         <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 190                         <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 191                         <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 192                         <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 193                         <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 194
 195                         /* PCIe Controller 2 */
 196                         <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 197                         <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 198                         <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 199                         <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 200                         <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 201                         <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 202
 203                         /* USB 2.0 Controller */
 204                         <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 205
 206                         /* USB 3.0 Controller */
 207                         <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 208
 209                         /* Ethernet Controller 0 */
 210                         <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 211
 212                         /* Ethernet Controller 1 */
 213                         <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 214
 215                         /* Ethernet Controller 2 */
 216                         <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 217
 218                         /* Ethernet Controller 3 */
 219                         <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 220
 221                         /* NAND Controller */
 222                         <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 223                         <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 224                         <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 225                         <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 226                         <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 227                         <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 228                         <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 229                         <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 230
 231                 chipcommon: chipcommon@0 {
 232                         reg = <0x00000000 0x1000>;
 233
 234                         gpio-controller;
 235                         #gpio-cells = <2>;
 236                         interrupt-controller;
 237                         #interrupt-cells = <2>;
 238                 };
 239
 240                 pcie0: pcie@12000 {
 241                         reg = <0x00012000 0x1000>;
 242                 };
 243
 244                 pcie1: pcie@13000 {
 245                         reg = <0x00013000 0x1000>;
 246                 };
 247
 248                 pcie2: pcie@14000 {
 249                         reg = <0x00014000 0x1000>;
 250                 };
 251
 252                 usb2: usb2@21000 {
 253                         reg = <0x00021000 0x1000>;
 254
 255                         #address-cells = <1>;
 256                         #size-cells = <1>;
 257                         ranges;
 258
 259                         interrupt-parent = <&gic>;
 260
 261                         ehci: usb@21000 {
 262                                 #usb-cells = <0>;
 263
 264                                 compatible = "generic-ehci";
 265                                 reg = <0x00021000 0x1000>;
 266                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 267                                 phys = <&usb2_phy>;
 268
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271
 272                                 ehci_port1: port@1 {
 273                                         reg = <1>;
 274                                         #trigger-source-cells = <0>;
 275                                 };
 276
 277                                 ehci_port2: port@2 {
 278                                         reg = <2>;
 279                                         #trigger-source-cells = <0>;
 280                                 };
 281                         };
 282
 283                         ohci: usb@22000 {
 284                                 #usb-cells = <0>;
 285
 286                                 compatible = "generic-ohci";
 287                                 reg = <0x00022000 0x1000>;
 288                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 289
 290                                 #address-cells = <1>;
 291                                 #size-cells = <0>;
 292
 293                                 ohci_port1: port@1 {
 294                                         reg = <1>;
 295                                         #trigger-source-cells = <0>;
 296                                 };
 297
 298                                 ohci_port2: port@2 {
 299                                         reg = <2>;
 300                                         #trigger-source-cells = <0>;
 301                                 };
 302                         };
 303                 };
 304
 305                 usb3: usb3@23000 {
 306                         reg = <0x00023000 0x1000>;
 307
 308                         #address-cells = <1>;
 309                         #size-cells = <1>;
 310                         ranges;
 311
 312                         interrupt-parent = <&gic>;
 313
 314                         xhci: usb@23000 {
 315                                 #usb-cells = <0>;
 316
 317                                 compatible = "generic-xhci";
 318                                 reg = <0x00023000 0x1000>;
 319                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 320                                 phys = <&usb3_phy>;
 321                                 phy-names = "usb";
 322
 323                                 #address-cells = <1>;
 324                                 #size-cells = <0>;
 325
 326                                 xhci_port1: port@1 {
 327                                         reg = <1>;
 328                                         #trigger-source-cells = <0>;
 329                                 };
 330                         };
 331                 };
 332
 333                 gmac0: ethernet@24000 {
 334                         reg = <0x24000 0x800>;
 335                 };
 336
 337                 gmac1: ethernet@25000 {
 338                         reg = <0x25000 0x800>;
 339                 };
 340
 341                 gmac2: ethernet@26000 {
 342                         reg = <0x26000 0x800>;
 343                 };
 344
 345                 gmac3: ethernet@27000 {
 346                         reg = <0x27000 0x800>;
 347                 };
 348         };
 349
 350         pwm: pwm@18002000 {
 351                 compatible = "brcm,iproc-pwm";
 352                 reg = <0x18002000 0x28>;
 353                 clocks = <&osc>;
 354                 #pwm-cells = <3>;
 355                 status = "disabled";
 356         };
 357
 358         mdio: mdio@18003000 {
 359                 compatible = "brcm,iproc-mdio";
 360                 reg = <0x18003000 0x8>;
 361                 #size-cells = <0>;
 362                 #address-cells = <1>;
 363         };
 364
 365         mdio-mux@18003000 {
 366                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 367                 mdio-parent-bus = <&mdio>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 reg = <0x18003000 0x4>;
 371                 mux-mask = <0x200>;
 372
 373                 mdio@0 {
 374                         reg = <0x0>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377
 378                         usb3_phy: usb3-phy@10 {
 379                                 compatible = "brcm,ns-ax-usb3-phy";
 380                                 reg = <0x10>;
 381                                 usb3-dmp-syscon = <&usb3_dmp>;
 382                                 #phy-cells = <0>;
 383                                 status = "disabled";
 384                         };
 385                 };
 386         };
 387
 388         usb3_dmp: syscon@18105000 {
 389                 reg = <0x18105000 0x1000>;
 390         };
 391
 392         uart2: serial@18008000 {
 393                 compatible = "ns16550a";
 394                 reg = <0x18008000 0x20>;
 395                 clocks = <&iprocslow>;
 396                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 397                 reg-shift = <2>;
 398                 status = "disabled";
 399         };
 400
 401         i2c0: i2c@18009000 {
 402                 compatible = "brcm,iproc-i2c";
 403                 reg = <0x18009000 0x50>;
 404                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clock-frequency = <100000>;
 408                 status = "disabled";
 409         };
 410
 411         dmu-bus@1800c000 {
 412                 compatible = "simple-bus";
 413                 ranges = <0 0x1800c000 0x1000>;
 414                 #address-cells = <1>;
 415                 #size-cells = <1>;
 416
 417                 cru-bus@100 {
 418                         compatible = "brcm,ns-cru", "simple-mfd";
 419                         reg = <0x100 0x1a4>;
 420                         ranges;
 421                         #address-cells = <1>;
 422                         #size-cells = <1>;
 423
 424                         lcpll0: clock-controller@100 {
 425                                 #clock-cells = <1>;
 426                                 compatible = "brcm,nsp-lcpll0";
 427                                 reg = <0x100 0x14>;
 428                                 clocks = <&osc>;
 429                                 clock-output-names = "lcpll0", "pcie_phy",
 430                                                      "sdio", "ddr_phy";
 431                         };
 432
 433                         genpll: clock-controller@140 {
 434                                 #clock-cells = <1>;
 435                                 compatible = "brcm,nsp-genpll";
 436                                 reg = <0x140 0x24>;
 437                                 clocks = <&osc>;
 438                                 clock-output-names = "genpll", "phy",
 439                                                      "ethernetclk",
 440                                                      "usbclk", "iprocfast",
 441                                                      "sata1", "sata2";
 442                         };
 443
 444                         usb2_phy: phy@164 {
 445                                 compatible = "brcm,ns-usb2-phy";
 446                                 reg = <0x164 0x4>;
 447                                 brcm,syscon-clkset = <&cru_clkset>;
 448                                 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
 449                                 clock-names = "phy-ref-clk";
 450                                 #phy-cells = <0>;
 451                         };
 452
 453                         cru_clkset: syscon@180 {
 454                                 compatible = "brcm,cru-clkset", "syscon";
 455                                 reg = <0x180 0x4>;
 456                         };
 457
 458                         pinctrl: pinctrl@1c0 {
 459                                 compatible = "brcm,bcm4708-pinmux";
 460                                 reg = <0x1c0 0x24>;
 461                                 reg-names = "cru_gpio_control";
 462
 463                                 spi-pins {
 464                                         groups = "spi_grp";
 465                                         function = "spi";
 466                                 };
 467
 468                                 pinmux_i2c: i2c-pins {
 469                                         groups = "i2c_grp";
 470                                         function = "i2c";
 471                                 };
 472
 473                                 pinmux_pwm: pwm-pins {
 474                                         groups = "pwm0_grp", "pwm1_grp",
 475                                                  "pwm2_grp", "pwm3_grp";
 476                                         function = "pwm";
 477                                 };
 478
 479                                 pinmux_uart1: uart1-pins {
 480                                         groups = "uart1_grp";
 481                                         function = "uart1";
 482                                 };
 483                         };
 484
 485                         thermal: thermal@2c0 {
 486                                 compatible = "brcm,ns-thermal";
 487                                 reg = <0x2c0 0x10>;
 488                                 #thermal-sensor-cells = <0>;
 489                         };
 490                 };
 491         };
 492
 493         srab: ethernet-switch@18007000 {
 494                 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
 495                 reg = <0x18007000 0x1000>;
 496
 497                 status = "disabled";
 498
 499                 /* ports are defined in board DTS */
 500                 ports {
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                 };
 504         };
 505
 506         rng: rng@18004000 {
 507                 compatible = "brcm,bcm5301x-rng";
 508                 reg = <0x18004000 0x14>;
 509         };
 510
 511         nand_controller: nand-controller@18028000 {
 512                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 513                 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
 514                 reg-names = "nand", "iproc-idm", "iproc-ext";
 515                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 516
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519
 520                 brcm,nand-has-wp;
 521         };
 522
 523         spi@18029200 {
 524                 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
 525                 reg = <0x18029200 0x184>,
 526                       <0x18029000 0x124>,
 527                       <0x1811b408 0x004>,
 528                       <0x180293a0 0x01c>;
 529                 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
 530                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 531                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 532                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 533                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 534                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 535                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 536                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 537                 interrupt-names = "mspi_done",
 538                                   "mspi_halted",
 539                                   "spi_lr_fullness_reached",
 540                                   "spi_lr_session_aborted",
 541                                   "spi_lr_impatient",
 542                                   "spi_lr_session_done",
 543                                   "spi_lr_overread";
 544                 clocks = <&iprocmed>;
 545                 clock-names = "iprocmed";
 546                 num-cs = <2>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549
 550                 spi_nor: flash@0 {
 551                         compatible = "jedec,spi-nor";
 552                         reg = <0>;
 553                         spi-max-frequency = <20000000>;
 554                         status = "disabled";
 555
 556                         partitions {
 557                                 compatible = "brcm,bcm947xx-cfe-partitions";
 558                         };
 559                 };
 560         };
 561
 562         thermal-zones {
 563                 cpu_thermal: cpu-thermal {
 564                         polling-delay-passive = <0>;
 565                         polling-delay = <1000>;
 566                         coefficients = <(-556) 418000>;
 567                         thermal-sensors = <&thermal>;
 568
 569                         trips {
 570                                 cpu-crit {
 571                                         temperature = <125000>;
 572                                         hysteresis = <0>;
 573                                         type = "critical";
 574                                 };
 575                         };
 576
 577                         cooling-maps {
 578                         };
 579                 };
 580         };
 581 };