arch/arm/boot/dts/am4372.dtsi

   1 /*
   2  * Device Tree Source for AM4372 SoC
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/am4.h>
  15
  16 / {
  17         compatible = "ti,am4372", "ti,am43";
  18         interrupt-parent = <&wakeupgen>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         chosen { };
  22
  23         memory@0 {
  24                 device_type = "memory";
  25                 reg = <0 0>;
  26         };
  27
  28         aliases {
  29                 i2c0 = &i2c0;
  30                 i2c1 = &i2c1;
  31                 i2c2 = &i2c2;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 serial5 = &uart5;
  38                 ethernet0 = &cpsw_emac0;
  39                 ethernet1 = &cpsw_emac1;
  40                 spi0 = &qspi;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 cpu: cpu@0 {
  47                         compatible = "arm,cortex-a9";
  48                         device_type = "cpu";
  49                         reg = <0>;
  50
  51                         clocks = <&dpll_mpu_ck>;
  52                         clock-names = "cpu";
  53
  54                         operating-points-v2 = <&cpu0_opp_table>;
  55
  56                         clock-latency = <300000>; /* From omap-cpufreq driver */
  57                 };
  58         };
  59
  60         cpu0_opp_table: opp-table {
  61                 compatible = "operating-points-v2-ti-cpu";
  62                 syscon = <&scm_conf>;
  63
  64                 opp50-300000000 {
  65                         opp-hz = /bits/ 64 <300000000>;
  66                         opp-microvolt = <950000 931000 969000>;
  67                         opp-supported-hw = <0xFF 0x01>;
  68                         opp-suspend;
  69                 };
  70
  71                 opp100-600000000 {
  72                         opp-hz = /bits/ 64 <600000000>;
  73                         opp-microvolt = <1100000 1078000 1122000>;
  74                         opp-supported-hw = <0xFF 0x04>;
  75                 };
  76
  77                 opp120-720000000 {
  78                         opp-hz = /bits/ 64 <720000000>;
  79                         opp-microvolt = <1200000 1176000 1224000>;
  80                         opp-supported-hw = <0xFF 0x08>;
  81                 };
  82
  83                 oppturbo-800000000 {
  84                         opp-hz = /bits/ 64 <800000000>;
  85                         opp-microvolt = <1260000 1234800 1285200>;
  86                         opp-supported-hw = <0xFF 0x10>;
  87                 };
  88
  89                 oppnitro-1000000000 {
  90                         opp-hz = /bits/ 64 <1000000000>;
  91                         opp-microvolt = <1325000 1298500 1351500>;
  92                         opp-supported-hw = <0xFF 0x20>;
  93                 };
  94         };
  95
  96         soc {
  97                 compatible = "ti,omap-infra";
  98                 mpu {
  99                         compatible = "ti,omap4-mpu";
 100                         ti,hwmods = "mpu";
 101                         pm-sram = <&pm_sram_code
 102                                    &pm_sram_data>;
 103                 };
 104         };
 105
 106         gic: interrupt-controller@48241000 {
 107                 compatible = "arm,cortex-a9-gic";
 108                 interrupt-controller;
 109                 #interrupt-cells = <3>;
 110                 reg = <0x48241000 0x1000>,
 111                       <0x48240100 0x0100>;
 112                 interrupt-parent = <&gic>;
 113         };
 114
 115         wakeupgen: interrupt-controller@48281000 {
 116                 compatible = "ti,omap4-wugen-mpu";
 117                 interrupt-controller;
 118                 #interrupt-cells = <3>;
 119                 reg = <0x48281000 0x1000>;
 120                 interrupt-parent = <&gic>;
 121         };
 122
 123         scu: scu@48240000 {
 124                 compatible = "arm,cortex-a9-scu";
 125                 reg = <0x48240000 0x100>;
 126         };
 127
 128         global_timer: timer@48240200 {
 129                 compatible = "arm,cortex-a9-global-timer";
 130                 reg = <0x48240200 0x100>;
 131                 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
 132                 interrupt-parent = <&gic>;
 133                 clocks = <&mpu_periphclk>;
 134         };
 135
 136         local_timer: timer@48240600 {
 137                 compatible = "arm,cortex-a9-twd-timer";
 138                 reg = <0x48240600 0x100>;
 139                 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
 140                 interrupt-parent = <&gic>;
 141                 clocks = <&mpu_periphclk>;
 142         };
 143
 144         l2-cache-controller@48242000 {
 145                 compatible = "arm,pl310-cache";
 146                 reg = <0x48242000 0x1000>;
 147                 cache-unified;
 148                 cache-level = <2>;
 149         };
 150
 151         ocp@44000000 {
 152                 compatible = "ti,am4372-l3-noc", "simple-bus";
 153                 #address-cells = <1>;
 154                 #size-cells = <1>;
 155                 ranges;
 156                 ti,hwmods = "l3_main";
 157                 ti,no-idle;
 158                 reg = <0x44000000 0x400000
 159                        0x44800000 0x400000>;
 160                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 162
 163                 l4_wkup: interconnect@44c00000 {
 164                         wkup_m3: wkup_m3@100000 {
 165                                 compatible = "ti,am4372-wkup-m3";
 166                                 reg = <0x100000 0x4000>,
 167                                       <0x180000 0x2000>;
 168                                 reg-names = "umem", "dmem";
 169                                 ti,hwmods = "wkup_m3";
 170                                 ti,pm-firmware = "am335x-pm-firmware.elf";
 171                         };
 172                 };
 173                 l4_per: interconnect@48000000 {
 174                 };
 175                 l4_fast: interconnect@4a000000 {
 176                 };
 177
 178                 emif: emif@4c000000 {
 179                         compatible = "ti,emif-am4372";
 180                         reg = <0x4c000000 0x1000000>;
 181                         ti,hwmods = "emif";
 182                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 183                         ti,no-idle;
 184                         sram = <&pm_sram_code
 185                                 &pm_sram_data>;
 186                 };
 187
 188                 edma: edma@49000000 {
 189                         compatible = "ti,edma3-tpcc";
 190                         ti,hwmods = "tpcc";
 191                         reg =   <0x49000000 0x10000>;
 192                         reg-names = "edma3_cc";
 193                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 196                         interrupt-names = "edma3_ccint", "edma3_mperr",
 197                                           "edma3_ccerrint";
 198                         dma-requests = <64>;
 199                         #dma-cells = <2>;
 200
 201                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
 202                                    <&edma_tptc2 0>;
 203
 204                         ti,edma-memcpy-channels = <58 59>;
 205                 };
 206
 207                 edma_tptc0: tptc@49800000 {
 208                         compatible = "ti,edma3-tptc";
 209                         ti,hwmods = "tptc0";
 210                         reg =   <0x49800000 0x100000>;
 211                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 212                         interrupt-names = "edma3_tcerrint";
 213                 };
 214
 215                 edma_tptc1: tptc@49900000 {
 216                         compatible = "ti,edma3-tptc";
 217                         ti,hwmods = "tptc1";
 218                         reg =   <0x49900000 0x100000>;
 219                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 220                         interrupt-names = "edma3_tcerrint";
 221                 };
 222
 223                 edma_tptc2: tptc@49a00000 {
 224                         compatible = "ti,edma3-tptc";
 225                         ti,hwmods = "tptc2";
 226                         reg =   <0x49a00000 0x100000>;
 227                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 228                         interrupt-names = "edma3_tcerrint";
 229                 };
 230
 231                 target-module@47810000 {
 232                         compatible = "ti,sysc-omap2", "ti,sysc";
 233                         reg = <0x478102fc 0x4>,
 234                               <0x47810110 0x4>,
 235                               <0x47810114 0x4>;
 236                         reg-names = "rev", "sysc", "syss";
 237                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 238                                          SYSC_OMAP2_ENAWAKEUP |
 239                                          SYSC_OMAP2_SOFTRESET |
 240                                          SYSC_OMAP2_AUTOIDLE)>;
 241                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 242                                         <SYSC_IDLE_NO>,
 243                                         <SYSC_IDLE_SMART>;
 244                         ti,syss-mask = <1>;
 245                         clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
 246                         clock-names = "fck";
 247                         #address-cells = <1>;
 248                         #size-cells = <1>;
 249                         ranges = <0x0 0x47810000 0x1000>;
 250
 251                         mmc3: mmc@0 {
 252                                 compatible = "ti,omap4-hsmmc";
 253                                 ti,needs-special-reset;
 254                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 255                                 reg = <0x0 0x1000>;
 256                         };
 257                 };
 258
 259                 sham_target: target-module@53100000 {
 260                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 261                         reg = <0x53100100 0x4>,
 262                               <0x53100110 0x4>,
 263                               <0x53100114 0x4>;
 264                         reg-names = "rev", "sysc", "syss";
 265                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 266                                          SYSC_OMAP2_AUTOIDLE)>;
 267                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 268                                         <SYSC_IDLE_NO>,
 269                                         <SYSC_IDLE_SMART>;
 270                         ti,syss-mask = <1>;
 271                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 272                         clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
 273                         clock-names = "fck";
 274                         #address-cells = <1>;
 275                         #size-cells = <1>;
 276                         ranges = <0x0 0x53100000 0x1000>;
 277
 278                         sham: sham@0 {
 279                                 compatible = "ti,omap5-sham";
 280                                 reg = <0 0x300>;
 281                                 dmas = <&edma 36 0>;
 282                                 dma-names = "rx";
 283                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 284                         };
 285                 };
 286
 287                 aes_target: target-module@53501000 {
 288                         compatible = "ti,sysc-omap2", "ti,sysc";
 289                         reg = <0x53501080 0x4>,
 290                               <0x53501084 0x4>,
 291                               <0x53501088 0x4>;
 292                         reg-names = "rev", "sysc", "syss";
 293                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 294                                          SYSC_OMAP2_AUTOIDLE)>;
 295                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 296                                         <SYSC_IDLE_NO>,
 297                                         <SYSC_IDLE_SMART>,
 298                                         <SYSC_IDLE_SMART_WKUP>;
 299                         ti,syss-mask = <1>;
 300                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 301                         clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
 302                         clock-names = "fck";
 303                         #address-cells = <1>;
 304                         #size-cells = <1>;
 305                         ranges = <0x0 0x53501000 0x1000>;
 306
 307                         aes: aes@0 {
 308                                 compatible = "ti,omap4-aes";
 309                                 reg = <0 0xa0>;
 310                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 311                                 dmas = <&edma 6 0>,
 312                                       <&edma 5 0>;
 313                                 dma-names = "tx", "rx";
 314                         };
 315                 };
 316
 317                 des_target: target-module@53701000 {
 318                         compatible = "ti,sysc-omap2", "ti,sysc";
 319                         ti,hwmods = "des";
 320                         reg = <0x53701030 0x4>,
 321                               <0x53701034 0x4>,
 322                               <0x53701038 0x4>;
 323                         reg-names = "rev", "sysc", "syss";
 324                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 325                                          SYSC_OMAP2_AUTOIDLE)>;
 326                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 327                                         <SYSC_IDLE_NO>,
 328                                         <SYSC_IDLE_SMART>,
 329                                         <SYSC_IDLE_SMART_WKUP>;
 330                         ti,syss-mask = <1>;
 331                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 332                         clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
 333                         clock-names = "fck";
 334                         #address-cells = <1>;
 335                         #size-cells = <1>;
 336                         ranges = <0 0x53701000 0x1000>;
 337
 338                         des: des@0 {
 339                                 compatible = "ti,omap4-des";
 340                                 reg = <0 0xa0>;
 341                                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 342                                 dmas = <&edma 34 0>,
 343                                        <&edma 33 0>;
 344                                 dma-names = "tx", "rx";
 345                         };
 346                 };
 347
 348                 gpmc: gpmc@50000000 {
 349                         compatible = "ti,am3352-gpmc";
 350                         ti,hwmods = "gpmc";
 351                         dmas = <&edma 52 0>;
 352                         dma-names = "rxtx";
 353                         clocks = <&l3s_gclk>;
 354                         clock-names = "fck";
 355                         reg = <0x50000000 0x2000>;
 356                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 357                         gpmc,num-cs = <7>;
 358                         gpmc,num-waitpins = <2>;
 359                         #address-cells = <2>;
 360                         #size-cells = <1>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                         gpio-controller;
 364                         #gpio-cells = <2>;
 365                         status = "disabled";
 366                 };
 367
 368                 target-module@47900000 {
 369                         compatible = "ti,sysc-omap4", "ti,sysc";
 370                         reg = <0x47900000 0x4>,
 371                               <0x47900010 0x4>;
 372                         reg-names = "rev", "sysc";
 373                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 374                                         <SYSC_IDLE_NO>,
 375                                         <SYSC_IDLE_SMART>,
 376                                         <SYSC_IDLE_SMART_WKUP>;
 377                         clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
 378                         clock-names = "fck";
 379                         #address-cells = <1>;
 380                         #size-cells = <1>;
 381                         ranges = <0x0 0x47900000 0x1000>,
 382                                  <0x30000000 0x30000000 0x4000000>;
 383
 384                         qspi: spi@0 {
 385                                 compatible = "ti,am4372-qspi";
 386                                 reg = <0 0x100>,
 387                                       <0x30000000 0x4000000>;
 388                                 reg-names = "qspi_base", "qspi_mmap";
 389                                 clocks = <&dpll_per_m2_div4_ck>;
 390                                 clock-names = "fck";
 391                                 #address-cells = <1>;
 392                                 #size-cells = <0>;
 393                                 interrupts = <0 138 0x4>;
 394                                 num-cs = <4>;
 395                         };
 396                 };
 397
 398                 dss: dss@4832a000 {
 399                         compatible = "ti,omap3-dss";
 400                         reg = <0x4832a000 0x200>;
 401                         status = "disabled";
 402                         ti,hwmods = "dss_core";
 403                         clocks = <&disp_clk>;
 404                         clock-names = "fck";
 405                         #address-cells = <1>;
 406                         #size-cells = <1>;
 407                         ranges;
 408
 409                         dispc: dispc@4832a400 {
 410                                 compatible = "ti,omap3-dispc";
 411                                 reg = <0x4832a400 0x400>;
 412                                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 413                                 ti,hwmods = "dss_dispc";
 414                                 clocks = <&disp_clk>;
 415                                 clock-names = "fck";
 416
 417                                 max-memory-bandwidth = <230000000>;
 418                         };
 419
 420                         rfbi: rfbi@4832a800 {
 421                                 compatible = "ti,omap3-rfbi";
 422                                 reg = <0x4832a800 0x100>;
 423                                 ti,hwmods = "dss_rfbi";
 424                                 clocks = <&disp_clk>;
 425                                 clock-names = "fck";
 426                                 status = "disabled";
 427                         };
 428                 };
 429
 430                 ocmcram: sram@40300000 {
 431                         compatible = "mmio-sram";
 432                         reg = <0x40300000 0x40000>; /* 256k */
 433                         ranges = <0x0 0x40300000 0x40000>;
 434                         #address-cells = <1>;
 435                         #size-cells = <1>;
 436
 437                         pm_sram_code: pm-code-sram@0 {
 438                                 compatible = "ti,sram";
 439                                 reg = <0x0 0x1000>;
 440                                 protect-exec;
 441                         };
 442
 443                         pm_sram_data: pm-data-sram@1000 {
 444                                 compatible = "ti,sram";
 445                                 reg = <0x1000 0x1000>;
 446                                 pool;
 447                         };
 448                 };
 449         };
 450 };
 451
 452 #include "am437x-l4.dtsi"
 453 #include "am43xx-clocks.dtsi"
 454
 455 &prcm {
 456         prm_gfx: prm@400 {
 457                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 458                 reg = <0x400 0x100>;
 459                 #reset-cells = <1>;
 460         };
 461
 462         prm_per: prm@800 {
 463                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 464                 reg = <0x800 0x100>;
 465                 #reset-cells = <1>;
 466         };
 467
 468         prm_wkup: prm@2000 {
 469                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 470                 reg = <0x2000 0x100>;
 471                 #reset-cells = <1>;
 472         };
 473
 474         prm_device: prm@4000 {
 475                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 476                 reg = <0x4000 0x100>;
 477                 #reset-cells = <1>;
 478         };
 479 };