1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
9 select ARCH_HAS_CURRENT_STACK_POINTER
10 select ARCH_HAS_DEBUG_VIRTUAL if MMU
11 select ARCH_HAS_DMA_ALLOC if MMU
12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
13 select ARCH_HAS_ELF_RANDOMIZE
14 select ARCH_HAS_FORTIFY_SOURCE
15 select ARCH_HAS_KEEPINITRD
17 select ARCH_HAS_MEMBARRIER_SYNC_CORE
18 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
19 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
20 select ARCH_HAS_SETUP_DMA_OPS
21 select ARCH_HAS_SET_MEMORY
23 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
24 select ARCH_HAS_STRICT_MODULE_RWX if MMU
25 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
26 select ARCH_HAS_SYNC_DMA_FOR_CPU
27 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_KEEP_MEMBLOCK
32 select ARCH_HAS_UBSAN_SANITIZE_ALL
33 select ARCH_MIGHT_HAVE_PC_PARPORT
34 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
35 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
36 select ARCH_SUPPORTS_ATOMIC_RMW
37 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
38 select ARCH_SUPPORTS_PER_VMA_LOCK
39 select ARCH_USE_BUILTIN_BSWAP
40 select ARCH_USE_CMPXCHG_LOCKREF
41 select ARCH_USE_MEMTEST
42 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
43 select ARCH_WANT_GENERAL_HUGETLB
44 select ARCH_WANT_IPC_PARSE_VERSION
45 select ARCH_WANT_LD_ORPHAN_WARN
46 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
47 select BUILDTIME_TABLE_SORT if MMU
48 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
49 select CLONE_BACKWARDS
50 select CPU_PM if SUSPEND || CPU_IDLE
51 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
52 select DMA_DECLARE_COHERENT
53 select DMA_GLOBAL_POOL if !MMU
55 select DMA_NONCOHERENT_MMAP if MMU
57 select EDAC_ATOMIC_SCRUB
58 select GENERIC_ALLOCATOR
59 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
60 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
61 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
62 select GENERIC_IRQ_IPI if SMP
63 select GENERIC_CPU_AUTOPROBE
64 select GENERIC_EARLY_IOREMAP
65 select GENERIC_IDLE_POLL_SETUP
66 select GENERIC_IRQ_MULTI_HANDLER
67 select GENERIC_IRQ_PROBE
68 select GENERIC_IRQ_SHOW
69 select GENERIC_IRQ_SHOW_LEVEL
70 select GENERIC_LIB_DEVMEM_IS_ALLOWED
71 select GENERIC_PCI_IOMAP
72 select GENERIC_SCHED_CLOCK
73 select GENERIC_SMP_IDLE_THREAD
74 select HARDIRQS_SW_RESEND
76 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
77 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
78 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
79 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
80 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
81 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
82 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
83 select HAVE_ARCH_MMAP_RND_BITS if MMU
84 select HAVE_ARCH_PFN_VALID
85 select HAVE_ARCH_SECCOMP
86 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
87 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
88 select HAVE_ARCH_TRACEHOOK
89 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
90 select HAVE_ARM_SMCCC if CPU_V7
91 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
92 select HAVE_CONTEXT_TRACKING_USER
93 select HAVE_C_RECORDMCOUNT
94 select HAVE_BUILDTIME_MCOUNT_SORT
95 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
96 select HAVE_DMA_CONTIGUOUS if MMU
97 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
98 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
99 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
100 select HAVE_EXIT_THREAD
101 select HAVE_FAST_GUP if ARM_LPAE
102 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
103 select HAVE_FUNCTION_ERROR_INJECTION
104 select HAVE_FUNCTION_GRAPH_TRACER
105 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
106 select HAVE_GCC_PLUGINS
107 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
108 select HAVE_IRQ_TIME_ACCOUNTING
109 select HAVE_KERNEL_GZIP
110 select HAVE_KERNEL_LZ4
111 select HAVE_KERNEL_LZMA
112 select HAVE_KERNEL_LZO
113 select HAVE_KERNEL_XZ
114 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
115 select HAVE_KRETPROBES if HAVE_KPROBES
116 select HAVE_MOD_ARCH_SPECIFIC
118 select HAVE_OPTPROBES if !THUMB2_KERNEL
119 select HAVE_PCI if MMU
120 select HAVE_PERF_EVENTS
121 select HAVE_PERF_REGS
122 select HAVE_PERF_USER_STACK_DUMP
123 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
124 select HAVE_REGS_AND_STACK_ACCESS_API
126 select HAVE_STACKPROTECTOR
127 select HAVE_SYSCALL_TRACEPOINTS
129 select HAVE_VIRT_CPU_ACCOUNTING_GEN
130 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
131 select IRQ_FORCED_THREADING
132 select LOCK_MM_AND_FIND_VMA
133 select MODULES_USE_ELF_REL
134 select NEED_DMA_MAP_STATE
135 select OF_EARLY_FLATTREE if OF
137 select OLD_SIGSUSPEND3
138 select PCI_DOMAINS_GENERIC if PCI
139 select PCI_SYSCALL if PCI
140 select PERF_USE_VMALLOC
142 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
143 select SYS_SUPPORTS_APM_EMULATION
144 select THREAD_INFO_IN_TASK
145 select TIMER_OF if OF
146 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
147 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
148 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
149 # Above selects are sorted alphabetically; please add new ones
150 # according to that. Thanks.
152 The ARM series is a line of low-power-consumption RISC chip designs
153 licensed by ARM Ltd and targeted at embedded applications and
154 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
155 manufactured, but legacy ARM-based PC hardware remains popular in
156 Europe. There is an ARM Linux project with a web page at
157 <http://www.arm.linux.org.uk/>.
159 config ARM_HAS_GROUP_RELOCS
161 depends on !LD_IS_LLD || LLD_VERSION >= 140000
162 depends on !COMPILE_TEST
164 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
165 relocations, which have been around for a long time, but were not
166 supported in LLD until version 14. The combined range is -/+ 256 MiB,
167 which is usually sufficient, but not for allyesconfig, so we disable
168 this feature when doing compile testing.
170 config ARM_DMA_USE_IOMMU
172 select NEED_SG_DMA_LENGTH
176 config ARM_DMA_IOMMU_ALIGNMENT
177 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
181 DMA mapping framework by default aligns all buffers to the smallest
182 PAGE_SIZE order which is greater than or equal to the requested buffer
183 size. This works well for buffers up to a few hundreds kilobytes, but
184 for larger buffers it just a waste of address space. Drivers which has
185 relatively small addressing window (like 64Mib) might run out of
186 virtual space with just a few allocations.
188 With this parameter you can specify the maximum PAGE_SIZE order for
189 DMA IOMMU buffers. Larger buffers will be aligned only to this
190 specified order. The order is expressed as a power of two multiplied
195 config SYS_SUPPORTS_APM_EMULATION
200 select GENERIC_ALLOCATOR
211 config STACKTRACE_SUPPORT
215 config LOCKDEP_SUPPORT
219 config ARCH_HAS_ILOG2_U32
222 config ARCH_HAS_ILOG2_U64
225 config ARCH_HAS_BANDGAP
228 config FIX_EARLYCON_MEM
231 config GENERIC_HWEIGHT
235 config GENERIC_CALIBRATE_DELAY
239 config ARCH_MAY_HAVE_PC_FDC
242 config ARCH_SUPPORTS_UPROBES
245 config GENERIC_ISA_DMA
254 config ARM_PATCH_PHYS_VIRT
255 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
259 Patch phys-to-virt and virt-to-phys translation functions at
260 boot and module load time according to the position of the
261 kernel in system memory.
263 This can only be used with non-XIP MMU kernels where the base
264 of physical memory is at a 2 MiB boundary.
266 Only disable this option if you know that you do not require
267 this feature (eg, building a kernel for a single machine) and
268 you need to shrink the kernel to the minimal size.
270 config NEED_MACH_IO_H
273 Select this when mach/io.h is required to provide special
274 definitions for this platform. The need for mach/io.h should
275 be avoided when possible.
277 config NEED_MACH_MEMORY_H
280 Select this when mach/memory.h is required to provide special
281 definitions for this platform. The need for mach/memory.h should
282 be avoided when possible.
285 hex "Physical address of main memory" if MMU
286 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
287 default DRAM_BASE if !MMU
288 default 0x00000000 if ARCH_FOOTBRIDGE
289 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
290 default 0xa0000000 if ARCH_PXA
291 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
294 Please provide the physical address corresponding to the
295 location of main memory in your system.
301 config PGTABLE_LEVELS
303 default 3 if ARM_LPAE
309 bool "MMU-based Paged Memory Management Support"
312 Select if you want MMU-based virtualised addressing space
313 support by paged memory management. If unsure, say 'Y'.
315 config ARM_SINGLE_ARMV7M
321 config ARCH_MMAP_RND_BITS_MIN
324 config ARCH_MMAP_RND_BITS_MAX
325 default 14 if PAGE_OFFSET=0x40000000
326 default 15 if PAGE_OFFSET=0x80000000
329 config ARCH_MULTIPLATFORM
330 bool "Require kernel to be portable to multiple machines" if EXPERT
331 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
334 In general, all Arm machines can be supported in a single
335 kernel image, covering either Armv4/v5 or Armv6/v7.
337 However, some configuration options require hardcoding machine
338 specific physical addresses or enable errata workarounds that may
339 break other machines.
341 Selecting N here allows using those options, including
342 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
344 source "arch/arm/Kconfig.platforms"
347 # This is sorted alphabetically by mach-* pathname. However, plat-*
348 # Kconfigs may be included either alphabetically (according to the
349 # plat- suffix) or along side the corresponding mach-* source.
351 source "arch/arm/mach-actions/Kconfig"
353 source "arch/arm/mach-alpine/Kconfig"
355 source "arch/arm/mach-artpec/Kconfig"
357 source "arch/arm/mach-aspeed/Kconfig"
359 source "arch/arm/mach-at91/Kconfig"
361 source "arch/arm/mach-axxia/Kconfig"
363 source "arch/arm/mach-bcm/Kconfig"
365 source "arch/arm/mach-berlin/Kconfig"
367 source "arch/arm/mach-clps711x/Kconfig"
369 source "arch/arm/mach-davinci/Kconfig"
371 source "arch/arm/mach-digicolor/Kconfig"
373 source "arch/arm/mach-dove/Kconfig"
375 source "arch/arm/mach-ep93xx/Kconfig"
377 source "arch/arm/mach-exynos/Kconfig"
379 source "arch/arm/mach-footbridge/Kconfig"
381 source "arch/arm/mach-gemini/Kconfig"
383 source "arch/arm/mach-highbank/Kconfig"
385 source "arch/arm/mach-hisi/Kconfig"
387 source "arch/arm/mach-hpe/Kconfig"
389 source "arch/arm/mach-imx/Kconfig"
391 source "arch/arm/mach-ixp4xx/Kconfig"
393 source "arch/arm/mach-keystone/Kconfig"
395 source "arch/arm/mach-lpc32xx/Kconfig"
397 source "arch/arm/mach-mediatek/Kconfig"
399 source "arch/arm/mach-meson/Kconfig"
401 source "arch/arm/mach-milbeaut/Kconfig"
403 source "arch/arm/mach-mmp/Kconfig"
405 source "arch/arm/mach-mstar/Kconfig"
407 source "arch/arm/mach-mv78xx0/Kconfig"
409 source "arch/arm/mach-mvebu/Kconfig"
411 source "arch/arm/mach-mxs/Kconfig"
413 source "arch/arm/mach-nomadik/Kconfig"
415 source "arch/arm/mach-npcm/Kconfig"
417 source "arch/arm/mach-omap1/Kconfig"
419 source "arch/arm/mach-omap2/Kconfig"
421 source "arch/arm/mach-orion5x/Kconfig"
423 source "arch/arm/mach-pxa/Kconfig"
425 source "arch/arm/mach-qcom/Kconfig"
427 source "arch/arm/mach-realtek/Kconfig"
429 source "arch/arm/mach-rpc/Kconfig"
431 source "arch/arm/mach-rockchip/Kconfig"
433 source "arch/arm/mach-s3c/Kconfig"
435 source "arch/arm/mach-s5pv210/Kconfig"
437 source "arch/arm/mach-sa1100/Kconfig"
439 source "arch/arm/mach-shmobile/Kconfig"
441 source "arch/arm/mach-socfpga/Kconfig"
443 source "arch/arm/mach-spear/Kconfig"
445 source "arch/arm/mach-sti/Kconfig"
447 source "arch/arm/mach-stm32/Kconfig"
449 source "arch/arm/mach-sunxi/Kconfig"
451 source "arch/arm/mach-tegra/Kconfig"
453 source "arch/arm/mach-ux500/Kconfig"
455 source "arch/arm/mach-versatile/Kconfig"
457 source "arch/arm/mach-vt8500/Kconfig"
459 source "arch/arm/mach-zynq/Kconfig"
461 # ARMv7-M architecture
463 bool "NXP LPC18xx/LPC43xx"
464 depends on ARM_SINGLE_ARMV7M
465 select ARCH_HAS_RESET_CONTROLLER
467 select CLKSRC_LPC32XX
470 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
471 high performance microcontrollers.
474 bool "ARM MPS2 platform"
475 depends on ARM_SINGLE_ARMV7M
479 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
480 with a range of available cores like Cortex-M3/M4/M7.
482 Please, note that depends which Application Note is used memory map
483 for the platform may vary, so adjustment of RAM base might be needed.
485 # Definitions to make life easier
492 select GENERIC_IRQ_CHIP
495 config PLAT_ORION_LEGACY
499 config PLAT_VERSATILE
502 source "arch/arm/mm/Kconfig"
505 bool "Enable iWMMXt support"
506 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
507 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
509 Enable support for iWMMXt context switching at run time if
510 running on a CPU that supports it.
513 source "arch/arm/Kconfig-nommu"
516 config PJ4B_ERRATA_4742
517 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
518 depends on CPU_PJ4B && MACH_ARMADA_370
521 When coming out of either a Wait for Interrupt (WFI) or a Wait for
522 Event (WFE) IDLE states, a specific timing sensitivity exists between
523 the retiring WFI/WFE instructions and the newly issued subsequent
524 instructions. This sensitivity can result in a CPU hang scenario.
526 The software must insert either a Data Synchronization Barrier (DSB)
527 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
530 config ARM_ERRATA_326103
531 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
534 Executing a SWP instruction to read-only memory does not set bit 11
535 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
536 treat the access as a read, preventing a COW from occurring and
537 causing the faulting task to livelock.
539 config ARM_ERRATA_411920
540 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
541 depends on CPU_V6 || CPU_V6K
543 Invalidation of the Instruction Cache operation can
544 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
545 It does not affect the MPCore. This option enables the ARM Ltd.
546 recommended workaround.
548 config ARM_ERRATA_430973
549 bool "ARM errata: Stale prediction on replaced interworking branch"
552 This option enables the workaround for the 430973 Cortex-A8
553 r1p* erratum. If a code sequence containing an ARM/Thumb
554 interworking branch is replaced with another code sequence at the
555 same virtual address, whether due to self-modifying code or virtual
556 to physical address re-mapping, Cortex-A8 does not recover from the
557 stale interworking branch prediction. This results in Cortex-A8
558 executing the new code sequence in the incorrect ARM or Thumb state.
559 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
560 and also flushes the branch target cache at every context switch.
561 Note that setting specific bits in the ACTLR register may not be
562 available in non-secure mode.
564 config ARM_ERRATA_458693
565 bool "ARM errata: Processor deadlock when a false hazard is created"
567 depends on !ARCH_MULTIPLATFORM
569 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
570 erratum. For very specific sequences of memory operations, it is
571 possible for a hazard condition intended for a cache line to instead
572 be incorrectly associated with a different cache line. This false
573 hazard might then cause a processor deadlock. The workaround enables
574 the L1 caching of the NEON accesses and disables the PLD instruction
575 in the ACTLR register. Note that setting specific bits in the ACTLR
576 register may not be available in non-secure mode and thus is not
577 available on a multiplatform kernel. This should be applied by the
580 config ARM_ERRATA_460075
581 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
583 depends on !ARCH_MULTIPLATFORM
585 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
586 erratum. Any asynchronous access to the L2 cache may encounter a
587 situation in which recent store transactions to the L2 cache are lost
588 and overwritten with stale memory contents from external memory. The
589 workaround disables the write-allocate mode for the L2 cache via the
590 ACTLR register. Note that setting specific bits in the ACTLR register
591 may not be available in non-secure mode and thus is not available on
592 a multiplatform kernel. This should be applied by the bootloader
595 config ARM_ERRATA_742230
596 bool "ARM errata: DMB operation may be faulty"
597 depends on CPU_V7 && SMP
598 depends on !ARCH_MULTIPLATFORM
600 This option enables the workaround for the 742230 Cortex-A9
601 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
602 between two write operations may not ensure the correct visibility
603 ordering of the two writes. This workaround sets a specific bit in
604 the diagnostic register of the Cortex-A9 which causes the DMB
605 instruction to behave as a DSB, ensuring the correct behaviour of
606 the two writes. Note that setting specific bits in the diagnostics
607 register may not be available in non-secure mode and thus is not
608 available on a multiplatform kernel. This should be applied by the
611 config ARM_ERRATA_742231
612 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
613 depends on CPU_V7 && SMP
614 depends on !ARCH_MULTIPLATFORM
616 This option enables the workaround for the 742231 Cortex-A9
617 (r2p0..r2p2) erratum. Under certain conditions, specific to the
618 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
619 accessing some data located in the same cache line, may get corrupted
620 data due to bad handling of the address hazard when the line gets
621 replaced from one of the CPUs at the same time as another CPU is
622 accessing it. This workaround sets specific bits in the diagnostic
623 register of the Cortex-A9 which reduces the linefill issuing
624 capabilities of the processor. Note that setting specific bits in the
625 diagnostics register may not be available in non-secure mode and thus
626 is not available on a multiplatform kernel. This should be applied by
627 the bootloader instead.
629 config ARM_ERRATA_643719
630 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
631 depends on CPU_V7 && SMP
634 This option enables the workaround for the 643719 Cortex-A9 (prior to
635 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
636 register returns zero when it should return one. The workaround
637 corrects this value, ensuring cache maintenance operations which use
638 it behave as intended and avoiding data corruption.
640 config ARM_ERRATA_720789
641 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
644 This option enables the workaround for the 720789 Cortex-A9 (prior to
645 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
646 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
647 As a consequence of this erratum, some TLB entries which should be
648 invalidated are not, resulting in an incoherency in the system page
649 tables. The workaround changes the TLB flushing routines to invalidate
650 entries regardless of the ASID.
652 config ARM_ERRATA_743622
653 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
655 depends on !ARCH_MULTIPLATFORM
657 This option enables the workaround for the 743622 Cortex-A9
658 (r2p*) erratum. Under very rare conditions, a faulty
659 optimisation in the Cortex-A9 Store Buffer may lead to data
660 corruption. This workaround sets a specific bit in the diagnostic
661 register of the Cortex-A9 which disables the Store Buffer
662 optimisation, preventing the defect from occurring. This has no
663 visible impact on the overall performance or power consumption of the
664 processor. Note that setting specific bits in the diagnostics register
665 may not be available in non-secure mode and thus is not available on a
666 multiplatform kernel. This should be applied by the bootloader instead.
668 config ARM_ERRATA_751472
669 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
671 depends on !ARCH_MULTIPLATFORM
673 This option enables the workaround for the 751472 Cortex-A9 (prior
674 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
675 completion of a following broadcasted operation if the second
676 operation is received by a CPU before the ICIALLUIS has completed,
677 potentially leading to corrupted entries in the cache or TLB.
678 Note that setting specific bits in the diagnostics register may
679 not be available in non-secure mode and thus is not available on
680 a multiplatform kernel. This should be applied by the bootloader
683 config ARM_ERRATA_754322
684 bool "ARM errata: possible faulty MMU translations following an ASID switch"
687 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
688 r3p*) erratum. A speculative memory access may cause a page table walk
689 which starts prior to an ASID switch but completes afterwards. This
690 can populate the micro-TLB with a stale entry which may be hit with
691 the new ASID. This workaround places two dsb instructions in the mm
692 switching code so that no page table walks can cross the ASID switch.
694 config ARM_ERRATA_754327
695 bool "ARM errata: no automatic Store Buffer drain"
696 depends on CPU_V7 && SMP
698 This option enables the workaround for the 754327 Cortex-A9 (prior to
699 r2p0) erratum. The Store Buffer does not have any automatic draining
700 mechanism and therefore a livelock may occur if an external agent
701 continuously polls a memory location waiting to observe an update.
702 This workaround defines cpu_relax() as smp_mb(), preventing correctly
703 written polling loops from denying visibility of updates to memory.
705 config ARM_ERRATA_364296
706 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
709 This options enables the workaround for the 364296 ARM1136
710 r0p2 erratum (possible cache data corruption with
711 hit-under-miss enabled). It sets the undocumented bit 31 in
712 the auxiliary control register and the FI bit in the control
713 register, thus disabling hit-under-miss without putting the
714 processor into full low interrupt latency mode. ARM11MPCore
717 config ARM_ERRATA_764369
718 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
719 depends on CPU_V7 && SMP
721 This option enables the workaround for erratum 764369
722 affecting Cortex-A9 MPCore with two or more processors (all
723 current revisions). Under certain timing circumstances, a data
724 cache line maintenance operation by MVA targeting an Inner
725 Shareable memory region may fail to proceed up to either the
726 Point of Coherency or to the Point of Unification of the
727 system. This workaround adds a DSB instruction before the
728 relevant cache maintenance functions and sets a specific bit
729 in the diagnostic control register of the SCU.
731 config ARM_ERRATA_764319
732 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
735 This option enables the workaround for the 764319 Cortex A-9 erratum.
736 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
737 unexpected Undefined Instruction exception when the DBGSWENABLE
738 external pin is set to 0, even when the CP14 accesses are performed
739 from a privileged mode. This work around catches the exception in a
740 way the kernel does not stop execution.
742 config ARM_ERRATA_775420
743 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
746 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
747 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
748 operation aborts with MMU exception, it might cause the processor
749 to deadlock. This workaround puts DSB before executing ISB if
750 an abort may occur on cache maintenance.
752 config ARM_ERRATA_798181
753 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
754 depends on CPU_V7 && SMP
756 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
757 adequately shooting down all use of the old entries. This
758 option enables the Linux kernel workaround for this erratum
759 which sends an IPI to the CPUs that are running the same ASID
760 as the one being invalidated.
762 config ARM_ERRATA_773022
763 bool "ARM errata: incorrect instructions may be executed from loop buffer"
766 This option enables the workaround for the 773022 Cortex-A15
767 (up to r0p4) erratum. In certain rare sequences of code, the
768 loop buffer may deliver incorrect instructions. This
769 workaround disables the loop buffer to avoid the erratum.
771 config ARM_ERRATA_818325_852422
772 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
775 This option enables the workaround for:
776 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
777 instruction might deadlock. Fixed in r0p1.
778 - Cortex-A12 852422: Execution of a sequence of instructions might
779 lead to either a data corruption or a CPU deadlock. Not fixed in
780 any Cortex-A12 cores yet.
781 This workaround for all both errata involves setting bit[12] of the
782 Feature Register. This bit disables an optimisation applied to a
783 sequence of 2 instructions that use opposing condition codes.
785 config ARM_ERRATA_821420
786 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
789 This option enables the workaround for the 821420 Cortex-A12
790 (all revs) erratum. In very rare timing conditions, a sequence
791 of VMOV to Core registers instructions, for which the second
792 one is in the shadow of a branch or abort, can lead to a
793 deadlock when the VMOV instructions are issued out-of-order.
795 config ARM_ERRATA_825619
796 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
799 This option enables the workaround for the 825619 Cortex-A12
800 (all revs) erratum. Within rare timing constraints, executing a
801 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
802 and Device/Strongly-Ordered loads and stores might cause deadlock
804 config ARM_ERRATA_857271
805 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
808 This option enables the workaround for the 857271 Cortex-A12
809 (all revs) erratum. Under very rare timing conditions, the CPU might
810 hang. The workaround is expected to have a < 1% performance impact.
812 config ARM_ERRATA_852421
813 bool "ARM errata: A17: DMB ST might fail to create order between stores"
816 This option enables the workaround for the 852421 Cortex-A17
817 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
818 execution of a DMB ST instruction might fail to properly order
819 stores from GroupA and stores from GroupB.
821 config ARM_ERRATA_852423
822 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
825 This option enables the workaround for:
826 - Cortex-A17 852423: Execution of a sequence of instructions might
827 lead to either a data corruption or a CPU deadlock. Not fixed in
828 any Cortex-A17 cores yet.
829 This is identical to Cortex-A12 erratum 852422. It is a separate
830 config option from the A12 erratum due to the way errata are checked
833 config ARM_ERRATA_857272
834 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
837 This option enables the workaround for the 857272 Cortex-A17 erratum.
838 This erratum is not known to be fixed in any A17 revision.
839 This is identical to Cortex-A12 erratum 857271. It is a separate
840 config option from the A12 erratum due to the way errata are checked
845 source "arch/arm/common/Kconfig"
852 Find out whether you have ISA slots on your motherboard. ISA is the
853 name of a bus system, i.e. the way the CPU talks to the other stuff
854 inside your box. Other bus systems are PCI, EISA, MicroChannel
855 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
856 newer boards don't support it. If you have ISA, say Y, otherwise N.
858 # Select ISA DMA interface
862 config ARM_ERRATA_814220
863 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
866 The v7 ARM states that all cache and branch predictor maintenance
867 operations that do not specify an address execute, relative to
868 each other, in program order.
869 However, because of this erratum, an L2 set/way cache maintenance
870 operation can overtake an L1 set/way cache maintenance operation.
871 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
876 menu "Kernel Features"
881 This option should be selected by machines which have an SMP-
884 The only effect of this option is to make the SMP-related
885 options available to the user for configuration.
888 bool "Symmetric Multi-Processing"
889 depends on CPU_V6K || CPU_V7
891 depends on MMU || ARM_MPU
894 This enables support for systems with more than one CPU. If you have
895 a system with only one CPU, say N. If you have a system with more
898 If you say N here, the kernel will run on uni- and multiprocessor
899 machines, but will use only one CPU of a multiprocessor machine. If
900 you say Y here, the kernel will run on many, but not all,
901 uniprocessor machines. On a uniprocessor machine, the kernel
902 will run faster if you say N here.
904 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
905 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
906 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
908 If you don't know what to do here, say N.
911 bool "Allow booting SMP kernel on uniprocessor systems"
912 depends on SMP && MMU
915 SMP kernels contain instructions which fail on non-SMP processors.
916 Enabling this option allows the kernel to modify itself to make
917 these instructions safe. Disabling it allows about 1K of space
920 If you don't know what to do here, say Y.
923 config CURRENT_POINTER_IN_TPIDRURO
925 depends on CPU_32v6K && !CPU_V6
929 select HAVE_IRQ_EXIT_ON_IRQ_STACK
930 select HAVE_SOFTIRQ_ON_OWN_STACK
932 config ARM_CPU_TOPOLOGY
933 bool "Support cpu topology definition"
934 depends on SMP && CPU_V7
937 Support ARM cpu topology definition. The MPIDR register defines
938 affinity between processors which is then used to describe the cpu
939 topology of an ARM System.
942 bool "Multi-core scheduler support"
943 depends on ARM_CPU_TOPOLOGY
945 Multi-core scheduler support improves the CPU scheduler's decision
946 making when dealing with multi-core CPU chips at a cost of slightly
947 increased overhead in some places. If unsure say N here.
950 bool "SMT scheduler support"
951 depends on ARM_CPU_TOPOLOGY
953 Improves the CPU scheduler's decision making when dealing with
954 MultiThreading at a cost of slightly increased overhead in some
955 places. If unsure say N here.
960 This option enables support for the ARM snoop control unit
962 config HAVE_ARM_ARCH_TIMER
963 bool "Architected timer support"
965 select ARM_ARCH_TIMER
967 This option enables support for the ARM architected timer
972 This options enables support for the ARM timer and watchdog unit
975 bool "Multi-Cluster Power Management"
976 depends on CPU_V7 && SMP
978 This option provides the common power management infrastructure
979 for (multi-)cluster based systems, such as big.LITTLE based
982 config MCPM_QUAD_CLUSTER
986 To avoid wasting resources unnecessarily, MCPM only supports up
987 to 2 clusters by default.
988 Platforms with 3 or 4 clusters that use MCPM must select this
989 option to allow the additional clusters to be managed.
992 bool "big.LITTLE support (Experimental)"
993 depends on CPU_V7 && SMP
996 This option enables support selections for the big.LITTLE
1000 bool "big.LITTLE switcher support"
1001 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1004 The big.LITTLE "switcher" provides the core functionality to
1005 transparently handle transition between a cluster of A15's
1006 and a cluster of A7's in a big.LITTLE system.
1008 config BL_SWITCHER_DUMMY_IF
1009 tristate "Simple big.LITTLE switcher user interface"
1010 depends on BL_SWITCHER && DEBUG_KERNEL
1012 This is a simple and dummy char dev interface to control
1013 the big.LITTLE switcher core code. It is meant for
1014 debugging purposes only.
1017 prompt "Memory split"
1021 Select the desired split between kernel and user memory.
1023 If you are not absolutely sure what you are doing, leave this
1027 bool "3G/1G user/kernel split"
1028 config VMSPLIT_3G_OPT
1029 depends on !ARM_LPAE
1030 bool "3G/1G user/kernel split (for full 1G low memory)"
1032 bool "2G/2G user/kernel split"
1034 bool "1G/3G user/kernel split"
1039 default PHYS_OFFSET if !MMU
1040 default 0x40000000 if VMSPLIT_1G
1041 default 0x80000000 if VMSPLIT_2G
1042 default 0xB0000000 if VMSPLIT_3G_OPT
1045 config KASAN_SHADOW_OFFSET
1048 default 0x1f000000 if PAGE_OFFSET=0x40000000
1049 default 0x5f000000 if PAGE_OFFSET=0x80000000
1050 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1051 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1055 int "Maximum number of CPUs (2-32)"
1056 range 2 16 if DEBUG_KMAP_LOCAL
1057 range 2 32 if !DEBUG_KMAP_LOCAL
1061 The maximum number of CPUs that the kernel can support.
1062 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1063 debugging is enabled, which uses half of the per-CPU fixmap
1064 slots as guard regions.
1067 bool "Support for hot-pluggable CPUs"
1069 select GENERIC_IRQ_MIGRATION
1071 Say Y here to experiment with turning CPUs off and on. CPUs
1072 can be controlled through /sys/devices/system/cpu.
1075 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1076 depends on HAVE_ARM_SMCCC
1079 Say Y here if you want Linux to communicate with system firmware
1080 implementing the PSCI specification for CPU-centric power
1081 management operations described in ARM document number ARM DEN
1082 0022A ("Power State Coordination Interface System Software on
1087 default 128 if SOC_AT91RM9200
1091 depends on HZ_FIXED = 0
1092 prompt "Timer frequency"
1116 default HZ_FIXED if HZ_FIXED != 0
1117 default 100 if HZ_100
1118 default 200 if HZ_200
1119 default 250 if HZ_250
1120 default 300 if HZ_300
1121 default 500 if HZ_500
1125 def_bool HIGH_RES_TIMERS
1127 config THUMB2_KERNEL
1128 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1129 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1130 default y if CPU_THUMBONLY
1133 By enabling this option, the kernel will be compiled in
1138 config ARM_PATCH_IDIV
1139 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1143 The ARM compiler inserts calls to __aeabi_idiv() and
1144 __aeabi_uidiv() when it needs to perform division on signed
1145 and unsigned integers. Some v7 CPUs have support for the sdiv
1146 and udiv instructions that can be used to implement those
1149 Enabling this option allows the kernel to modify itself to
1150 replace the first two instructions of these library functions
1151 with the sdiv or udiv plus "bx lr" instructions when the CPU
1152 it is running on supports them. Typically this will be faster
1153 and less power intensive than running the original library
1154 code to do integer division.
1157 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1158 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1159 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1161 This option allows for the kernel to be compiled using the latest
1162 ARM ABI (aka EABI). This is only useful if you are using a user
1163 space environment that is also compiled with EABI.
1165 Since there are major incompatibilities between the legacy ABI and
1166 EABI, especially with regard to structure member alignment, this
1167 option also changes the kernel syscall calling convention to
1168 disambiguate both ABIs and allow for backward compatibility support
1169 (selected with CONFIG_OABI_COMPAT).
1171 To use this you need GCC version 4.0.0 or later.
1174 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1175 depends on AEABI && !THUMB2_KERNEL
1177 This option preserves the old syscall interface along with the
1178 new (ARM EABI) one. It also provides a compatibility layer to
1179 intercept syscalls that have structure arguments which layout
1180 in memory differs between the legacy ABI and the new ARM EABI
1181 (only for non "thumb" binaries). This option adds a tiny
1182 overhead to all syscalls and produces a slightly larger kernel.
1184 The seccomp filter system will not be available when this is
1185 selected, since there is no way yet to sensibly distinguish
1186 between calling conventions during filtering.
1188 If you know you'll be using only pure EABI user space then you
1189 can say N here. If this option is not selected and you attempt
1190 to execute a legacy ABI binary then the result will be
1191 UNPREDICTABLE (in fact it can be predicted that it won't work
1192 at all). If in doubt say N.
1194 config ARCH_SELECT_MEMORY_MODEL
1197 config ARCH_FLATMEM_ENABLE
1198 def_bool !(ARCH_RPC || ARCH_SA1100)
1200 config ARCH_SPARSEMEM_ENABLE
1201 def_bool !ARCH_FOOTBRIDGE
1202 select SPARSEMEM_STATIC if SPARSEMEM
1205 bool "High Memory Support"
1208 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1210 The address space of ARM processors is only 4 Gigabytes large
1211 and it has to accommodate user address space, kernel address
1212 space as well as some memory mapped IO. That means that, if you
1213 have a large amount of physical memory and/or IO, not all of the
1214 memory can be "permanently mapped" by the kernel. The physical
1215 memory that is not permanently mapped is called "high memory".
1217 Depending on the selected kernel/user memory split, minimum
1218 vmalloc space and actual amount of RAM, you may not need this
1219 option which should result in a slightly faster kernel.
1224 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1228 The VM uses one page of physical memory for each page table.
1229 For systems with a lot of processes, this can use a lot of
1230 precious low memory, eventually leading to low memory being
1231 consumed by page tables. Setting this option will allow
1232 user-space 2nd level page tables to reside in high memory.
1234 config CPU_SW_DOMAIN_PAN
1235 bool "Enable use of CPU domains to implement privileged no-access"
1236 depends on MMU && !ARM_LPAE
1239 Increase kernel security by ensuring that normal kernel accesses
1240 are unable to access userspace addresses. This can help prevent
1241 use-after-free bugs becoming an exploitable privilege escalation
1242 by ensuring that magic values (such as LIST_POISON) will always
1243 fault when dereferenced.
1245 CPUs with low-vector mappings use a best-efforts implementation.
1246 Their lower 1MB needs to remain accessible for the vectors, but
1247 the remainder of userspace will become appropriately inaccessible.
1249 config HW_PERF_EVENTS
1253 config ARM_MODULE_PLTS
1254 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1256 select KASAN_VMALLOC if KASAN
1259 Allocate PLTs when loading modules so that jumps and calls whose
1260 targets are too far away for their relative offsets to be encoded
1261 in the instructions themselves can be bounced via veneers in the
1262 module's PLT. This allows modules to be allocated in the generic
1263 vmalloc area after the dedicated module memory area has been
1264 exhausted. The modules will use slightly more memory, but after
1265 rounding up to page size, the actual memory footprint is usually
1268 Disabling this is usually safe for small single-platform
1269 configurations. If unsure, say y.
1271 config ARCH_FORCE_MAX_ORDER
1272 int "Order of maximal physically contiguous allocations"
1273 default "11" if SOC_AM33XX
1274 default "8" if SA1111
1277 The kernel page allocator limits the size of maximal physically
1278 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1279 defines the maximal power of two of number of pages that can be
1280 allocated as a single contiguous block. This option allows
1281 overriding the default setting when ability to allocate very
1282 large blocks of physically contiguous memory is required.
1284 Don't change if unsure.
1286 config ALIGNMENT_TRAP
1287 def_bool CPU_CP15_MMU
1288 select HAVE_PROC_CPU if PROC_FS
1290 ARM processors cannot fetch/store information which is not
1291 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1292 address divisible by 4. On 32-bit ARM processors, these non-aligned
1293 fetch/store instructions will be emulated in software if you say
1294 here, which has a severe performance impact. This is necessary for
1295 correct operation of some network protocols. With an IP-only
1296 configuration it is safe to say N, otherwise say Y.
1298 config UACCESS_WITH_MEMCPY
1299 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1301 default y if CPU_FEROCEON
1303 Implement faster copy_to_user and clear_user methods for CPU
1304 cores where a 8-word STM instruction give significantly higher
1305 memory write throughput than a sequence of individual 32bit stores.
1307 A possible side effect is a slight increase in scheduling latency
1308 between threads sharing the same address space if they invoke
1309 such copy operations with large buffers.
1311 However, if the CPU data cache is using a write-allocate mode,
1312 this option is unlikely to provide any performance gain.
1315 bool "Enable paravirtualization code"
1317 This changes the kernel so it can modify itself when it is run
1318 under a hypervisor, potentially improving performance significantly
1319 over full virtualization.
1321 config PARAVIRT_TIME_ACCOUNTING
1322 bool "Paravirtual steal time accounting"
1325 Select this option to enable fine granularity task steal time
1326 accounting. Time spent executing other tasks in parallel with
1327 the current vCPU is discounted from the vCPU power. To account for
1328 that, there can be a small performance impact.
1330 If in doubt, say N here.
1337 bool "Xen guest support on ARM"
1338 depends on ARM && AEABI && OF
1339 depends on CPU_V7 && !CPU_V6
1340 depends on !GENERIC_ATOMIC64
1342 select ARCH_DMA_ADDR_T_64BIT
1348 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1350 config CC_HAVE_STACKPROTECTOR_TLS
1351 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1353 config STACKPROTECTOR_PER_TASK
1354 bool "Use a unique stack canary value for each task"
1355 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1356 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1357 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1360 Due to the fact that GCC uses an ordinary symbol reference from
1361 which to load the value of the stack canary, this value can only
1362 change at reboot time on SMP systems, and all tasks running in the
1363 kernel's address space are forced to use the same canary value for
1364 the entire duration that the system is up.
1366 Enable this option to switch to a different method that uses a
1367 different canary value for each task.
1374 bool "Flattened Device Tree support"
1378 Include support for flattened device tree machine descriptions.
1380 config ARCH_WANT_FLAT_DTB_INSTALL
1384 bool "Support for the traditional ATAGS boot data passing"
1387 This is the traditional way of passing data to the kernel at boot
1388 time. If you are solely relying on the flattened device tree (or
1389 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1390 to remove ATAGS support from your kernel binary.
1392 config DEPRECATED_PARAM_STRUCT
1393 bool "Provide old way to pass kernel parameters"
1396 This was deprecated in 2001 and announced to live on for 5 years.
1397 Some old boot loaders still use this way.
1399 # Compressed boot loader in ROM. Yes, we really want to ask about
1400 # TEXT and BSS so we preserve their values in the config files.
1401 config ZBOOT_ROM_TEXT
1402 hex "Compressed ROM boot loader base address"
1405 The physical address at which the ROM-able zImage is to be
1406 placed in the target. Platforms which normally make use of
1407 ROM-able zImage formats normally set this to a suitable
1408 value in their defconfig file.
1410 If ZBOOT_ROM is not enabled, this has no effect.
1412 config ZBOOT_ROM_BSS
1413 hex "Compressed ROM boot loader BSS address"
1416 The base address of an area of read/write memory in the target
1417 for the ROM-able zImage which must be available while the
1418 decompressor is running. It must be large enough to hold the
1419 entire decompressed kernel plus an additional 128 KiB.
1420 Platforms which normally make use of ROM-able zImage formats
1421 normally set this to a suitable value in their defconfig file.
1423 If ZBOOT_ROM is not enabled, this has no effect.
1426 bool "Compressed boot loader in ROM/flash"
1427 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1428 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1430 Say Y here if you intend to execute your compressed kernel image
1431 (zImage) directly from ROM or flash. If unsure, say N.
1433 config ARM_APPENDED_DTB
1434 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1437 With this option, the boot code will look for a device tree binary
1438 (DTB) appended to zImage
1439 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1441 This is meant as a backward compatibility convenience for those
1442 systems with a bootloader that can't be upgraded to accommodate
1443 the documented boot protocol using a device tree.
1445 Beware that there is very little in terms of protection against
1446 this option being confused by leftover garbage in memory that might
1447 look like a DTB header after a reboot if no actual DTB is appended
1448 to zImage. Do not leave this option active in a production kernel
1449 if you don't intend to always append a DTB. Proper passing of the
1450 location into r2 of a bootloader provided DTB is always preferable
1453 config ARM_ATAG_DTB_COMPAT
1454 bool "Supplement the appended DTB with traditional ATAG information"
1455 depends on ARM_APPENDED_DTB
1457 Some old bootloaders can't be updated to a DTB capable one, yet
1458 they provide ATAGs with memory configuration, the ramdisk address,
1459 the kernel cmdline string, etc. Such information is dynamically
1460 provided by the bootloader and can't always be stored in a static
1461 DTB. To allow a device tree enabled kernel to be used with such
1462 bootloaders, this option allows zImage to extract the information
1463 from the ATAG list and store it at run time into the appended DTB.
1466 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1467 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1469 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1470 bool "Use bootloader kernel arguments if available"
1472 Uses the command-line options passed by the boot loader instead of
1473 the device tree bootargs property. If the boot loader doesn't provide
1474 any, the device tree bootargs property will be used.
1476 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1477 bool "Extend with bootloader kernel arguments"
1479 The command-line arguments provided by the boot loader will be
1480 appended to the the device tree bootargs property.
1485 string "Default kernel command string"
1488 On some architectures (e.g. CATS), there is currently no way
1489 for the boot loader to pass arguments to the kernel. For these
1490 architectures, you should supply some command-line options at build
1491 time by entering them here. As a minimum, you should specify the
1492 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1495 prompt "Kernel command line type" if CMDLINE != ""
1496 default CMDLINE_FROM_BOOTLOADER
1498 config CMDLINE_FROM_BOOTLOADER
1499 bool "Use bootloader kernel arguments if available"
1501 Uses the command-line options passed by the boot loader. If
1502 the boot loader doesn't provide any, the default kernel command
1503 string provided in CMDLINE will be used.
1505 config CMDLINE_EXTEND
1506 bool "Extend bootloader kernel arguments"
1508 The command-line arguments provided by the boot loader will be
1509 appended to the default kernel command string.
1511 config CMDLINE_FORCE
1512 bool "Always use the default kernel command string"
1514 Always use the default kernel command string, even if the boot
1515 loader passes other arguments to the kernel.
1516 This is useful if you cannot or don't want to change the
1517 command-line options your boot loader passes to the kernel.
1521 bool "Kernel Execute-In-Place from ROM"
1522 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1523 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1525 Execute-In-Place allows the kernel to run from non-volatile storage
1526 directly addressable by the CPU, such as NOR flash. This saves RAM
1527 space since the text section of the kernel is not loaded from flash
1528 to RAM. Read-write sections, such as the data section and stack,
1529 are still copied to RAM. The XIP kernel is not compressed since
1530 it has to run directly from flash, so it will take more space to
1531 store it. The flash address used to link the kernel object files,
1532 and for storing it, is configuration dependent. Therefore, if you
1533 say Y here, you must know the proper physical address where to
1534 store the kernel image depending on your own flash memory usage.
1536 Also note that the make target becomes "make xipImage" rather than
1537 "make zImage" or "make Image". The final kernel binary to put in
1538 ROM memory will be arch/arm/boot/xipImage.
1542 config XIP_PHYS_ADDR
1543 hex "XIP Kernel Physical Location"
1544 depends on XIP_KERNEL
1545 default "0x00080000"
1547 This is the physical address in your flash memory the kernel will
1548 be linked for and stored to. This address is dependent on your
1551 config XIP_DEFLATED_DATA
1552 bool "Store kernel .data section compressed in ROM"
1553 depends on XIP_KERNEL
1556 Before the kernel is actually executed, its .data section has to be
1557 copied to RAM from ROM. This option allows for storing that data
1558 in compressed form and decompressed to RAM rather than merely being
1559 copied, saving some precious ROM space. A possible drawback is a
1560 slightly longer boot delay.
1562 config ARCH_SUPPORTS_KEXEC
1563 def_bool (!SMP || PM_SLEEP_SMP) && MMU
1566 bool "Export atags in procfs"
1567 depends on ATAGS && KEXEC
1570 Should the atags used to boot the kernel be exported in an "atags"
1571 file in procfs. Useful with kexec.
1573 config ARCH_SUPPORTS_CRASH_DUMP
1576 config AUTO_ZRELADDR
1577 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1578 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1580 ZRELADDR is the physical address where the decompressed kernel
1581 image will be placed. If AUTO_ZRELADDR is selected, the address
1582 will be determined at run-time, either by masking the current IP
1583 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1584 This assumes the zImage being placed in the first 128MB from
1591 bool "UEFI runtime support"
1592 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1594 select EFI_PARAMS_FROM_FDT
1596 select EFI_GENERIC_STUB
1597 select EFI_RUNTIME_WRAPPERS
1599 This option provides support for runtime services provided
1600 by UEFI firmware (such as non-volatile variables, realtime
1601 clock, and platform reset). A UEFI stub is also provided to
1602 allow the kernel to be booted as an EFI application. This
1603 is only useful for kernels that may run on systems that have
1607 bool "Enable support for SMBIOS (DMI) tables"
1611 This enables SMBIOS/DMI feature for systems.
1613 This option is only useful on systems that have UEFI firmware.
1614 However, even with this option, the resultant kernel should
1615 continue to boot on existing non-UEFI platforms.
1617 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1618 i.e., the the practice of identifying the platform via DMI to
1619 decide whether certain workarounds for buggy hardware and/or
1620 firmware need to be enabled. This would require the DMI subsystem
1621 to be enabled much earlier than we do on ARM, which is non-trivial.
1625 menu "CPU Power Management"
1627 source "drivers/cpufreq/Kconfig"
1629 source "drivers/cpuidle/Kconfig"
1633 menu "Floating point emulation"
1635 comment "At least one emulation must be selected"
1638 bool "NWFPE math emulation"
1639 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1641 Say Y to include the NWFPE floating point emulator in the kernel.
1642 This is necessary to run most binaries. Linux does not currently
1643 support floating point hardware so you need to say Y here even if
1644 your machine has an FPA or floating point co-processor podule.
1646 You may say N here if you are going to load the Acorn FPEmulator
1647 early in the bootup.
1650 bool "Support extended precision"
1651 depends on FPE_NWFPE
1653 Say Y to include 80-bit support in the kernel floating-point
1654 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1655 Note that gcc does not generate 80-bit operations by default,
1656 so in most cases this option only enlarges the size of the
1657 floating point emulator without any good reason.
1659 You almost surely want to say N here.
1662 bool "FastFPE math emulation (EXPERIMENTAL)"
1663 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1665 Say Y here to include the FAST floating point emulator in the kernel.
1666 This is an experimental much faster emulator which now also has full
1667 precision for the mantissa. It does not support any exceptions.
1668 It is very simple, and approximately 3-6 times faster than NWFPE.
1670 It should be sufficient for most programs. It may be not suitable
1671 for scientific calculations, but you have to check this for yourself.
1672 If you do not feel you need a faster FP emulation you should better
1676 bool "VFP-format floating point maths"
1677 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1679 Say Y to include VFP support code in the kernel. This is needed
1680 if your hardware includes a VFP unit.
1682 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1683 release notes and additional status information.
1685 Say N if your target does not have VFP hardware.
1693 bool "Advanced SIMD (NEON) Extension support"
1694 depends on VFPv3 && CPU_V7
1696 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1699 config KERNEL_MODE_NEON
1700 bool "Support for NEON in kernel mode"
1701 depends on NEON && AEABI
1703 Say Y to include support for NEON in kernel mode.
1707 menu "Power management options"
1709 source "kernel/power/Kconfig"
1711 config ARCH_SUSPEND_POSSIBLE
1712 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1713 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1716 config ARM_CPU_SUSPEND
1717 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1718 depends on ARCH_SUSPEND_POSSIBLE
1720 config ARCH_HIBERNATION_POSSIBLE
1723 default y if ARCH_SUSPEND_POSSIBLE
1727 source "arch/arm/Kconfig.assembler"