arch/arc/include/asm/atomic.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef _ASM_ARC_ATOMIC_H
  10 #define _ASM_ARC_ATOMIC_H
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <linux/types.h>
  15 #include <linux/compiler.h>
  16 #include <asm/cmpxchg.h>
  17 #include <asm/barrier.h>
  18 #include <asm/smp.h>
  19
  20 #define ATOMIC_INIT(i)  { (i) }
  21
  22 #ifndef CONFIG_ARC_PLAT_EZNPS
  23
  24 #define atomic_read(v)  READ_ONCE((v)->counter)
  25
  26 #ifdef CONFIG_ARC_HAS_LLSC
  27
  28 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
  29
  30 #define ATOMIC_OP(op, c_op, asm_op)                                     \
  31 static inline void atomic_##op(int i, atomic_t *v)                      \
  32 {                                                                       \
  33         unsigned int val;                                               \
  34                                                                         \
  35         __asm__ __volatile__(                                           \
  36         "1:     llock   %[val], [%[ctr]]                \n"             \
  37         "       " #asm_op " %[val], %[val], %[i]        \n"             \
  38         "       scond   %[val], [%[ctr]]                \n"             \
  39         "       bnz     1b                              \n"             \
  40         : [val] "=&r"   (val) /* Early clobber to prevent reg reuse */  \
  41         : [ctr] "r"     (&v->counter), /* Not "m": llock only supports reg direct addr mode */  \
  42           [i]   "ir"    (i)                                             \
  43         : "cc");                                                        \
  44 }                                                                       \
  45
  46 #define ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
  47 static inline int atomic_##op##_return(int i, atomic_t *v)              \
  48 {                                                                       \
  49         unsigned int val;                                               \
  50                                                                         \
  51         /*                                                              \
  52          * Explicit full memory barrier needed before/after as          \
  53          * LLOCK/SCOND thmeselves don't provide any such semantics      \
  54          */                                                             \
  55         smp_mb();                                                       \
  56                                                                         \
  57         __asm__ __volatile__(                                           \
  58         "1:     llock   %[val], [%[ctr]]                \n"             \
  59         "       " #asm_op " %[val], %[val], %[i]        \n"             \
  60         "       scond   %[val], [%[ctr]]                \n"             \
  61         "       bnz     1b                              \n"             \
  62         : [val] "=&r"   (val)                                           \
  63         : [ctr] "r"     (&v->counter),                                  \
  64           [i]   "ir"    (i)                                             \
  65         : "cc");                                                        \
  66                                                                         \
  67         smp_mb();                                                       \
  68                                                                         \
  69         return val;                                                     \
  70 }
  71
  72 #define ATOMIC_FETCH_OP(op, c_op, asm_op)                               \
  73 static inline int atomic_fetch_##op(int i, atomic_t *v)                 \
  74 {                                                                       \
  75         unsigned int val, orig;                                         \
  76                                                                         \
  77         /*                                                              \
  78          * Explicit full memory barrier needed before/after as          \
  79          * LLOCK/SCOND thmeselves don't provide any such semantics      \
  80          */                                                             \
  81         smp_mb();                                                       \
  82                                                                         \
  83         __asm__ __volatile__(                                           \
  84         "1:     llock   %[orig], [%[ctr]]               \n"             \
  85         "       " #asm_op " %[val], %[orig], %[i]       \n"             \
  86         "       scond   %[val], [%[ctr]]                \n"             \
  87         "                                               \n"             \
  88         : [val] "=&r"   (val),                                          \
  89           [orig] "=&r" (orig)                                           \
  90         : [ctr] "r"     (&v->counter),                                  \
  91           [i]   "ir"    (i)                                             \
  92         : "cc");                                                        \
  93                                                                         \
  94         smp_mb();                                                       \
  95                                                                         \
  96         return orig;                                                    \
  97 }
  98
  99 #else   /* !CONFIG_ARC_HAS_LLSC */
 100
 101 #ifndef CONFIG_SMP
 102
 103  /* violating atomic_xxx API locking protocol in UP for optimization sake */
 104 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
 105
 106 #else
 107
 108 static inline void atomic_set(atomic_t *v, int i)
 109 {
 110         /*
 111          * Independent of hardware support, all of the atomic_xxx() APIs need
 112          * to follow the same locking rules to make sure that a "hardware"
 113          * atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
 114          * sequence
 115          *
 116          * Thus atomic_set() despite being 1 insn (and seemingly atomic)
 117          * requires the locking.
 118          */
 119         unsigned long flags;
 120
 121         atomic_ops_lock(flags);
 122         WRITE_ONCE(v->counter, i);
 123         atomic_ops_unlock(flags);
 124 }
 125
 126 #define atomic_set_release(v, i)        atomic_set((v), (i))
 127
 128 #endif
 129
 130 /*
 131  * Non hardware assisted Atomic-R-M-W
 132  * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
 133  */
 134
 135 #define ATOMIC_OP(op, c_op, asm_op)                                     \
 136 static inline void atomic_##op(int i, atomic_t *v)                      \
 137 {                                                                       \
 138         unsigned long flags;                                            \
 139                                                                         \
 140         atomic_ops_lock(flags);                                         \
 141         v->counter c_op i;                                              \
 142         atomic_ops_unlock(flags);                                       \
 143 }
 144
 145 #define ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
 146 static inline int atomic_##op##_return(int i, atomic_t *v)              \
 147 {                                                                       \
 148         unsigned long flags;                                            \
 149         unsigned long temp;                                             \
 150                                                                         \
 151         /*                                                              \
 152          * spin lock/unlock provides the needed smp_mb() before/after   \
 153          */                                                             \
 154         atomic_ops_lock(flags);                                         \
 155         temp = v->counter;                                              \
 156         temp c_op i;                                                    \
 157         v->counter = temp;                                              \
 158         atomic_ops_unlock(flags);                                       \
 159                                                                         \
 160         return temp;                                                    \
 161 }
 162
 163 #define ATOMIC_FETCH_OP(op, c_op, asm_op)                               \
 164 static inline int atomic_fetch_##op(int i, atomic_t *v)                 \
 165 {                                                                       \
 166         unsigned long flags;                                            \
 167         unsigned long orig;                                             \
 168                                                                         \
 169         /*                                                              \
 170          * spin lock/unlock provides the needed smp_mb() before/after   \
 171          */                                                             \
 172         atomic_ops_lock(flags);                                         \
 173         orig = v->counter;                                              \
 174         v->counter c_op i;                                              \
 175         atomic_ops_unlock(flags);                                       \
 176                                                                         \
 177         return orig;                                                    \
 178 }
 179
 180 #endif /* !CONFIG_ARC_HAS_LLSC */
 181
 182 #define ATOMIC_OPS(op, c_op, asm_op)                                    \
 183         ATOMIC_OP(op, c_op, asm_op)                                     \
 184         ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
 185         ATOMIC_FETCH_OP(op, c_op, asm_op)
 186
 187 ATOMIC_OPS(add, +=, add)
 188 ATOMIC_OPS(sub, -=, sub)
 189
 190 #define atomic_andnot atomic_andnot
 191
 192 #undef ATOMIC_OPS
 193 #define ATOMIC_OPS(op, c_op, asm_op)                                    \
 194         ATOMIC_OP(op, c_op, asm_op)                                     \
 195         ATOMIC_FETCH_OP(op, c_op, asm_op)
 196
 197 ATOMIC_OPS(and, &=, and)
 198 ATOMIC_OPS(andnot, &= ~, bic)
 199 ATOMIC_OPS(or, |=, or)
 200 ATOMIC_OPS(xor, ^=, xor)
 201
 202 #else /* CONFIG_ARC_PLAT_EZNPS */
 203
 204 static inline int atomic_read(const atomic_t *v)
 205 {
 206         int temp;
 207
 208         __asm__ __volatile__(
 209         "       ld.di %0, [%1]"
 210         : "=r"(temp)
 211         : "r"(&v->counter)
 212         : "memory");
 213         return temp;
 214 }
 215
 216 static inline void atomic_set(atomic_t *v, int i)
 217 {
 218         __asm__ __volatile__(
 219         "       st.di %0,[%1]"
 220         :
 221         : "r"(i), "r"(&v->counter)
 222         : "memory");
 223 }
 224
 225 #define ATOMIC_OP(op, c_op, asm_op)                                     \
 226 static inline void atomic_##op(int i, atomic_t *v)                      \
 227 {                                                                       \
 228         __asm__ __volatile__(                                           \
 229         "       mov r2, %0\n"                                           \
 230         "       mov r3, %1\n"                                           \
 231         "       .word %2\n"                                             \
 232         :                                                               \
 233         : "r"(i), "r"(&v->counter), "i"(asm_op)                         \
 234         : "r2", "r3", "memory");                                        \
 235 }                                                                       \
 236
 237 #define ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
 238 static inline int atomic_##op##_return(int i, atomic_t *v)              \
 239 {                                                                       \
 240         unsigned int temp = i;                                          \
 241                                                                         \
 242         /* Explicit full memory barrier needed before/after */          \
 243         smp_mb();                                                       \
 244                                                                         \
 245         __asm__ __volatile__(                                           \
 246         "       mov r2, %0\n"                                           \
 247         "       mov r3, %1\n"                                           \
 248         "       .word %2\n"                                             \
 249         "       mov %0, r2"                                             \
 250         : "+r"(temp)                                                    \
 251         : "r"(&v->counter), "i"(asm_op)                                 \
 252         : "r2", "r3", "memory");                                        \
 253                                                                         \
 254         smp_mb();                                                       \
 255                                                                         \
 256         temp c_op i;                                                    \
 257                                                                         \
 258         return temp;                                                    \
 259 }
 260
 261 #define ATOMIC_FETCH_OP(op, c_op, asm_op)                               \
 262 static inline int atomic_fetch_##op(int i, atomic_t *v)                 \
 263 {                                                                       \
 264         unsigned int temp = i;                                          \
 265                                                                         \
 266         /* Explicit full memory barrier needed before/after */          \
 267         smp_mb();                                                       \
 268                                                                         \
 269         __asm__ __volatile__(                                           \
 270         "       mov r2, %0\n"                                           \
 271         "       mov r3, %1\n"                                           \
 272         "       .word %2\n"                                             \
 273         "       mov %0, r2"                                             \
 274         : "+r"(temp)                                                    \
 275         : "r"(&v->counter), "i"(asm_op)                                 \
 276         : "r2", "r3", "memory");                                        \
 277                                                                         \
 278         smp_mb();                                                       \
 279                                                                         \
 280         return temp;                                                    \
 281 }
 282
 283 #define ATOMIC_OPS(op, c_op, asm_op)                                    \
 284         ATOMIC_OP(op, c_op, asm_op)                                     \
 285         ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
 286         ATOMIC_FETCH_OP(op, c_op, asm_op)
 287
 288 ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
 289 #define atomic_sub(i, v) atomic_add(-(i), (v))
 290 #define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
 291 #define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v))
 292
 293 #undef ATOMIC_OPS
 294 #define ATOMIC_OPS(op, c_op, asm_op)                                    \
 295         ATOMIC_OP(op, c_op, asm_op)                                     \
 296         ATOMIC_FETCH_OP(op, c_op, asm_op)
 297
 298 ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
 299 #define atomic_andnot(mask, v) atomic_and(~(mask), (v))
 300 #define atomic_fetch_andnot(mask, v) atomic_fetch_and(~(mask), (v))
 301 ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
 302 ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
 303
 304 #endif /* CONFIG_ARC_PLAT_EZNPS */
 305
 306 #undef ATOMIC_OPS
 307 #undef ATOMIC_FETCH_OP
 308 #undef ATOMIC_OP_RETURN
 309 #undef ATOMIC_OP
 310
 311 #define atomic_inc(v)                   atomic_add(1, v)
 312 #define atomic_dec(v)                   atomic_sub(1, v)
 313
 314 #define atomic_inc_return(v)            atomic_add_return(1, (v))
 315 #define atomic_dec_return(v)            atomic_sub_return(1, (v))
 316
 317 #ifdef CONFIG_GENERIC_ATOMIC64
 318
 319 #include <asm-generic/atomic64.h>
 320
 321 #else   /* Kconfig ensures this is only enabled with needed h/w assist */
 322
 323 /*
 324  * ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
 325  *  - The address HAS to be 64-bit aligned
 326  *  - There are 2 semantics involved here:
 327  *    = exclusive implies no interim update between load/store to same addr
 328  *    = both words are observed/updated together: this is guaranteed even
 329  *      for regular 64-bit load (LDD) / store (STD). Thus atomic64_set()
 330  *      is NOT required to use LLOCKD+SCONDD, STD suffices
 331  */
 332
 333 typedef struct {
 334         aligned_u64 counter;
 335 } atomic64_t;
 336
 337 #define ATOMIC64_INIT(a) { (a) }
 338
 339 static inline long long atomic64_read(const atomic64_t *v)
 340 {
 341         unsigned long long val;
 342
 343         __asm__ __volatile__(
 344         "       ldd   %0, [%1]  \n"
 345         : "=r"(val)
 346         : "r"(&v->counter));
 347
 348         return val;
 349 }
 350
 351 static inline void atomic64_set(atomic64_t *v, long long a)
 352 {
 353         /*
 354          * This could have been a simple assignment in "C" but would need
 355          * explicit volatile. Otherwise gcc optimizers could elide the store
 356          * which borked atomic64 self-test
 357          * In the inline asm version, memory clobber needed for exact same
 358          * reason, to tell gcc about the store.
 359          *
 360          * This however is not needed for sibling atomic64_add() etc since both
 361          * load/store are explicitly done in inline asm. As long as API is used
 362          * for each access, gcc has no way to optimize away any load/store
 363          */
 364         __asm__ __volatile__(
 365         "       std   %0, [%1]  \n"
 366         :
 367         : "r"(a), "r"(&v->counter)
 368         : "memory");
 369 }
 370
 371 #define ATOMIC64_OP(op, op1, op2)                                       \
 372 static inline void atomic64_##op(long long a, atomic64_t *v)            \
 373 {                                                                       \
 374         unsigned long long val;                                         \
 375                                                                         \
 376         __asm__ __volatile__(                                           \
 377         "1:                             \n"                             \
 378         "       llockd  %0, [%1]        \n"                             \
 379         "       " #op1 " %L0, %L0, %L2  \n"                             \
 380         "       " #op2 " %H0, %H0, %H2  \n"                             \
 381         "       scondd   %0, [%1]       \n"                             \
 382         "       bnz     1b              \n"                             \
 383         : "=&r"(val)                                                    \
 384         : "r"(&v->counter), "ir"(a)                                     \
 385         : "cc");                                                \
 386 }                                                                       \
 387
 388 #define ATOMIC64_OP_RETURN(op, op1, op2)                                \
 389 static inline long long atomic64_##op##_return(long long a, atomic64_t *v)      \
 390 {                                                                       \
 391         unsigned long long val;                                         \
 392                                                                         \
 393         smp_mb();                                                       \
 394                                                                         \
 395         __asm__ __volatile__(                                           \
 396         "1:                             \n"                             \
 397         "       llockd   %0, [%1]       \n"                             \
 398         "       " #op1 " %L0, %L0, %L2  \n"                             \
 399         "       " #op2 " %H0, %H0, %H2  \n"                             \
 400         "       scondd   %0, [%1]       \n"                             \
 401         "       bnz     1b              \n"                             \
 402         : [val] "=&r"(val)                                              \
 403         : "r"(&v->counter), "ir"(a)                                     \
 404         : "cc");        /* memory clobber comes from smp_mb() */        \
 405                                                                         \
 406         smp_mb();                                                       \
 407                                                                         \
 408         return val;                                                     \
 409 }
 410
 411 #define ATOMIC64_FETCH_OP(op, op1, op2)                                 \
 412 static inline long long atomic64_fetch_##op(long long a, atomic64_t *v) \
 413 {                                                                       \
 414         unsigned long long val, orig;                                   \
 415                                                                         \
 416         smp_mb();                                                       \
 417                                                                         \
 418         __asm__ __volatile__(                                           \
 419         "1:                             \n"                             \
 420         "       llockd   %0, [%2]       \n"                             \
 421         "       " #op1 " %L1, %L0, %L3  \n"                             \
 422         "       " #op2 " %H1, %H0, %H3  \n"                             \
 423         "       scondd   %1, [%2]       \n"                             \
 424         "       bnz     1b              \n"                             \
 425         : "=&r"(orig), "=&r"(val)                                       \
 426         : "r"(&v->counter), "ir"(a)                                     \
 427         : "cc");        /* memory clobber comes from smp_mb() */        \
 428                                                                         \
 429         smp_mb();                                                       \
 430                                                                         \
 431         return orig;                                                    \
 432 }
 433
 434 #define ATOMIC64_OPS(op, op1, op2)                                      \
 435         ATOMIC64_OP(op, op1, op2)                                       \
 436         ATOMIC64_OP_RETURN(op, op1, op2)                                \
 437         ATOMIC64_FETCH_OP(op, op1, op2)
 438
 439 #define atomic64_andnot atomic64_andnot
 440
 441 ATOMIC64_OPS(add, add.f, adc)
 442 ATOMIC64_OPS(sub, sub.f, sbc)
 443 ATOMIC64_OPS(and, and, and)
 444 ATOMIC64_OPS(andnot, bic, bic)
 445 ATOMIC64_OPS(or, or, or)
 446 ATOMIC64_OPS(xor, xor, xor)
 447
 448 #undef ATOMIC64_OPS
 449 #undef ATOMIC64_FETCH_OP
 450 #undef ATOMIC64_OP_RETURN
 451 #undef ATOMIC64_OP
 452
 453 static inline long long
 454 atomic64_cmpxchg(atomic64_t *ptr, long long expected, long long new)
 455 {
 456         long long prev;
 457
 458         smp_mb();
 459
 460         __asm__ __volatile__(
 461         "1:     llockd  %0, [%1]        \n"
 462         "       brne    %L0, %L2, 2f    \n"
 463         "       brne    %H0, %H2, 2f    \n"
 464         "       scondd  %3, [%1]        \n"
 465         "       bnz     1b              \n"
 466         "2:                             \n"
 467         : "=&r"(prev)
 468         : "r"(ptr), "ir"(expected), "r"(new)
 469         : "cc");        /* memory clobber comes from smp_mb() */
 470
 471         smp_mb();
 472
 473         return prev;
 474 }
 475
 476 static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
 477 {
 478         long long prev;
 479
 480         smp_mb();
 481
 482         __asm__ __volatile__(
 483         "1:     llockd  %0, [%1]        \n"
 484         "       scondd  %2, [%1]        \n"
 485         "       bnz     1b              \n"
 486         "2:                             \n"
 487         : "=&r"(prev)
 488         : "r"(ptr), "r"(new)
 489         : "cc");        /* memory clobber comes from smp_mb() */
 490
 491         smp_mb();
 492
 493         return prev;
 494 }
 495
 496 /**
 497  * atomic64_dec_if_positive - decrement by 1 if old value positive
 498  * @v: pointer of type atomic64_t
 499  *
 500  * The function returns the old value of *v minus 1, even if
 501  * the atomic variable, v, was not decremented.
 502  */
 503
 504 static inline long long atomic64_dec_if_positive(atomic64_t *v)
 505 {
 506         long long val;
 507
 508         smp_mb();
 509
 510         __asm__ __volatile__(
 511         "1:     llockd  %0, [%1]        \n"
 512         "       sub.f   %L0, %L0, 1     # w0 - 1, set C on borrow\n"
 513         "       sub.c   %H0, %H0, 1     # if C set, w1 - 1\n"
 514         "       brlt    %H0, 0, 2f      \n"
 515         "       scondd  %0, [%1]        \n"
 516         "       bnz     1b              \n"
 517         "2:                             \n"
 518         : "=&r"(val)
 519         : "r"(&v->counter)
 520         : "cc");        /* memory clobber comes from smp_mb() */
 521
 522         smp_mb();
 523
 524         return val;
 525 }
 526
 527 /**
 528  * atomic64_fetch_add_unless - add unless the number is a given value
 529  * @v: pointer of type atomic64_t
 530  * @a: the amount to add to v...
 531  * @u: ...unless v is equal to u.
 532  *
 533  * Atomically adds @a to @v, if it was not @u.
 534  * Returns the old value of @v
 535  */
 536 static inline long long atomic64_fetch_add_unless(atomic64_t *v, long long a,
 537                                                   long long u)
 538 {
 539         long long old, temp;
 540
 541         smp_mb();
 542
 543         __asm__ __volatile__(
 544         "1:     llockd  %0, [%2]        \n"
 545         "       brne    %L0, %L4, 2f    # continue to add since v != u \n"
 546         "       breq.d  %H0, %H4, 3f    # return since v == u \n"
 547         "2:                             \n"
 548         "       add.f   %L1, %L0, %L3   \n"
 549         "       adc     %H1, %H0, %H3   \n"
 550         "       scondd  %1, [%2]        \n"
 551         "       bnz     1b              \n"
 552         "3:                             \n"
 553         : "=&r"(old), "=&r" (temp)
 554         : "r"(&v->counter), "r"(a), "r"(u)
 555         : "cc");        /* memory clobber comes from smp_mb() */
 556
 557         smp_mb();
 558
 559         return old;
 560 }
 561 #define atomic64_fetch_add_unless atomic64_fetch_add_unless
 562
 563 #define atomic64_inc(v)                 atomic64_add(1LL, (v))
 564 #define atomic64_inc_return(v)          atomic64_add_return(1LL, (v))
 565 #define atomic64_dec(v)                 atomic64_sub(1LL, (v))
 566 #define atomic64_dec_return(v)          atomic64_sub_return(1LL, (v))
 567
 568 #endif  /* !CONFIG_GENERIC_ATOMIC64 */
 569
 570 #endif  /* !__ASSEMBLY__ */
 571
 572 #endif