arch/arc/boot/dts/hsdk.dts

   1 /*
   2  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device Tree for ARC HS Development Kit
  11  */
  12 /dts-v1/;
  13
  14 #include <dt-bindings/reset/snps,hsdk-reset.h>
  15
  16 / {
  17         model = "snps,hsdk";
  18         compatible = "snps,hsdk";
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen {
  24                 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
  25         };
  26
  27         aliases {
  28                 ethernet = &gmac;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "snps,archs38";
  38                         reg = <0>;
  39                         clocks = <&core_clk>;
  40                 };
  41
  42                 cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "snps,archs38";
  45                         reg = <1>;
  46                         clocks = <&core_clk>;
  47                 };
  48
  49                 cpu@2 {
  50                         device_type = "cpu";
  51                         compatible = "snps,archs38";
  52                         reg = <2>;
  53                         clocks = <&core_clk>;
  54                 };
  55
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "snps,archs38";
  59                         reg = <3>;
  60                         clocks = <&core_clk>;
  61                 };
  62         };
  63
  64         input_clk: input-clk {
  65                 #clock-cells = <0>;
  66                 compatible = "fixed-clock";
  67                 clock-frequency = <33333333>;
  68         };
  69
  70         cpu_intc: cpu-interrupt-controller {
  71                 compatible = "snps,archs-intc";
  72                 interrupt-controller;
  73                 #interrupt-cells = <1>;
  74         };
  75
  76         idu_intc: idu-interrupt-controller {
  77                 compatible = "snps,archs-idu-intc";
  78                 interrupt-controller;
  79                 #interrupt-cells = <1>;
  80                 interrupt-parent = <&cpu_intc>;
  81         };
  82
  83         arcpct: pct {
  84                 compatible = "snps,archs-pct";
  85         };
  86
  87         /* TIMER0 with interrupt for clockevent */
  88         timer {
  89                 compatible = "snps,arc-timer";
  90                 interrupts = <16>;
  91                 interrupt-parent = <&cpu_intc>;
  92                 clocks = <&core_clk>;
  93         };
  94
  95         /* 64-bit Global Free Running Counter */
  96         gfrc {
  97                 compatible = "snps,archs-timer-gfrc";
  98                 clocks = <&core_clk>;
  99         };
 100
 101         soc {
 102                 compatible = "simple-bus";
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 interrupt-parent = <&idu_intc>;
 106
 107                 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
 108
 109                 cgu_rst: reset-controller@8a0 {
 110                         compatible = "snps,hsdk-reset";
 111                         #reset-cells = <1>;
 112                         reg = <0x8a0 0x4>, <0xff0 0x4>;
 113                 };
 114
 115                 core_clk: core-clk@0 {
 116                         compatible = "snps,hsdk-core-pll-clock";
 117                         reg = <0x00 0x10>, <0x14b8 0x4>;
 118                         #clock-cells = <0>;
 119                         clocks = <&input_clk>;
 120
 121                         /*
 122                          * Set initial core pll output frequency to 1GHz.
 123                          * It will be applied at the core pll driver probing
 124                          * on early boot.
 125                          */
 126                         assigned-clocks = <&core_clk>;
 127                         assigned-clock-rates = <1000000000>;
 128                 };
 129
 130                 serial: serial@5000 {
 131                         compatible = "snps,dw-apb-uart";
 132                         reg = <0x5000 0x100>;
 133                         clock-frequency = <33330000>;
 134                         interrupts = <6>;
 135                         baud = <115200>;
 136                         reg-shift = <2>;
 137                         reg-io-width = <4>;
 138                 };
 139
 140                 gmacclk: gmacclk {
 141                         compatible = "fixed-clock";
 142                         clock-frequency = <400000000>;
 143                         #clock-cells = <0>;
 144                 };
 145
 146                 mmcclk_ciu: mmcclk-ciu {
 147                         compatible = "fixed-clock";
 148                         /*
 149                          * DW sdio controller has external ciu clock divider
 150                          * controlled via register in SDIO IP. Due to its
 151                          * unexpected default value (it should divide by 1
 152                          * but it divides by 8) SDIO IP uses wrong clock and
 153                          * works unstable (see STAR 9001204800)
 154                          * We switched to the minimum possible value of the
 155                          * divisor (div-by-2) in HSDK platform code.
 156                          * So add temporary fix and change clock frequency
 157                          * to 50000000 Hz until we fix dw sdio driver itself.
 158                          */
 159                         clock-frequency = <50000000>;
 160                         #clock-cells = <0>;
 161                 };
 162
 163                 mmcclk_biu: mmcclk-biu {
 164                         compatible = "fixed-clock";
 165                         clock-frequency = <400000000>;
 166                         #clock-cells = <0>;
 167                 };
 168
 169                 gpu_core_clk: gpu-core-clk {
 170                         compatible = "fixed-clock";
 171                         clock-frequency = <400000000>;
 172                         #clock-cells = <0>;
 173                 };
 174
 175                 gpu_dma_clk: gpu-dma-clk {
 176                         compatible = "fixed-clock";
 177                         clock-frequency = <400000000>;
 178                         #clock-cells = <0>;
 179                 };
 180
 181                 gpu_cfg_clk: gpu-cfg-clk {
 182                         compatible = "fixed-clock";
 183                         clock-frequency = <200000000>;
 184                         #clock-cells = <0>;
 185                 };
 186
 187                 dmac_core_clk: dmac-core-clk {
 188                         compatible = "fixed-clock";
 189                         clock-frequency = <400000000>;
 190                         #clock-cells = <0>;
 191                 };
 192
 193                 dmac_cfg_clk: dmac-gpu-cfg-clk {
 194                         compatible = "fixed-clock";
 195                         clock-frequency = <200000000>;
 196                         #clock-cells = <0>;
 197                 };
 198
 199                 gmac: ethernet@8000 {
 200                         #interrupt-cells = <1>;
 201                         compatible = "snps,dwmac";
 202                         reg = <0x8000 0x2000>;
 203                         interrupts = <10>;
 204                         interrupt-names = "macirq";
 205                         phy-mode = "rgmii";
 206                         snps,pbl = <32>;
 207                         snps,multicast-filter-bins = <256>;
 208                         clocks = <&gmacclk>;
 209                         clock-names = "stmmaceth";
 210                         phy-handle = <&phy0>;
 211                         resets = <&cgu_rst HSDK_ETH_RESET>;
 212                         reset-names = "stmmaceth";
 213                         mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
 214                         dma-coherent;
 215
 216                         tx-fifo-depth = <4096>;
 217                         rx-fifo-depth = <4096>;
 218
 219                         mdio {
 220                                 #address-cells = <1>;
 221                                 #size-cells = <0>;
 222                                 compatible = "snps,dwmac-mdio";
 223                                 phy0: ethernet-phy@0 {
 224                                         reg = <0>;
 225                                 };
 226                         };
 227                 };
 228
 229                 ohci@60000 {
 230                         compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
 231                         reg = <0x60000 0x100>;
 232                         interrupts = <15>;
 233                         resets = <&cgu_rst HSDK_USB_RESET>;
 234                         dma-coherent;
 235                 };
 236
 237                 ehci@40000 {
 238                         compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
 239                         reg = <0x40000 0x100>;
 240                         interrupts = <15>;
 241                         resets = <&cgu_rst HSDK_USB_RESET>;
 242                         dma-coherent;
 243                 };
 244
 245                 mmc@a000 {
 246                         compatible = "altr,socfpga-dw-mshc";
 247                         reg = <0xa000 0x400>;
 248                         num-slots = <1>;
 249                         fifo-depth = <16>;
 250                         card-detect-delay = <200>;
 251                         clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
 252                         clock-names = "biu", "ciu";
 253                         interrupts = <12>;
 254                         bus-width = <4>;
 255                         dma-coherent;
 256                 };
 257
 258                 creg_gpio: gpio@14b0 {
 259                         compatible = "snps,creg-gpio-hsdk";
 260                         reg = <0x14b0 0x4>;
 261                         gpio-controller;
 262                         #gpio-cells = <2>;
 263                         ngpios = <2>;
 264                 };
 265
 266                 gpio: gpio@3000 {
 267                         compatible = "snps,dw-apb-gpio";
 268                         reg = <0x3000 0x20>;
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271
 272                         gpio_port_a: gpio-controller@0 {
 273                                 compatible = "snps,dw-apb-gpio-port";
 274                                 gpio-controller;
 275                                 #gpio-cells = <2>;
 276                                 snps,nr-gpios = <24>;
 277                                 reg = <0>;
 278                         };
 279                 };
 280
 281                 gpu_3d: gpu@90000 {
 282                         compatible = "vivante,gc";
 283                         reg = <0x90000 0x4000>;
 284                         clocks = <&gpu_dma_clk>,
 285                                  <&gpu_cfg_clk>,
 286                                  <&gpu_core_clk>,
 287                                  <&gpu_core_clk>;
 288                         clock-names = "bus", "reg", "core", "shader";
 289                         interrupts = <28>;
 290                 };
 291
 292                 dmac: dmac@80000 {
 293                         compatible = "snps,axi-dma-1.01a";
 294                         reg = <0x80000 0x400>;
 295                         interrupts = <27>;
 296                         clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
 297                         clock-names = "core-clk", "cfgr-clk";
 298
 299                         dma-channels = <4>;
 300                         snps,dma-masters = <2>;
 301                         snps,data-width = <3>;
 302                         snps,block-size = <4096 4096 4096 4096>;
 303                         snps,priority = <0 1 2 3>;
 304                         snps,axi-max-burst-len = <16>;
 305                 };
 306         };
 307
 308         memory@80000000 {
 309                 #address-cells = <2>;
 310                 #size-cells = <2>;
 311                 device_type = "memory";
 312                 reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
 313                 /*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */
 314         };
 315 };