Documentation/devicetree/bindings/watchdog/cdns,wdt-r1p2.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Cadence watchdog timer controller
   8
   9 maintainers:
  10   - Neeli Srinivas <srinivas.neeli@amd.com>
  11
  12 description:
  13   The cadence watchdog timer is used to detect and recover from
  14   system malfunctions. This watchdog contains 24 bit counter and
  15   a programmable reset period. The timeout period varies from 1 ms
  16   to 30 seconds while using a 100Mhz clock.
  17
  18 allOf:
  19   - $ref: watchdog.yaml#
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - cdns,wdt-r1p2
  25
  26   reg:
  27     maxItems: 1
  28
  29   clocks:
  30     maxItems: 1
  31
  32   interrupts:
  33     maxItems: 1
  34
  35   reset-on-timeout:
  36     type: boolean
  37     description: |
  38       If this property exists, then a reset is done when watchdog
  39       times out.
  40
  41 required:
  42   - compatible
  43   - reg
  44   - clocks
  45   - interrupts
  46
  47 unevaluatedProperties: false
  48
  49 examples:
  50   - |
  51     #include <dt-bindings/interrupt-controller/arm-gic.h>
  52
  53     watchdog@f8005000 {
  54         compatible = "cdns,wdt-r1p2";
  55         reg = <0xf8005000 0x1000>;
  56         clocks = <&clkc 45>;
  57         interrupt-parent = <&intc>;
  58         interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;
  59         reset-on-timeout;
  60         timeout-sec = <10>;
  61     };
  62 ...