1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
13 Simple IO memory regions to be managed by the genalloc API.
15 Each child of the sram node specifies a region of reserved memory. Each
16 child node should use a 'reg' property to specify a specific range of
19 Following the generic-names recommended practice, node names should
20 reflect the purpose of the node. Unit address (@<address>) should be
25 pattern: "^sram(@.*)?"
31 - atmel,sama5d2-securam
32 - rockchip,rk3288-pmu-sram
40 A list of phandle and clock specifier pair that controls the single
52 Should translate from local addresses within the sram to bus addresses.
56 The flag indicating, that SRAM memory region has not to be remapped
57 as write combining. WC is used by default.
61 "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
64 Each child of the sram node specifies a region of reserved memory.
68 Should contain a vendor specific string in the form
69 <vendor>,[<device>-]<usage>
72 - allwinner,sun4i-a10-sram-a3-a4
73 - allwinner,sun4i-a10-sram-c1
74 - allwinner,sun4i-a10-sram-d
75 - allwinner,sun9i-a80-smp-sram
76 - allwinner,sun50i-a64-sram-c
77 - amlogic,meson8-ao-arc-sram
78 - amlogic,meson8b-ao-arc-sram
79 - amlogic,meson8-smp-sram
80 - amlogic,meson8b-smp-sram
81 - amlogic,meson-gxbb-scp-shmem
82 - amlogic,meson-axg-scp-shmem
86 - rockchip,rk3066-smp-sram
87 - samsung,exynos4210-sysram
88 - samsung,exynos4210-sysram-ns
89 - socionext,milbeaut-smp-sram
93 IO mem address range, relative to the SRAM range.
98 Indicates that the particular reserved SRAM area is addressable
99 and in use by another device or devices.
104 Indicates that the reserved SRAM area may be accessed outside
105 of the kernel, e.g. by bootloader or userspace.
110 Same as 'pool' above but with the additional constraint that code
111 will be run from the region and that the memory is maintained as
112 read-only, executable during code execution. NOTE: This region must
113 be page aligned on start and end in order to properly allow
114 manipulation of the page attributes.
119 The name for the reserved partition, if omitted, the label is taken
120 from the node name excluding the unit address.
125 additionalProperties: false
135 const: rockchip,rk3288-pmu-sram
143 additionalProperties: false
148 compatible = "mmio-sram";
149 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
151 #address-cells = <1>;
153 ranges = <0 0x5c000000 0x40000>;
160 reg = <0x1000 0x1000>;
164 exported-sram@20000 {
165 reg = <0x20000 0x20000>;
171 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
172 // of the secondary cores. Once the core gets powered up it executes the
173 // code that is residing at some specific location of the SYSRAM.
175 // Therefore reserved section sub-nodes have to be added to the mmio-sram
176 // declaration. These nodes are of two types depending upon secure or
177 // non-secure execution environment.
179 compatible = "mmio-sram";
180 reg = <0x02020000 0x54000>;
181 #address-cells = <1>;
183 ranges = <0 0x02020000 0x54000>;
186 compatible = "samsung,exynos4210-sysram";
191 compatible = "samsung,exynos4210-sysram-ns";
192 reg = <0x53000 0x1000>;
197 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
198 // Once the core gets powered up it executes the code that is residing at a
199 // specific location.
201 // Therefore a reserved section sub-node has to be added to the mmio-sram
204 compatible = "mmio-sram";
205 reg = <0xd9000000 0x20000>;
206 #address-cells = <1>;
208 ranges = <0 0xd9000000 0x20000>;
211 compatible = "amlogic,meson8b-smp-sram";
218 compatible = "mmio-sram";
219 reg = <0xe63c0000 0x1000>;
220 #address-cells = <1>;
222 ranges = <0 0xe63c0000 0x1000>;
225 compatible = "renesas,smp-sram";
232 compatible = "mmio-sram";
233 reg = <0x10080000 0x10000>;
234 #address-cells = <1>;
239 compatible = "rockchip,rk3066-smp-sram";
240 reg = <0x10080000 0x50>;
245 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
246 // resume from maskrom(the 1st level loader). This is a common use of
247 // the "pmu-sram" because it keeps power even in low power states
250 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
251 reg = <0xff720000 0x1000>;
255 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
256 // primary core (cpu0). Once the core gets powered up it checks if a magic
257 // value is set at a specific location. If it is then the BROM will jump
258 // to the software entry address, instead of executing a standard boot.
260 // Also there are no "secure-only" properties. The implementation should
261 // check if this SRAM is usable first.
263 // 256 KiB secure SRAM at 0x20000
264 compatible = "mmio-sram";
265 reg = <0x00020000 0x40000>;
266 #address-cells = <1>;
268 ranges = <0 0x00020000 0x40000>;
271 // This is checked by BROM to determine if
272 // cpu0 should jump to SMP entry vector
273 compatible = "allwinner,sun9i-a80-smp-sram";
280 compatible = "mmio-sram";
282 #address-cells = <1>;
284 ranges = <0 0x0 0x10000>;
287 compatible = "socionext,milbeaut-smp-sram";