1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC SPI controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 All the SPI controller nodes should be represented in the aliases node using
14 the following format 'spi{n}' where n is a unique number for the alias.
20 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
22 - samsung,s5pv210-spi # for S5PV210 and S5PC110
23 - samsung,exynos5433-spi
25 - const: samsung,exynos7-spi
52 The CS line is disconnected, therefore the device should not operate
53 based on CS signalling.
63 If the spi controller includes a internal clock mux to select the clock
64 source for the spi bus clock, this property can be used to indicate the
65 clock to be used for driving the spi bus clock. If not specified, the
66 clock number 0 is used as default.
67 $ref: /schemas/types.yaml#/definitions/uint32
83 - $ref: spi-controller.yaml#
88 const: samsung,exynos5433-spi
117 unevaluatedProperties: false
121 #include <dt-bindings/clock/exynos5433.h>
122 #include <dt-bindings/clock/samsung,s2mps11.h>
123 #include <dt-bindings/interrupt-controller/arm-gic.h>
124 #include <dt-bindings/gpio/gpio.h>
127 compatible = "samsung,exynos5433-spi";
128 reg = <0x14d30000 0x100>;
129 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
130 dmas = <&pdma0 11>, <&pdma0 10>;
131 dma-names = "tx", "rx";
132 #address-cells = <1>;
134 clocks = <&cmu_peric CLK_PCLK_SPI1>,
135 <&cmu_peric CLK_SCLK_SPI1>,
136 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
140 samsung,spi-src-clk = <0>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&spi1_bus>;
145 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
148 compatible = "wlf,wm5110";
150 spi-max-frequency = <20000000>;
151 interrupt-parent = <&gpa0>;
152 interrupts = <4 IRQ_TYPE_NONE>;
153 clocks = <&pmu_system_controller 0>,
154 <&s2mps13_osc S2MPS11_CLK_BT>;
155 clock-names = "mclk1", "mclk2";
159 interrupt-controller;
160 #interrupt-cells = <2>;
162 wlf,micd-detect-debounce = <300>;
163 wlf,micd-bias-start-time = <0x1>;
164 wlf,micd-rate = <0x7>;
165 wlf,micd-dbtime = <0x2>;
166 wlf,micd-force-micbias;
167 wlf,micd-configs = <0x0 1 0>;
168 wlf,hpdet-channel = <1>;
170 wlf,inmode = <2 0 2 0>;
172 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
173 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
176 AVDD-supply = <&ldo18_reg>;
177 DBVDD1-supply = <&ldo18_reg>;
178 CPVDD-supply = <&ldo18_reg>;
179 DBVDD2-supply = <&ldo18_reg>;
180 DBVDD3-supply = <&ldo18_reg>;
181 SPKVDDL-supply = <&ldo18_reg>;
182 SPKVDDR-supply = <&ldo18_reg>;
185 samsung,spi-feedback-delay = <0>;