1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19 instruction RAMs, some internal peripheral modules to facilitate industrial
20 communication, and an interrupt controller.
22 The programmable nature of the PRUs provide flexibility to implement custom
23 peripheral interfaces, fast real-time responses, or specialized data handling.
24 The common peripheral modules include the following,
25 - an Ethernet MII_RT module with two MII ports
26 - an MDIO port to control external Ethernet PHYs
27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
29 - an Enhanced Capture Module (eCAP)
30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31 - a 16550-compatible UART to support PROFIBUS
32 - Enhanced GPIO with async capture and serial support
34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
40 RAM, and specific register spaces for Control and Debug functionalities.
42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
43 nodes and are defined using a parent-child hierarchy depending on their
44 integration within the IP and the SoC. These nodes are described in the
50 Each PRU-ICSS instance is represented as its own node with the individual PRU
51 processor cores, the memories node, an INTC node and an MDIO node represented
52 as child nodes within this PRUSS node. This node shall be a child of the
53 corresponding interconnect bus nodes or target-module nodes.
55 See ../../mfd/syscon.yaml for generic SysCon binding details.
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
64 - ti,am3356-pruss # for AM335x SoC family
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67 - ti,am5728-pruss # for AM57xx SoC family
68 - ti,k2g-pruss # for 66AK2G SoC family
69 - ti,am654-icssg # for K3 AM65x SoC family
70 - ti,j721e-icssg # for K3 J721E SoC family
71 - ti,am642-icssg # for K3 AM64x SoC family
92 This property is as per sci-pm-domain.txt.
98 The various Data RAMs within a single PRU-ICSS unit are represented as a
99 single node with the name 'memories'.
105 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
107 - description: Address and size of the Data RAM0.
108 - description: Address and size of the Data RAM1.
110 Address and size of the Shared Data RAM. Note that on AM437x one
111 of two PRUSS units don't contain Shared RAM, while the second one
125 additionalProperties: false
129 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
136 - const: ti,pruss-cfg
162 coreclk-mux@[a-f0-9]+$:
164 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
165 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
166 ICSSG_ICLK. This node models this clock mux and should have the
177 - description: ICSSG_CORE Clock
178 - description: ICSSG_ICLK Clock
183 assigned-clock-parents:
186 Standard assigned-clocks-parents definition used for selecting
187 mux parent (one of the mux input).
195 additionalProperties: false
197 iepclk-mux@[a-f0-9]+$:
199 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
200 CORE_CLK (OCP_CLK in older SoCs). This node models this clock
201 mux and should have the name "iepclk-mux".
211 - description: ICSSG_IEP Clock
212 - description: Core Clock (OCP Clock in older SoCs)
217 assigned-clock-parents:
220 Standard assigned-clocks-parents definition used for selecting
221 mux parent (one of the mux input).
229 additionalProperties: false
231 additionalProperties: false
235 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
236 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
237 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs).
238 IEP is used for creating PTP clocks and generating PPS signals.
244 Real-Time Ethernet to support multiple industrial communication protocols.
245 MII-RT sub-module represented as a SysCon.
252 - const: ti,pruss-mii
258 additionalProperties: false
262 The Real-time Media Independent Interface to support multiple industrial
263 communication protocols (G stands for Gigabit). MII-G-RT sub-module
264 represented as a SysCon.
271 - const: ti,pruss-mii-g
277 additionalProperties: false
279 interrupt-controller@[a-f0-9]+$:
281 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
282 that is common to all the PRU cores. This should be represented as an
283 interrupt-controller node.
284 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
289 MDIO Node. Each PRUSS has an MDIO module that can be used to control
290 external PHYs. The MDIO module used within the PRU-ICSS is an instance of
291 the MDIO Controller used in TI Davinci SoCs.
292 $ref: /schemas/net/ti,davinci-mdio.yaml#
295 "^(pru|rtu|txpru)@[0-9a-f]+$":
297 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
298 device through a PRU child node each. Each node can optionally be rendered
299 inactive by using the standard DT string property, "status". The ICSSG IP
300 present on K3 SoCs have additional auxiliary PRU cores with slightly
301 different IP integration.
302 $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
310 additionalProperties: false
312 # Due to inability of correctly verifying sub-nodes with an @address through
313 # the "required" list, the required sub-nodes below are commented out for now.
317 # - interrupt-controller
347 /* Example 1 AM33xx PRU-ICSS */
349 compatible = "ti,am3356-pruss";
351 #address-cells = <1>;
355 pruss_mem: memories@0 {
359 reg-names = "dram0", "dram1", "shrdram2";
362 pruss_cfg: cfg@26000 {
363 compatible = "ti,pruss-cfg", "syscon";
364 #address-cells = <1>;
366 reg = <0x26000 0x2000>;
367 ranges = <0x00 0x26000 0x2000>;
370 #address-cells = <1>;
373 pruss_iepclk_mux: iepclk-mux@30 {
376 clocks = <&l3_gclk>, /* icss_iep */
377 <&pruss_ocp_gclk>; /* icss_ocp */
382 pruss_mii_rt: mii-rt@32000 {
383 compatible = "ti,pruss-mii", "syscon";
384 reg = <0x32000 0x58>;
387 pruss_intc: interrupt-controller@20000 {
388 compatible = "ti,pruss-intc";
389 reg = <0x20000 0x2000>;
390 interrupt-controller;
391 #interrupt-cells = <3>;
392 interrupts = <20 21 22 23 24 25 26 27>;
393 interrupt-names = "host_intr0", "host_intr1",
394 "host_intr2", "host_intr3",
395 "host_intr4", "host_intr5",
396 "host_intr6", "host_intr7";
400 compatible = "ti,am3356-pru";
401 reg = <0x34000 0x2000>,
404 reg-names = "iram", "control", "debug";
405 firmware-name = "am335x-pru0-fw";
409 compatible = "ti,am3356-pru";
410 reg = <0x38000 0x2000>,
413 reg-names = "iram", "control", "debug";
414 firmware-name = "am335x-pru1-fw";
417 pruss_mdio: mdio@32400 {
418 compatible = "ti,davinci_mdio";
419 reg = <0x32400 0x90>;
420 clocks = <&dpll_core_m4_ck>;
422 bus_freq = <1000000>;
423 #address-cells = <1>;
430 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
431 #include <dt-bindings/interrupt-controller/arm-gic.h>
433 compatible = "ti,am4376-pruss1";
435 #address-cells = <1>;
439 pruss1_mem: memories@0 {
443 reg-names = "dram0", "dram1", "shrdram2";
446 pruss1_cfg: cfg@26000 {
447 compatible = "ti,pruss-cfg", "syscon";
448 #address-cells = <1>;
450 reg = <0x26000 0x2000>;
451 ranges = <0x00 0x26000 0x2000>;
454 #address-cells = <1>;
457 pruss1_iepclk_mux: iepclk-mux@30 {
460 clocks = <&sysclk_div>, /* icss_iep */
461 <&pruss_ocp_gclk>; /* icss_ocp */
466 pruss1_mii_rt: mii-rt@32000 {
467 compatible = "ti,pruss-mii", "syscon";
468 reg = <0x32000 0x58>;
471 pruss1_intc: interrupt-controller@20000 {
472 compatible = "ti,pruss-intc";
473 reg = <0x20000 0x2000>;
474 interrupt-controller;
475 #interrupt-cells = <3>;
476 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
483 interrupt-names = "host_intr0", "host_intr1",
484 "host_intr2", "host_intr3",
486 "host_intr6", "host_intr7";
487 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
491 compatible = "ti,am4376-pru";
492 reg = <0x34000 0x3000>,
495 reg-names = "iram", "control", "debug";
496 firmware-name = "am437x-pru1_0-fw";
500 compatible = "ti,am4376-pru";
501 reg = <0x38000 0x3000>,
504 reg-names = "iram", "control", "debug";
505 firmware-name = "am437x-pru1_1-fw";
508 pruss1_mdio: mdio@32400 {
509 compatible = "ti,davinci_mdio";
510 reg = <0x32400 0x90>;
511 clocks = <&dpll_core_m4_ck>;
513 bus_freq = <1000000>;
514 #address-cells = <1>;