Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V CPUs
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12   - Conor Dooley <conor@kernel.org>
  13
  14 description: |
  15   This document uses some terminology common to the RISC-V community
  16   that is not widely used, the definitions of which are listed here:
  17
  18   hart: A hardware execution context, which contains all the state
  19   mandated by the RISC-V ISA: a PC and some registers.  This
  20   terminology is designed to disambiguate software's view of execution
  21   contexts from any particular microarchitectural implementation
  22   strategy.  For example, an Intel laptop containing one socket with
  23   two cores, each of which has two hyperthreads, could be described as
  24   having four harts.
  25
  26 allOf:
  27   - $ref: /schemas/cpu.yaml#
  28   - $ref: extensions.yaml
  29
  30 properties:
  31   compatible:
  32     oneOf:
  33       - items:
  34           - enum:
  35               - amd,mbv32
  36               - andestech,ax45mp
  37               - canaan,k210
  38               - sifive,bullet0
  39               - sifive,e5
  40               - sifive,e7
  41               - sifive,e71
  42               - sifive,rocket0
  43               - sifive,s7
  44               - sifive,u5
  45               - sifive,u54
  46               - sifive,u7
  47               - sifive,u74
  48               - sifive,u74-mc
  49               - thead,c906
  50               - thead,c910
  51               - thead,c920
  52           - const: riscv
  53       - items:
  54           - enum:
  55               - sifive,e51
  56               - sifive,u54-mc
  57           - const: sifive,rocket0
  58           - const: riscv
  59       - const: riscv    # Simulator only
  60     description:
  61       Identifies that the hart uses the RISC-V instruction set
  62       and identifies the type of the hart.
  63
  64   mmu-type:
  65     description:
  66       Identifies the largest MMU address translation mode supported by
  67       this hart.  These values originate from the RISC-V Privileged
  68       Specification document, available from
  69       https://riscv.org/specifications/
  70     $ref: /schemas/types.yaml#/definitions/string
  71     enum:
  72       - riscv,sv32
  73       - riscv,sv39
  74       - riscv,sv48
  75       - riscv,sv57
  76       - riscv,none
  77
  78   riscv,cbom-block-size:
  79     $ref: /schemas/types.yaml#/definitions/uint32
  80     description:
  81       The blocksize in bytes for the Zicbom cache operations.
  82
  83   riscv,cbop-block-size:
  84     $ref: /schemas/types.yaml#/definitions/uint32
  85     description:
  86       The blocksize in bytes for the Zicbop cache operations.
  87
  88   riscv,cboz-block-size:
  89     $ref: /schemas/types.yaml#/definitions/uint32
  90     description:
  91       The blocksize in bytes for the Zicboz cache operations.
  92
  93   # RISC-V has multiple properties for cache op block sizes as the sizes
  94   # differ between individual CBO extensions
  95   cache-op-block-size: false
  96   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  97   timebase-frequency: false
  98
  99   interrupt-controller:
 100     type: object
 101     additionalProperties: false
 102     description: Describes the CPU's local interrupt controller
 103
 104     properties:
 105       '#interrupt-cells':
 106         const: 1
 107
 108       compatible:
 109         const: riscv,cpu-intc
 110
 111       interrupt-controller: true
 112
 113     required:
 114       - '#interrupt-cells'
 115       - compatible
 116       - interrupt-controller
 117
 118   cpu-idle-states:
 119     $ref: /schemas/types.yaml#/definitions/phandle-array
 120     items:
 121       maxItems: 1
 122     description: |
 123       List of phandles to idle state nodes supported
 124       by this hart (see ./idle-states.yaml).
 125
 126   capacity-dmips-mhz:
 127     description:
 128       u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
 129       DMIPS/MHz, relative to highest capacity-dmips-mhz
 130       in the system.
 131
 132 anyOf:
 133   - required:
 134       - riscv,isa
 135   - required:
 136       - riscv,isa-base
 137
 138 dependencies:
 139   riscv,isa-base: [ "riscv,isa-extensions" ]
 140   riscv,isa-extensions: [ "riscv,isa-base" ]
 141
 142 required:
 143   - interrupt-controller
 144
 145 unevaluatedProperties: false
 146
 147 examples:
 148   - |
 149     // Example 1: SiFive Freedom U540G Development Kit
 150     cpus {
 151         #address-cells = <1>;
 152         #size-cells = <0>;
 153         timebase-frequency = <1000000>;
 154         cpu@0 {
 155                 clock-frequency = <0>;
 156                 compatible = "sifive,rocket0", "riscv";
 157                 device_type = "cpu";
 158                 i-cache-block-size = <64>;
 159                 i-cache-sets = <128>;
 160                 i-cache-size = <16384>;
 161                 reg = <0>;
 162                 riscv,isa-base = "rv64i";
 163                 riscv,isa-extensions = "i", "m", "a", "c";
 164
 165                 cpu_intc0: interrupt-controller {
 166                         #interrupt-cells = <1>;
 167                         compatible = "riscv,cpu-intc";
 168                         interrupt-controller;
 169                 };
 170         };
 171         cpu@1 {
 172                 clock-frequency = <0>;
 173                 compatible = "sifive,rocket0", "riscv";
 174                 d-cache-block-size = <64>;
 175                 d-cache-sets = <64>;
 176                 d-cache-size = <32768>;
 177                 d-tlb-sets = <1>;
 178                 d-tlb-size = <32>;
 179                 device_type = "cpu";
 180                 i-cache-block-size = <64>;
 181                 i-cache-sets = <64>;
 182                 i-cache-size = <32768>;
 183                 i-tlb-sets = <1>;
 184                 i-tlb-size = <32>;
 185                 mmu-type = "riscv,sv39";
 186                 reg = <1>;
 187                 tlb-split;
 188                 riscv,isa-base = "rv64i";
 189                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 190
 191                 cpu_intc1: interrupt-controller {
 192                         #interrupt-cells = <1>;
 193                         compatible = "riscv,cpu-intc";
 194                         interrupt-controller;
 195                 };
 196         };
 197     };
 198
 199   - |
 200     // Example 2: Spike ISA Simulator with 1 Hart
 201     cpus {
 202         #address-cells = <1>;
 203         #size-cells = <0>;
 204         cpu@0 {
 205                 device_type = "cpu";
 206                 reg = <0>;
 207                 compatible = "riscv";
 208                 mmu-type = "riscv,sv48";
 209                 riscv,isa-base = "rv64i";
 210                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 211
 212                 interrupt-controller {
 213                         #interrupt-cells = <1>;
 214                         interrupt-controller;
 215                         compatible = "riscv,cpu-intc";
 216                 };
 217         };
 218     };
 219 ...