1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware
14 on the Qualcomm DSP Hexagon cores.
19 - qcom,sm8550-adsp-pas
20 - qcom,sm8550-cdsp-pas
21 - qcom,sm8550-mpss-pas
22 - qcom,sm8650-adsp-pas
23 - qcom,sm8650-cdsp-pas
24 - qcom,sm8650-mpss-pas
25 - qcom,x1e80100-adsp-pas
26 - qcom,x1e80100-cdsp-pas
33 - description: XO clock
40 $ref: /schemas/types.yaml#/definitions/phandle
41 description: Reference to the AOSS side-channel message RAM.
46 $ref: /schemas/types.yaml#/definitions/string-array
48 - description: Firmware name of the Hexagon core
49 - description: Firmware name of the Hexagon Devicetree
54 - description: Memory region for main Firmware authentication
55 - description: Memory region for Devicetree Firmware authentication
56 - description: DSM Memory region
57 - description: DSM Memory region 2
58 - description: Memory region for Qlink Logging
66 - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
71 - qcom,sm8550-adsp-pas
72 - qcom,sm8550-cdsp-pas
73 - qcom,sm8650-adsp-pas
74 - qcom,x1e80100-adsp-pas
75 - qcom,x1e80100-cdsp-pas
88 - qcom,sm8650-cdsp-pas
102 - qcom,sm8550-mpss-pas
116 - qcom,sm8650-mpss-pas
131 - qcom,sm8550-adsp-pas
132 - qcom,sm8650-adsp-pas
133 - qcom,x1e80100-adsp-pas
138 - description: LCX power domain
139 - description: LMX power domain
149 - qcom,sm8550-mpss-pas
150 - qcom,sm8650-mpss-pas
155 - description: CX power domain
156 - description: MSS power domain
165 - qcom,sm8550-cdsp-pas
166 - qcom,sm8650-cdsp-pas
167 - qcom,x1e80100-cdsp-pas
172 - description: CX power domain
173 - description: MXC power domain
174 - description: NSP power domain
181 unevaluatedProperties: false
185 #include <dt-bindings/clock/qcom,rpmh.h>
186 #include <dt-bindings/interrupt-controller/irq.h>
187 #include <dt-bindings/mailbox/qcom-ipcc.h>
189 remoteproc@30000000 {
190 compatible = "qcom,sm8550-adsp-pas";
191 reg = <0x030000000 0x100>;
193 clocks = <&rpmhcc RPMH_CXO_CLK>;
196 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
197 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
198 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
199 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
200 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
201 interrupt-names = "wdog", "fatal", "ready",
202 "handover", "stop-ack";
204 memory-region = <&adsp_mem>, <&dtb_adsp_mem>;
206 firmware-name = "qcom/sm8550/adsp.mbn",
207 "qcom/sm8550/adsp_dtb.mbn";
209 power-domains = <&rpmhpd_sm8550_lcx>,
210 <&rpmhpd_sm8550_lmx>;
211 power-domain-names = "lcx", "lmx";
213 qcom,qmp = <&aoss_qmp>;
214 qcom,smem-states = <&smp2p_adsp_out 0>;
215 qcom,smem-state-names = "stop";
218 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
219 IPCC_MPROC_SIGNAL_GLINK_QMP
220 IRQ_TYPE_EDGE_RISING>;
221 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
224 qcom,remote-pid = <2>;