1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
19 - qcom,sc8280xp-qmp-usb43dp-phy
20 - qcom,sm6350-qmp-usb3-dp-phy
21 - qcom,sm8350-qmp-usb3-dp-phy
22 - qcom,sm8450-qmp-usb3-dp-phy
23 - qcom,sm8550-qmp-usb3-dp-phy
56 See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
61 See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
65 Flag the PHY as possible handler of USB Type-C orientation switching
69 $ref: /schemas/graph.yaml#/properties/ports
72 $ref: /schemas/graph.yaml#/properties/port
73 description: Output endpoint of the PHY
76 $ref: /schemas/graph.yaml#/properties/port
77 description: Incoming endpoint from the USB controller
80 $ref: /schemas/graph.yaml#/properties/port
81 description: Incoming endpoint from the DisplayPort controller
96 additionalProperties: false
100 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
103 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
104 reg = <0x088eb000 0x4000>;
106 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
107 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
108 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
109 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
110 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
112 power-domains = <&gcc USB30_PRIM_GDSC>;
114 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
115 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
116 reset-names = "phy", "common";
118 vdda-phy-supply = <&vreg_l9d>;
119 vdda-pll-supply = <&vreg_l4d>;
127 #address-cells = <1>;
134 remote-endpoint = <&typec_connector_ss>;
142 remote-endpoint = <&dwc3_ss_out>;
150 remote-endpoint = <&mdss_dp_out>;