1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek switches for unmanaged switches
13 - Linus Walleij <linus.walleij@linaro.org>
16 Realtek advertises these chips as fast/gigabit switches or unmanaged
17 switches. They can be controlled using different interfaces, like SMI,
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
22 not use the MDIO protocol. This binding defines how to specify the
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
24 and it must be inserted inside a platform node.
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
30 The compatible string is only used to identify which (silicon) family the
31 switch belongs to. Roughly speaking, a family is any set of Realtek switches
32 whose chip identification register(s) have a common location and semantics.
33 The different models in a given family can be automatically disambiguated by
34 parsing the chip identification register(s) according to the given family,
35 avoiding the need for a unique compatible string for each model.
44 Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
45 RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
46 RTL8367SB, RTL8370MB, RTL8310SR
48 Use with models RTL8366RB, RTL8366S
51 description: GPIO line for the MDC clock line.
55 description: GPIO line for the MDIO data line.
59 description: GPIO to be used to reset the whole device
65 if the LED drivers are not used in the hardware design,
66 this will disable them so they are not turned on
72 This defines an interrupt controller with an IRQ line (typically
73 a GPIO) that will demultiplex and handle the interrupt from the single
74 interrupt line coming out of one of the Realtek switch chips. It most
75 importantly provides link up/down interrupts to the PHY blocks inside
80 interrupt-controller: true
85 A single IRQ line from the switch, either active LOW or HIGH
94 - interrupt-controller
99 $ref: /schemas/net/mdio.yaml#
100 unevaluatedProperties: false
104 const: realtek,smi-mdio
137 unevaluatedProperties: false
141 #include <dt-bindings/gpio/gpio.h>
142 #include <dt-bindings/interrupt-controller/irq.h>
146 compatible = "realtek,rtl8366rb";
147 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
148 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
149 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
150 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
152 switch_intc1: interrupt-controller {
153 /* GPIO 15 provides the interrupt */
154 interrupt-parent = <&gpio0>;
155 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
156 interrupt-controller;
157 #address-cells = <0>;
158 #interrupt-cells = <1>;
162 #address-cells = <1>;
167 phy-handle = <&phy0>;
172 phy-handle = <&phy1>;
177 phy-handle = <&phy2>;
182 phy-handle = <&phy3>;
187 phy-handle = <&phy4>;
202 compatible = "realtek,smi-mdio";
203 #address-cells = <1>;
206 phy0: ethernet-phy@0 {
208 interrupt-parent = <&switch_intc1>;
211 phy1: ethernet-phy@1 {
213 interrupt-parent = <&switch_intc1>;
216 phy2: ethernet-phy@2 {
218 interrupt-parent = <&switch_intc1>;
221 phy3: ethernet-phy@3 {
223 interrupt-parent = <&switch_intc1>;
226 phy4: ethernet-phy@4 {
228 interrupt-parent = <&switch_intc1>;
236 #include <dt-bindings/gpio/gpio.h>
237 #include <dt-bindings/interrupt-controller/irq.h>
241 compatible = "realtek,rtl8365mb";
242 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
243 mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
244 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
246 switch_intc2: interrupt-controller {
247 interrupt-parent = <&gpio5>;
248 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <1>;
255 #address-cells = <1>;
260 phy-handle = <ðphy0>;
265 phy-handle = <ðphy1>;
270 phy-handle = <ðphy2>;
275 phy-handle = <ðphy3>;
282 tx-internal-delay-ps = <2000>;
283 rx-internal-delay-ps = <2000>;
294 compatible = "realtek,smi-mdio";
295 #address-cells = <1>;
298 ethphy0: ethernet-phy@0 {
300 interrupt-parent = <&switch_intc2>;
303 ethphy1: ethernet-phy@1 {
305 interrupt-parent = <&switch_intc2>;
308 ethphy2: ethernet-phy@2 {
310 interrupt-parent = <&switch_intc2>;
313 ethphy3: ethernet-phy@3 {
315 interrupt-parent = <&switch_intc2>;
323 #include <dt-bindings/gpio/gpio.h>
324 #include <dt-bindings/interrupt-controller/irq.h>
327 #address-cells = <1>;
331 compatible = "realtek,rtl8365mb";
334 reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
336 switch_intc3: interrupt-controller {
337 interrupt-parent = <&gpio0>;
338 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
339 interrupt-controller;
340 #address-cells = <0>;
341 #interrupt-cells = <1>;
345 #address-cells = <1>;
375 ethernet = <ðernet>;
377 tx-internal-delay-ps = <2000>;
378 rx-internal-delay-ps = <0>;