Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ZynqMP Mode Pin GPIO controller
   8
   9 description:
  10   PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
  11   GPIO controller with configurable from numbers of pins (from 0 to 3 per
  12   PS_MODE). Every pin can be configured as input/output.
  13
  14 maintainers:
  15   - Piyush Mehta <piyush.mehta@amd.com>
  16
  17 properties:
  18   compatible:
  19     const: xlnx,zynqmp-gpio-modepin
  20
  21   gpio-controller: true
  22
  23   "#gpio-cells":
  24     const: 2
  25
  26   label: true
  27
  28 required:
  29   - compatible
  30   - gpio-controller
  31   - "#gpio-cells"
  32
  33 additionalProperties: false
  34
  35 examples:
  36   - |
  37     zynqmp-firmware {
  38         gpio {
  39             compatible = "xlnx,zynqmp-gpio-modepin";
  40             gpio-controller;
  41             #gpio-cells = <2>;
  42             label = "modepin";
  43         };
  44     };
  45
  46 ...