Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for QCM2290 target
   8
   9 maintainers:
  10   - Loic Poulain <loic.poulain@linaro.org>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  15   and DPU are mentioned for QCM2290 target.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: qcom,qcm2290-mdss
  21
  22   reg:
  23     maxItems: 1
  24
  25   reg-names:
  26     const: mdss
  27
  28   power-domains:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Display AHB clock from gcc
  34       - description: Display AXI clock
  35       - description: Display core clock
  36
  37   clock-names:
  38     items:
  39       - const: iface
  40       - const: bus
  41       - const: core
  42
  43   interrupts:
  44     maxItems: 1
  45
  46   interrupt-controller: true
  47
  48   "#address-cells": true
  49
  50   "#size-cells": true
  51
  52   "#interrupt-cells":
  53     const: 1
  54
  55   iommus:
  56     items:
  57       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
  58       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
  59
  60   ranges: true
  61
  62   interconnects:
  63     items:
  64       - description: Interconnect path specifying the port ids for data bus
  65
  66   interconnect-names:
  67     const: mdp0-mem
  68
  69 patternProperties:
  70   "^display-controller@[0-9a-f]+$":
  71     type: object
  72     description: Node containing the properties of DPU.
  73
  74     properties:
  75       compatible:
  76         items:
  77           - const: qcom,qcm2290-dpu
  78
  79       reg:
  80         items:
  81           - description: Address offset and size for mdp register set
  82           - description: Address offset and size for vbif register set
  83
  84       reg-names:
  85         items:
  86           - const: mdp
  87           - const: vbif
  88
  89       clocks:
  90         items:
  91           - description: Display AXI clock from gcc
  92           - description: Display AHB clock from dispcc
  93           - description: Display core clock from dispcc
  94           - description: Display lut clock from dispcc
  95           - description: Display vsync clock from dispcc
  96
  97       clock-names:
  98         items:
  99           - const: bus
 100           - const: iface
 101           - const: core
 102           - const: lut
 103           - const: vsync
 104
 105       interrupts:
 106         maxItems: 1
 107
 108       power-domains:
 109         maxItems: 1
 110
 111       operating-points-v2: true
 112
 113       ports:
 114         $ref: /schemas/graph.yaml#/properties/ports
 115         description: |
 116           Contains the list of output ports from DPU device. These ports
 117           connect to interfaces that are external to the DPU hardware,
 118           such as DSI. Each output port contains an endpoint that
 119           describes how it is connected to an external interface.
 120
 121         properties:
 122           port@0:
 123             $ref: /schemas/graph.yaml#/properties/port
 124             description: DPU_INTF1 (DSI1)
 125
 126         required:
 127           - port@0
 128
 129     required:
 130       - compatible
 131       - reg
 132       - reg-names
 133       - clocks
 134       - interrupts
 135       - power-domains
 136       - operating-points-v2
 137       - ports
 138
 139 required:
 140   - compatible
 141   - reg
 142   - reg-names
 143   - power-domains
 144   - clocks
 145   - interrupts
 146   - interrupt-controller
 147   - iommus
 148   - ranges
 149
 150 additionalProperties: false
 151
 152 examples:
 153   - |
 154     #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
 155     #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
 156     #include <dt-bindings/interrupt-controller/arm-gic.h>
 157     #include <dt-bindings/interconnect/qcom,qcm2290.h>
 158     #include <dt-bindings/power/qcom-rpmpd.h>
 159
 160     mdss: mdss@5e00000 {
 161         #address-cells = <1>;
 162         #size-cells = <1>;
 163         compatible = "qcom,qcm2290-mdss";
 164         reg = <0x05e00000 0x1000>;
 165         reg-names = "mdss";
 166         power-domains = <&dispcc MDSS_GDSC>;
 167         clocks = <&gcc GCC_DISP_AHB_CLK>,
 168                  <&gcc GCC_DISP_HF_AXI_CLK>,
 169                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 170         clock-names = "iface", "bus", "core";
 171
 172         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 173         interrupt-controller;
 174         #interrupt-cells = <1>;
 175
 176         interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
 177         interconnect-names = "mdp0-mem";
 178
 179         iommus = <&apps_smmu 0x420 0x2>,
 180                  <&apps_smmu 0x421 0x0>;
 181         ranges;
 182
 183         mdss_mdp: display-controller@5e01000 {
 184                 compatible = "qcom,qcm2290-dpu";
 185                 reg = <0x05e01000 0x8f000>,
 186                       <0x05eb0000 0x2008>;
 187                 reg-names = "mdp", "vbif";
 188
 189                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 190                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
 191                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
 192                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 193                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 194                 clock-names = "bus", "iface", "core", "lut", "vsync";
 195
 196                 operating-points-v2 = <&mdp_opp_table>;
 197                 power-domains = <&rpmpd QCM2290_VDDCX>;
 198
 199                 interrupt-parent = <&mdss>;
 200                 interrupts = <0>;
 201
 202                 ports {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205
 206                         port@0 {
 207                                 reg = <0>;
 208                                 dpu_intf1_out: endpoint {
 209                                         remote-endpoint = <&dsi0_in>;
 210                                 };
 211                         };
 212                 };
 213          };
 214     };
 215 ...