Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display Clock & Reset Controller for SM8550
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Neil Armstrong <neil.armstrong@linaro.org>
  12
  13 description: |
  14   Qualcomm display clock control module provides the clocks, resets and power
  15   domains on SM8550.
  16
  17   See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - qcom,sm8550-dispcc
  23
  24   clocks:
  25     items:
  26       - description: Board XO source
  27       - description: Board Always On XO source
  28       - description: Display's AHB clock
  29       - description: sleep clock
  30       - description: Byte clock from DSI PHY0
  31       - description: Pixel clock from DSI PHY0
  32       - description: Byte clock from DSI PHY1
  33       - description: Pixel clock from DSI PHY1
  34       - description: Link clock from DP PHY0
  35       - description: VCO DIV clock from DP PHY0
  36       - description: Link clock from DP PHY1
  37       - description: VCO DIV clock from DP PHY1
  38       - description: Link clock from DP PHY2
  39       - description: VCO DIV clock from DP PHY2
  40       - description: Link clock from DP PHY3
  41       - description: VCO DIV clock from DP PHY3
  42
  43   '#clock-cells':
  44     const: 1
  45
  46   '#reset-cells':
  47     const: 1
  48
  49   '#power-domain-cells':
  50     const: 1
  51
  52   reg:
  53     maxItems: 1
  54
  55   power-domains:
  56     description:
  57       A phandle and PM domain specifier for the MMCX power domain.
  58     maxItems: 1
  59
  60   required-opps:
  61     description:
  62       A phandle to an OPP node describing required MMCX performance point.
  63     maxItems: 1
  64
  65 required:
  66   - compatible
  67   - reg
  68   - clocks
  69   - '#clock-cells'
  70   - '#reset-cells'
  71   - '#power-domain-cells'
  72
  73 additionalProperties: false
  74
  75 examples:
  76   - |
  77     #include <dt-bindings/clock/qcom,sm8550-gcc.h>
  78     #include <dt-bindings/clock/qcom,rpmh.h>
  79     #include <dt-bindings/power/qcom,rpmhpd.h>
  80     clock-controller@af00000 {
  81       compatible = "qcom,sm8550-dispcc";
  82       reg = <0x0af00000 0x10000>;
  83       clocks = <&rpmhcc RPMH_CXO_CLK>,
  84                <&rpmhcc RPMH_CXO_CLK_A>,
  85                <&gcc GCC_DISP_AHB_CLK>,
  86                <&sleep_clk>,
  87                <&dsi0_phy 0>,
  88                <&dsi0_phy 1>,
  89                <&dsi1_phy 0>,
  90                <&dsi1_phy 1>,
  91                <&dp0_phy 0>,
  92                <&dp0_phy 1>,
  93                <&dp1_phy 0>,
  94                <&dp1_phy 1>,
  95                <&dp2_phy 0>,
  96                <&dp2_phy 1>,
  97                <&dp3_phy 0>,
  98                <&dp3_phy 1>;
  99       #clock-cells = <1>;
 100       #reset-cells = <1>;
 101       #power-domain-cells = <1>;
 102       power-domains = <&rpmhpd RPMHPD_MMCX>;
 103       required-opps = <&rpmhpd_opp_low_svs>;
 104     };
 105 ...