1 /* Optimized memcmp implementation for POWER7/PowerPC64.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
23 /* int [r3] memcmp (const char *s1 [r3],
28 EALIGN (BP_SYM(memcmp),4,0)
33 #define rSTR1 r3 /* first string arg */
34 #define rSTR2 r4 /* second string arg */
35 #define rN r5 /* max string length */
36 /* Note: The Bounded pointer support in this code is broken. This code
37 was inherited from PPC32 and that support was never completed.
38 Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
39 #define rWORD1 r6 /* current word in s1 */
40 #define rWORD2 r7 /* current word in s2 */
41 #define rWORD3 r8 /* next word in s1 */
42 #define rWORD4 r9 /* next word in s2 */
43 #define rWORD5 r10 /* next word in s1 */
44 #define rWORD6 r11 /* next word in s2 */
45 #define rBITDIF r12 /* bits that differ in s1 & s2 words */
46 #define rWORD7 r30 /* next word in s1 */
47 #define rWORD8 r31 /* next word in s2 */
53 clrldi rBITDIF,rSTR1,61
55 beq- cr6,L(zeroLength)
58 /* If less than 8 bytes or not aligned, use the unalligned
60 blt cr1,L(bytealigned)
64 cfi_offset(rWORD7,-16)
66 /* At this point we know both strings have the same alignment and the
67 compare length is at least 8 bytes. rBITDIF containes the low order
68 3 bits of rSTR1 and cr5 contains the result of the logical compare
69 of rBITDIF to 0. If rBITDIF == 0 then we are already double word
70 aligned and can perform the DWaligned loop.
72 Otherwise we know the two strings have the same alignment (but not
73 yet DW). So we can force the string addresses to the next lower DW
74 boundary and special case this first DW word using shift left to
75 ellimiate bits preceeding the first byte. Since we want to join the
76 normal (DWaligned) compare loop, starting at the second double word,
77 we need to adjust the length (rN) and special case the loop
78 versioning for the first DW. This insures that the loop count is
79 correct and the first DW (shifted) is in the expected resister pair. */
87 srdi rTMP,rN,5 /* Divide by 32 */
88 andi. rBITDIF,rN,24 /* Get the DW remainder */
102 sld rWORD5,rWORD1,r11
103 sld rWORD6,rWORD2,r11
104 cmpld cr5,rWORD5,rWORD6
106 /* Do something useful in this cycle since we have to branch anyway. */
109 cmpld cr0,rWORD1,rWORD2
111 /* Remainder is 16 */
114 sld rWORD5,rWORD1,r11
115 sld rWORD6,rWORD2,r11
116 cmpld cr6,rWORD5,rWORD6
118 /* Do something useful in this cycle since we have to branch anyway. */
121 cmpld cr5,rWORD7,rWORD8
123 /* Remainder is 24 */
126 sld rWORD3,rWORD1,r11
127 sld rWORD4,rWORD2,r11
128 cmpld cr1,rWORD3,rWORD4
130 /* Count is a multiple of 32, remainder is 0 */
134 sld rWORD1,rWORD1,r11
135 sld rWORD2,rWORD2,r11
136 cmpld cr0,rWORD1,rWORD2
139 /* At this point we know both strings are double word aligned and the
140 compare length is at least 8 bytes. */
143 andi. rBITDIF,rN,24 /* Get the DW remainder */
144 srdi rTMP,rN,5 /* Divide by 32 */
145 cmpldi cr1,rBITDIF,16
156 /* Normally we'd use rWORD7/rWORD8 here, but since we might exit early
157 (8-15 byte compare), we want to use only volitile registers. This
158 means we can avoid restoring non-volitile registers since we did not
159 change any on the early exit path. The key here is the non-early
160 exit path only cares about the condition code (cr5), not about which
161 register pair was used. */
164 cmpld cr5,rWORD5,rWORD6
168 cmpld cr0,rWORD1,rWORD2
172 cmpld cr1,rWORD3,rWORD4
175 cmpld cr6,rWORD5,rWORD6
182 cmpld cr5,rWORD7,rWORD8
191 subfic rN,r12,64 /* Shift count is 64 - (rN * 8). */
196 /* Remainder is 16 */
202 cmpld cr6,rWORD5,rWORD6
206 cmpld cr5,rWORD7,rWORD8
210 cmpld cr0,rWORD1,rWORD2
213 cmpld cr1,rWORD3,rWORD4
219 /* Again we are on a early exit path (16-23 byte compare), we want to
220 only use volitile registers and avoid restoring non-volitile
226 cmpld cr5,rWORD3,rWORD4
232 subfic rN,r12,64 /* Shift count is 64 - (rN * 8). */
237 /* Remainder is 24 */
243 cmpld cr1,rWORD3,rWORD4
247 cmpld cr6,rWORD5,rWORD6
251 cmpld cr5,rWORD7,rWORD8
254 cmpld cr0,rWORD1,rWORD2
260 /* Again we are on a early exit path (24-31 byte compare), we want to
261 only use volitile registers and avoid restoring non-volitile
267 cmpld cr5,rWORD1,rWORD2
273 subfic rN,r12,64 /* Shift count is 64 - (rN * 8). */
279 /* Count is a multiple of 32, remainder is 0 */
285 cmpld cr0,rWORD1,rWORD2
289 cmpld cr1,rWORD3,rWORD4
292 cmpld cr6,rWORD5,rWORD6
295 cmpld cr5,rWORD7,rWORD8
298 bdz- L(d24) /* Adjust CTR as we start with +4 */
299 /* This is the primary loop */
304 cmpld cr1,rWORD3,rWORD4
309 cmpld cr6,rWORD5,rWORD6
314 cmpld cr5,rWORD7,rWORD8
320 cmpld cr0,rWORD1,rWORD2
324 cmpld cr1,rWORD3,rWORD4
326 cmpld cr6,rWORD5,rWORD6
328 cmpld cr5,rWORD7,rWORD8
341 subfic rN,r12,64 /* Shift count is 64 - (rN * 8). */
343 /* At this point we have a remainder of 1 to 7 bytes to compare. Since
344 we are aligned it is safe to load the whole double word, and use
345 shift right double to elliminate bits beyond the compare length. */
351 cmpld cr5,rWORD1,rWORD2
392 beq cr6,L(zeroLength)
394 /* We need to prime this loop. This loop is swing modulo scheduled
395 to avoid pipe delays. The dependent instruction latencies (load to
396 compare to conditional branch) is 2 to 3 cycles. In this loop each
397 dispatch group ends in a branch and takes 1 cycle. Effectively
398 the first iteration of the loop only serves to load operands and
399 branches based on compares are delayed until the next loop.
401 So we must precondition some registers and condition codes so that
402 we don't exit the loop early on the first iteration. */
407 cmpld cr0,rWORD1,rWORD2
411 cmpld cr1,rWORD3,rWORD4
421 cmpld cr6,rWORD5,rWORD6
428 cmpld cr0,rWORD1,rWORD2
435 cmpld cr1,rWORD3,rWORD4
438 /* We speculatively loading bytes before we have tested the previous
439 bytes. But we must avoid overrunning the length (in the ctr) to
440 prevent these speculative loads from causing a segfault. In this
441 case the loop will exit early (before the all pending bytes are
442 tested. In this case we must complete the pending operations
479 sub rRTN,rWORD5,rWORD6
485 sub rRTN,rWORD3,rWORD4
489 sub rRTN,rWORD1,rWORD2
500 /* At this point we know the strings have different alignment and the
501 compare length is at least 8 bytes. rBITDIF containes the low order
502 3 bits of rSTR1 and cr5 contains the result of the logical compare
503 of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word
504 aligned and can perform the DWunaligned loop.
506 Otherwise we know that rSTR1 is not aready DW aligned yet.
507 So we can force the string addresses to the next lower DW
508 boundary and special case this first DW word using shift left to
509 ellimiate bits preceeding the first byte. Since we want to join the
510 normal (DWaligned) compare loop, starting at the second double word,
511 we need to adjust the length (rN) and special case the loop
512 versioning for the first DW. This insures that the loop count is
513 correct and the first DW (shifted) is in the expected resister pair. */
514 #define rSHL r29 /* Unaligned shift left count. */
515 #define rSHR r28 /* Unaligned shift right count. */
516 #define rB r27 /* Left rotation temp for rWORD2. */
517 #define rD r26 /* Left rotation temp for rWORD4. */
518 #define rF r25 /* Left rotation temp for rWORD6. */
519 #define rH r24 /* Left rotation temp for rWORD8. */
520 #define rA r0 /* Right rotation temp for rWORD2. */
521 #define rC r12 /* Right rotation temp for rWORD4. */
522 #define rE r0 /* Right rotation temp for rWORD6. */
523 #define rG r12 /* Right rotation temp for rWORD8. */
528 beq cr6,L(duzeroLength)
531 beq cr5,L(DWunaligned)
534 /* Adjust the logical start of rSTR2 ro compensate for the extra bits
535 in the 1st rSTR1 DW. */
536 sub r27,rSTR2,rBITDIF
537 /* But do not attempt to address the DW before that DW that contains
538 the actual start of rSTR2. */
542 /* Compute the leaft/right shift counts for the unalign rSTR2,
543 compensating for the logical (DW aligned) start of rSTR1. */
555 srdi rTMP,rN,5 /* Divide by 32 */
556 andi. rBITDIF,rN,24 /* Get the DW remainder */
557 /* We normally need to load 2 DWs to start the unaligned rSTR2, but in
558 this special case those bits may be discarded anyway. Also we
559 must avoid loading a DW where none of the bits are part of rSTR2 as
560 this may cross a page boundary and cause a page fault. */
565 sld rWORD8,rWORD8,rSHL
570 cmpldi cr1,rBITDIF,16
584 sld rWORD7,rWORD1,r11
585 sld rWORD8,rWORD8,r11
587 /* At this point we exit early with the first double word compare
588 complete and remainder of 0 to 7 bytes. See L(du14) for details on
589 how we handle the remaining bytes. */
590 cmpld cr5,rWORD7,rWORD8
600 /* Remainder is 16 */
604 sld rWORD5,rWORD1,r11
605 sld rWORD6,rWORD8,r11
607 /* Remainder is 24 */
611 sld rWORD3,rWORD1,r11
612 sld rWORD4,rWORD8,r11
614 /* Count is a multiple of 32, remainder is 0 */
620 sld rWORD1,rWORD1,r11
621 sld rWORD2,rWORD8,r11
624 /* At this point we know rSTR1 is double word aligned and the
625 compare length is at least 8 bytes. */
633 srdi rTMP,rN,5 /* Divide by 32 */
636 andi. rBITDIF,rN,24 /* Get the DW remainder */
642 cmpldi cr1,rBITDIF,16
663 cmpld cr5,rWORD7,rWORD8
669 cmpld cr0,rWORD1,rWORD2
676 cmpld cr1,rWORD3,rWORD4
681 cmpld cr6,rWORD5,rWORD6
684 /* At this point we exit early with the first double word compare
685 complete and remainder of 0 to 7 bytes. See L(du14) for details on
686 how we handle the remaining bytes. */
688 cmpld cr5,rWORD7,rWORD8
698 /* Remainder is 16 */
708 cmpld cr6,rWORD5,rWORD6
715 cmpld cr5,rWORD7,rWORD8
722 cmpld cr0,rWORD1,rWORD2
729 cmpld cr1,rWORD3,rWORD4
733 cmpld cr5,rWORD7,rWORD8
747 /* Remainder is 24 */
757 cmpld cr1,rWORD3,rWORD4
763 cmpld cr6,rWORD5,rWORD6
771 cmpld cr5,rWORD7,rWORD8
778 cmpld cr0,rWORD1,rWORD2
785 cmpld cr5,rWORD7,rWORD8
797 /* Count is a multiple of 32, remainder is 0 */
808 cmpld cr0,rWORD1,rWORD2
814 cmpld cr1,rWORD3,rWORD4
821 cmpld cr6,rWORD5,rWORD6
826 cmpld cr5,rWORD7,rWORD8
827 bdz L(du24) /* Adjust CTR as we start with +4 */
828 /* This is the primary loop */
833 cmpld cr1,rWORD3,rWORD4
841 cmpld cr6,rWORD5,rWORD6
849 cmpld cr5,rWORD7,rWORD8
857 cmpld cr0,rWORD1,rWORD2
866 cmpld cr1,rWORD3,rWORD4
868 cmpld cr6,rWORD5,rWORD6
870 cmpld cr5,rWORD7,rWORD8
880 /* At this point we have a remainder of 1 to 7 bytes to compare. We use
881 shift right double to elliminate bits beyond the compare length.
882 This allows the use of double word subtract to compute the final
885 However it may not be safe to load rWORD2 which may be beyond the
886 string length. So we compare the bit length of the remainder to
887 the right shift count (rSHR). If the bit count is less than or equal
888 we do not need to load rWORD2 (all significant bits are already in
900 subfic rN,rN,64 /* Shift count is 64 - (rN * 8). */
909 cmpld cr0,rWORD1,rWORD2
912 beq cr0,L(dureturn24)
923 bgt cr0,L(dureturn29)
933 bgt cr1,L(dureturn29)
943 bgt cr6,L(dureturn29)
953 bgt cr5,L(dureturn29)
981 END (BP_SYM (memcmp))
982 libc_hidden_builtin_def (memcmp)
983 weak_alias (memcmp,bcmp)