1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // Copyright(c) 2023 Intel Corporation. All rights reserved.
6 * Hardware interface for audio DSP on LunarLake.
9 #include <linux/firmware.h>
10 #include <sound/hda_register.h>
11 #include <sound/sof/ipc4/header.h>
12 #include <trace/events/sof_intel.h>
13 #include "../ipc4-priv.h"
17 #include "../sof-audio.h"
19 #include <sound/hda-mlink.h>
22 struct snd_sof_dsp_ops sof_lnl_ops;
23 EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
25 static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = {
26 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
27 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
31 /* this helps allows the DSP to setup DMIC/SSP */
32 static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus, bool enable)
36 ret = hdac_bus_eml_enable_offload(bus, true,
37 AZX_REG_ML_LEPTR_ID_INTEL_SSP, enable);
41 ret = hdac_bus_eml_enable_offload(bus, true,
42 AZX_REG_ML_LEPTR_ID_INTEL_DMIC, enable);
49 static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev)
53 ret = hda_dsp_probe(sdev);
57 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true);
60 static void lnl_hda_dsp_remove(struct snd_sof_dev *sdev)
64 ret = hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), false);
67 "Failed to disable offload for DMIC/SSP: %d\n", ret);
72 static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev)
76 ret = hda_dsp_resume(sdev);
80 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true);
83 static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
87 ret = hda_dsp_runtime_resume(sdev);
91 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true);
94 static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev)
96 if (sdev->first_boot) {
97 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
99 /* Check if IMR boot is usable */
100 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
101 hda->imrboot_supported = true;
107 int sof_lnl_ops_init(struct snd_sof_dev *sdev)
109 struct sof_ipc4_fw_data *ipc4_data;
111 /* common defaults */
112 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
115 if (!sdev->dspless_mode_selected) {
116 sof_lnl_ops.probe = lnl_hda_dsp_probe;
117 sof_lnl_ops.remove = lnl_hda_dsp_remove;
121 sof_lnl_ops.shutdown = hda_dsp_shutdown;
124 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread;
127 sof_lnl_ops.send_msg = mtl_ipc_send_msg;
128 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
129 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
132 sof_lnl_ops.debug_map = lnl_dsp_debugfs;
133 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs);
134 sof_lnl_ops.dbg_dump = mtl_dsp_dump;
135 sof_lnl_ops.ipc_dump = mtl_ipc_dump;
137 /* pre/post fw run */
138 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
139 sof_lnl_ops.post_fw_run = lnl_dsp_post_fw_run;
141 /* parse platform specific extended manifest */
142 sof_lnl_ops.parse_platform_ext_manifest = NULL;
144 /* dsp core get/put */
145 /* TODO: add core_get and core_put */
148 if (!sdev->dspless_mode_selected) {
149 sof_lnl_ops.resume = lnl_hda_dsp_resume;
150 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume;
153 /* dsp core get/put */
154 sof_lnl_ops.core_get = mtl_dsp_core_get;
155 sof_lnl_ops.core_put = mtl_dsp_core_put;
157 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
161 ipc4_data = sdev->private;
162 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
164 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
166 ipc4_data->fw_context_save = true;
168 /* External library loading support */
169 ipc4_data->load_library = hda_dsp_ipc4_load_library;
172 hda_set_dai_drv_ops(sdev, &sof_lnl_ops);
174 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
178 EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
180 /* Check if an SDW IRQ occurred */
181 static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
183 struct hdac_bus *bus = sof_to_bus(sdev);
185 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
188 static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
190 struct hdac_bus *bus = sof_to_bus(sdev);
192 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable);
195 static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
197 lnl_enable_sdw_irq(sdev, false);
198 mtl_disable_ipc_interrupts(sdev);
199 return mtl_enable_interrupts(sdev, false);
202 const struct sof_intel_dsp_desc lnl_chip_info = {
204 .init_core_mask = BIT(0),
205 .host_managed_cores_mask = BIT(0),
206 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
207 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
208 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
209 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
210 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
211 .rom_status_reg = MTL_DSP_ROM_STS,
212 .rom_init_timeout = 300,
213 .ssp_count = MTL_SSP_COUNT,
214 .d0i3_offset = MTL_HDA_VS_D0I3C,
215 .read_sdw_lcount = hda_sdw_check_lcount_ext,
216 .enable_sdw_irq = lnl_enable_sdw_irq,
217 .check_sdw_irq = lnl_dsp_check_sdw_irq,
218 .check_ipc_irq = mtl_dsp_check_ipc_irq,
219 .cl_init = mtl_dsp_cl_init,
220 .power_down_dsp = mtl_power_down_dsp,
221 .disable_interrupts = lnl_dsp_disable_interrupts,
222 .hw_ip_version = SOF_INTEL_ACE_2_0,
224 EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);