drivers/usb/dwc3/dwc3-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dwc3-pci.c - PCI Specific glue layer
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/acpi.h>
  21 #include <linux/delay.h>
  22
  23 #define PCI_DEVICE_ID_INTEL_BYT                 0x0f37
  24 #define PCI_DEVICE_ID_INTEL_MRFLD               0x119e
  25 #define PCI_DEVICE_ID_INTEL_BSW                 0x22b7
  26 #define PCI_DEVICE_ID_INTEL_SPTLP               0x9d30
  27 #define PCI_DEVICE_ID_INTEL_SPTH                0xa130
  28 #define PCI_DEVICE_ID_INTEL_BXT                 0x0aaa
  29 #define PCI_DEVICE_ID_INTEL_BXT_M               0x1aaa
  30 #define PCI_DEVICE_ID_INTEL_APL                 0x5aaa
  31 #define PCI_DEVICE_ID_INTEL_KBP                 0xa2b0
  32 #define PCI_DEVICE_ID_INTEL_CMLLP               0x02ee
  33 #define PCI_DEVICE_ID_INTEL_CMLH                0x06ee
  34 #define PCI_DEVICE_ID_INTEL_GLK                 0x31aa
  35 #define PCI_DEVICE_ID_INTEL_CNPLP               0x9dee
  36 #define PCI_DEVICE_ID_INTEL_CNPH                0xa36e
  37 #define PCI_DEVICE_ID_INTEL_CNPV                0xa3b0
  38 #define PCI_DEVICE_ID_INTEL_ICLLP               0x34ee
  39 #define PCI_DEVICE_ID_INTEL_EHL                 0x4b7e
  40 #define PCI_DEVICE_ID_INTEL_TGPLP               0xa0ee
  41 #define PCI_DEVICE_ID_INTEL_TGPH                0x43ee
  42 #define PCI_DEVICE_ID_INTEL_JSP                 0x4dee
  43 #define PCI_DEVICE_ID_INTEL_ADL                 0x460e
  44 #define PCI_DEVICE_ID_INTEL_ADL_PCH             0x51ee
  45 #define PCI_DEVICE_ID_INTEL_ADLN                0x465e
  46 #define PCI_DEVICE_ID_INTEL_ADLN_PCH            0x54ee
  47 #define PCI_DEVICE_ID_INTEL_ADLS                0x7ae1
  48 #define PCI_DEVICE_ID_INTEL_RPL                 0xa70e
  49 #define PCI_DEVICE_ID_INTEL_RPLS                0x7a61
  50 #define PCI_DEVICE_ID_INTEL_MTLM                0x7eb1
  51 #define PCI_DEVICE_ID_INTEL_MTLP                0x7ec1
  52 #define PCI_DEVICE_ID_INTEL_MTLS                0x7f6f
  53 #define PCI_DEVICE_ID_INTEL_MTL                 0x7e7e
  54 #define PCI_DEVICE_ID_INTEL_ARLH_PCH            0x777e
  55 #define PCI_DEVICE_ID_INTEL_TGL                 0x9a15
  56 #define PCI_DEVICE_ID_AMD_MR                    0x163a
  57
  58 #define PCI_INTEL_BXT_DSM_GUID          "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  59 #define PCI_INTEL_BXT_FUNC_PMU_PWR      4
  60 #define PCI_INTEL_BXT_STATE_D0          0
  61 #define PCI_INTEL_BXT_STATE_D3          3
  62
  63 #define GP_RWBAR                        1
  64 #define GP_RWREG1                       0xa0
  65 #define GP_RWREG1_ULPI_REFCLK_DISABLE   (1 << 17)
  66
  67 /**
  68  * struct dwc3_pci - Driver private structure
  69  * @dwc3: child dwc3 platform_device
  70  * @pci: our link to PCI bus
  71  * @guid: _DSM GUID
  72  * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  73  * @wakeup_work: work for asynchronous resume
  74  */
  75 struct dwc3_pci {
  76         struct platform_device *dwc3;
  77         struct pci_dev *pci;
  78
  79         guid_t guid;
  80
  81         unsigned int has_dsm_for_pm:1;
  82         struct work_struct wakeup_work;
  83 };
  84
  85 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  86 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  87
  88 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  89         { "reset-gpios", &reset_gpios, 1 },
  90         { "cs-gpios", &cs_gpios, 1 },
  91         { },
  92 };
  93
  94 static struct gpiod_lookup_table platform_bytcr_gpios = {
  95         .dev_id         = "0000:00:16.0",
  96         .table          = {
  97                 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
  98                 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
  99                 {}
 100         },
 101 };
 102
 103 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
 104 {
 105         void __iomem    *reg;
 106         u32             value;
 107
 108         reg = pcim_iomap(pci, GP_RWBAR, 0);
 109         if (!reg)
 110                 return -ENOMEM;
 111
 112         value = readl(reg + GP_RWREG1);
 113         if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
 114                 goto unmap; /* ULPI refclk already enabled */
 115
 116         value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
 117         writel(value, reg + GP_RWREG1);
 118         /* This comes from the Intel Android x86 tree w/o any explanation */
 119         msleep(100);
 120 unmap:
 121         pcim_iounmap(pci, reg);
 122         return 0;
 123 }
 124
 125 static const struct property_entry dwc3_pci_intel_properties[] = {
 126         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 127         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 128         {}
 129 };
 130
 131 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
 132         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 133         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 134         PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
 135         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 136         {}
 137 };
 138
 139 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
 140         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 141         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 142         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 143         {}
 144 };
 145
 146 static const struct property_entry dwc3_pci_mrfld_properties[] = {
 147         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 148         PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
 149         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 150         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 151         PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
 152         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 153         {}
 154 };
 155
 156 static const struct property_entry dwc3_pci_amd_properties[] = {
 157         PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
 158         PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
 159         PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
 160         PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
 161         PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
 162         PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
 163         PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
 164         PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
 165         PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
 166         PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
 167         PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
 168         /* FIXME these quirks should be removed when AMD NL tapes out */
 169         PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
 170         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 171         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 172         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 173         {}
 174 };
 175
 176 static const struct property_entry dwc3_pci_mr_properties[] = {
 177         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 178         PROPERTY_ENTRY_BOOL("usb-role-switch"),
 179         PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
 180         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 181         {}
 182 };
 183
 184 static const struct software_node dwc3_pci_intel_swnode = {
 185         .properties = dwc3_pci_intel_properties,
 186 };
 187
 188 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
 189         .properties = dwc3_pci_intel_phy_charger_detect_properties,
 190 };
 191
 192 static const struct software_node dwc3_pci_intel_byt_swnode = {
 193         .properties = dwc3_pci_intel_byt_properties,
 194 };
 195
 196 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
 197         .properties = dwc3_pci_mrfld_properties,
 198 };
 199
 200 static const struct software_node dwc3_pci_amd_swnode = {
 201         .properties = dwc3_pci_amd_properties,
 202 };
 203
 204 static const struct software_node dwc3_pci_amd_mr_swnode = {
 205         .properties = dwc3_pci_mr_properties,
 206 };
 207
 208 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
 209                            const struct software_node *swnode)
 210 {
 211         struct pci_dev                  *pdev = dwc->pci;
 212
 213         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 214                 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
 215                     pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
 216                     pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
 217                         guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
 218                         dwc->has_dsm_for_pm = true;
 219                 }
 220
 221                 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
 222                         struct gpio_desc *gpio;
 223                         int ret;
 224
 225                         /* On BYT the FW does not always enable the refclock */
 226                         ret = dwc3_byt_enable_ulpi_refclock(pdev);
 227                         if (ret)
 228                                 return ret;
 229
 230                         ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
 231                                         acpi_dwc3_byt_gpios);
 232                         if (ret)
 233                                 dev_dbg(&pdev->dev, "failed to add mapping table\n");
 234
 235                         /*
 236                          * A lot of BYT devices lack ACPI resource entries for
 237                          * the GPIOs. If the ACPI entry for the GPIO controller
 238                          * is present add a fallback mapping to the reference
 239                          * design GPIOs which all boards seem to use.
 240                          */
 241                         if (acpi_dev_present("INT33FC", NULL, -1))
 242                                 gpiod_add_lookup_table(&platform_bytcr_gpios);
 243
 244                         /*
 245                          * These GPIOs will turn on the USB2 PHY. Note that we have to
 246                          * put the gpio descriptors again here because the phy driver
 247                          * might want to grab them, too.
 248                          */
 249                         gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
 250                         if (IS_ERR(gpio))
 251                                 return PTR_ERR(gpio);
 252
 253                         gpiod_set_value_cansleep(gpio, 1);
 254                         gpiod_put(gpio);
 255
 256                         gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
 257                         if (IS_ERR(gpio))
 258                                 return PTR_ERR(gpio);
 259
 260                         if (gpio) {
 261                                 gpiod_set_value_cansleep(gpio, 1);
 262                                 gpiod_put(gpio);
 263                                 usleep_range(10000, 11000);
 264                         }
 265
 266                         /*
 267                          * Make the pdev name predictable (only 1 DWC3 on BYT)
 268                          * and patch the phy dev-name into the lookup table so
 269                          * that the phy-driver can get the GPIOs.
 270                          */
 271                         dwc->dwc3->id = PLATFORM_DEVID_NONE;
 272                         platform_bytcr_gpios.dev_id = "dwc3.ulpi";
 273
 274                         /*
 275                          * Some Android tablets with a Crystal Cove PMIC
 276                          * (INT33FD), rely on the TUSB1211 phy for charger
 277                          * detection. These can be identified by them _not_
 278                          * using the standard ACPI battery and ac drivers.
 279                          */
 280                         if (acpi_dev_present("INT33FD", "1", 2) &&
 281                             acpi_quirk_skip_acpi_ac_and_battery()) {
 282                                 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
 283                                 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
 284                         }
 285                 }
 286         }
 287
 288         return device_add_software_node(&dwc->dwc3->dev, swnode);
 289 }
 290
 291 #ifdef CONFIG_PM
 292 static void dwc3_pci_resume_work(struct work_struct *work)
 293 {
 294         struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
 295         struct platform_device *dwc3 = dwc->dwc3;
 296         int ret;
 297
 298         ret = pm_runtime_get_sync(&dwc3->dev);
 299         if (ret < 0) {
 300                 pm_runtime_put_sync_autosuspend(&dwc3->dev);
 301                 return;
 302         }
 303
 304         pm_runtime_mark_last_busy(&dwc3->dev);
 305         pm_runtime_put_sync_autosuspend(&dwc3->dev);
 306 }
 307 #endif
 308
 309 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
 310 {
 311         struct dwc3_pci         *dwc;
 312         struct resource         res[2];
 313         int                     ret;
 314         struct device           *dev = &pci->dev;
 315
 316         ret = pcim_enable_device(pci);
 317         if (ret) {
 318                 dev_err(dev, "failed to enable pci device\n");
 319                 return -ENODEV;
 320         }
 321
 322         pci_set_master(pci);
 323
 324         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 325         if (!dwc)
 326                 return -ENOMEM;
 327
 328         dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 329         if (!dwc->dwc3)
 330                 return -ENOMEM;
 331
 332         memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
 333
 334         res[0].start    = pci_resource_start(pci, 0);
 335         res[0].end      = pci_resource_end(pci, 0);
 336         res[0].name     = "dwc_usb3";
 337         res[0].flags    = IORESOURCE_MEM;
 338
 339         res[1].start    = pci->irq;
 340         res[1].name     = "dwc_usb3";
 341         res[1].flags    = IORESOURCE_IRQ;
 342
 343         ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
 344         if (ret) {
 345                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 346                 goto err;
 347         }
 348
 349         dwc->pci = pci;
 350         dwc->dwc3->dev.parent = dev;
 351         ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
 352
 353         ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
 354         if (ret)
 355                 goto err;
 356
 357         ret = platform_device_add(dwc->dwc3);
 358         if (ret) {
 359                 dev_err(dev, "failed to register dwc3 device\n");
 360                 goto err;
 361         }
 362
 363         device_init_wakeup(dev, true);
 364         pci_set_drvdata(pci, dwc);
 365         pm_runtime_put(dev);
 366 #ifdef CONFIG_PM
 367         INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
 368 #endif
 369
 370         return 0;
 371 err:
 372         device_remove_software_node(&dwc->dwc3->dev);
 373         platform_device_put(dwc->dwc3);
 374         return ret;
 375 }
 376
 377 static void dwc3_pci_remove(struct pci_dev *pci)
 378 {
 379         struct dwc3_pci         *dwc = pci_get_drvdata(pci);
 380         struct pci_dev          *pdev = dwc->pci;
 381
 382         if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
 383                 gpiod_remove_lookup_table(&platform_bytcr_gpios);
 384 #ifdef CONFIG_PM
 385         cancel_work_sync(&dwc->wakeup_work);
 386 #endif
 387         device_init_wakeup(&pci->dev, false);
 388         pm_runtime_get(&pci->dev);
 389         device_remove_software_node(&dwc->dwc3->dev);
 390         platform_device_unregister(dwc->dwc3);
 391 }
 392
 393 static const struct pci_device_id dwc3_pci_id_table[] = {
 394         { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) },
 395         { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) },
 396         { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) },
 397         { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) },
 398         { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) },
 399         { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) },
 400         { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) },
 401         { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) },
 402         { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) },
 403         { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) },
 404         { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) },
 405         { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) },
 406         { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) },
 407         { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) },
 408         { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) },
 409         { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) },
 410         { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) },
 411         { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) },
 412         { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) },
 413         { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) },
 414         { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) },
 415         { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) },
 416         { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) },
 417         { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) },
 418         { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) },
 419         { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) },
 420         { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) },
 421         { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) },
 422         { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) },
 423         { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) },
 424         { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) },
 425         { PCI_DEVICE_DATA(INTEL, ARLH_PCH, &dwc3_pci_intel_swnode) },
 426         { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
 427
 428         { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) },
 429         { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) },
 430
 431         {  }    /* Terminating Entry */
 432 };
 433 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
 434
 435 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
 436 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
 437 {
 438         union acpi_object *obj;
 439         union acpi_object tmp;
 440         union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
 441
 442         if (!dwc->has_dsm_for_pm)
 443                 return 0;
 444
 445         tmp.type = ACPI_TYPE_INTEGER;
 446         tmp.integer.value = param;
 447
 448         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
 449                         1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
 450         if (!obj) {
 451                 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
 452                 return -EIO;
 453         }
 454
 455         ACPI_FREE(obj);
 456
 457         return 0;
 458 }
 459 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
 460
 461 #ifdef CONFIG_PM
 462 static int dwc3_pci_runtime_suspend(struct device *dev)
 463 {
 464         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 465
 466         if (device_can_wakeup(dev))
 467                 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 468
 469         return -EBUSY;
 470 }
 471
 472 static int dwc3_pci_runtime_resume(struct device *dev)
 473 {
 474         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 475         int                     ret;
 476
 477         ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 478         if (ret)
 479                 return ret;
 480
 481         queue_work(pm_wq, &dwc->wakeup_work);
 482
 483         return 0;
 484 }
 485 #endif /* CONFIG_PM */
 486
 487 #ifdef CONFIG_PM_SLEEP
 488 static int dwc3_pci_suspend(struct device *dev)
 489 {
 490         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 491
 492         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 493 }
 494
 495 static int dwc3_pci_resume(struct device *dev)
 496 {
 497         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 498
 499         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 500 }
 501 #endif /* CONFIG_PM_SLEEP */
 502
 503 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
 504         SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
 505         SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
 506                 NULL)
 507 };
 508
 509 static struct pci_driver dwc3_pci_driver = {
 510         .name           = "dwc3-pci",
 511         .id_table       = dwc3_pci_id_table,
 512         .probe          = dwc3_pci_probe,
 513         .remove         = dwc3_pci_remove,
 514         .driver         = {
 515                 .pm     = &dwc3_pci_dev_pm_ops,
 516         }
 517 };
 518
 519 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 520 MODULE_LICENSE("GPL v2");
 521 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
 522
 523 module_pci_driver(dwc3_pci_driver);