1 // SPDX-License-Identifier: GPL-2.0
3 * USB4 specific functionality
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12 #include <linux/units.h>
17 #define USB4_DATA_RETRIES 3
18 #define USB4_DATA_DWORDS 16
21 USB4_SB_TARGET_ROUTER,
22 USB4_SB_TARGET_PARTNER,
23 USB4_SB_TARGET_RETIMER,
26 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
27 #define USB4_NVM_READ_OFFSET_SHIFT 2
28 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
29 #define USB4_NVM_READ_LENGTH_SHIFT 24
31 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
32 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
34 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
35 #define USB4_DROM_ADDRESS_SHIFT 2
36 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
37 #define USB4_DROM_SIZE_SHIFT 15
39 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
41 #define USB4_BA_LENGTH_MASK GENMASK(7, 0)
42 #define USB4_BA_INDEX_MASK GENMASK(15, 0)
45 USB4_BA_MAX_USB3 = 0x1,
46 USB4_BA_MIN_DP_AUX = 0x2,
47 USB4_BA_MIN_DP_MAIN = 0x3,
48 USB4_BA_MAX_PCIE = 0x4,
52 #define USB4_BA_VALUE_MASK GENMASK(31, 16)
53 #define USB4_BA_VALUE_SHIFT 16
55 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
56 u32 *metadata, u8 *status,
57 const void *tx_data, size_t tx_dwords,
58 void *rx_data, size_t rx_dwords)
64 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
69 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
75 val = opcode | ROUTER_CS_26_OV;
76 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
80 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
84 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
88 if (val & ROUTER_CS_26_ONS)
92 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
93 ROUTER_CS_26_STATUS_SHIFT;
96 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
101 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
110 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
111 u8 *status, const void *tx_data, size_t tx_dwords,
112 void *rx_data, size_t rx_dwords)
114 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
116 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
120 * If the connection manager implementation provides USB4 router
121 * operation proxy callback, call it here instead of running the
122 * operation natively.
124 if (cm_ops->usb4_switch_op) {
127 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
128 tx_data, tx_dwords, rx_data,
130 if (ret != -EOPNOTSUPP)
134 * If the proxy was not supported then run the native
135 * router operation instead.
139 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
140 tx_dwords, rx_data, rx_dwords);
143 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
144 u32 *metadata, u8 *status)
146 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
149 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
150 u32 *metadata, u8 *status,
151 const void *tx_data, size_t tx_dwords,
152 void *rx_data, size_t rx_dwords)
154 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
155 tx_dwords, rx_data, rx_dwords);
159 * usb4_switch_check_wakes() - Check for wakes and notify PM core about them
160 * @sw: Router whose wakes to check
162 * Checks wakes occurred during suspend and notify the PM core about them.
164 void usb4_switch_check_wakes(struct tb_switch *sw)
166 bool wakeup_usb4 = false;
167 struct usb4_port *usb4;
168 struct tb_port *port;
173 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
176 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
177 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
178 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
180 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
184 * Check for any downstream ports for USB4 wake,
185 * connection wake and disconnection wake.
187 tb_switch_for_each_port(sw, port) {
191 if (tb_port_read(port, &val, TB_CFG_PORT,
192 port->cap_usb4 + PORT_CS_18, 1))
195 tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
196 (val & PORT_CS_18_WOU4S) ? "yes" : "no",
197 (val & PORT_CS_18_WOCS) ? "yes" : "no",
198 (val & PORT_CS_18_WODS) ? "yes" : "no");
200 wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
204 if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
205 pm_wakeup_event(&usb4->dev, 0);
207 wakeup |= wakeup_usb4;
211 pm_wakeup_event(&sw->dev, 0);
214 static bool link_is_usb4(struct tb_port *port)
221 if (tb_port_read(port, &val, TB_CFG_PORT,
222 port->cap_usb4 + PORT_CS_18, 1))
225 return !(val & PORT_CS_18_TCM);
229 * usb4_switch_setup() - Additional setup for USB4 device
230 * @sw: USB4 router to setup
232 * USB4 routers need additional settings in order to enable all the
233 * tunneling. This function enables USB and PCIe tunneling if it can be
234 * enabled (e.g the parent switch also supports them). If USB tunneling
235 * is not available for some reason (like that there is Thunderbolt 3
236 * switch upstream) then the internal xHCI controller is enabled
239 * This does not set the configuration valid bit of the router. To do
240 * that call usb4_switch_configuration_valid().
242 int usb4_switch_setup(struct tb_switch *sw)
244 struct tb_switch *parent = tb_switch_parent(sw);
245 struct tb_port *down;
253 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
257 down = tb_switch_downstream_port(sw);
258 sw->link_usb4 = link_is_usb4(down);
259 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
261 xhci = val & ROUTER_CS_6_HCI;
262 tbt3 = !(val & ROUTER_CS_6_TNS);
264 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
265 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
267 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
271 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
272 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
273 val |= ROUTER_CS_5_UTO;
278 * Only enable PCIe tunneling if the parent router supports it
279 * and it is not disabled.
281 if (tb_acpi_may_tunnel_pcie() &&
282 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
283 val |= ROUTER_CS_5_PTO;
285 * xHCI can be enabled if PCIe tunneling is supported
286 * and the parent does not have any USB3 dowstream
287 * adapters (so we cannot do USB 3.x tunneling).
290 val |= ROUTER_CS_5_HCO;
293 /* TBT3 supported by the CM */
294 val &= ~ROUTER_CS_5_CNS;
296 return tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
300 * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
303 * Sets configuration valid bit for the router. Must be called before
304 * any tunnels can be set through the router and after
305 * usb4_switch_setup() has been called. Can be called to host and device
306 * routers (does nothing for the latter).
308 * Returns %0 in success and negative errno otherwise.
310 int usb4_switch_configuration_valid(struct tb_switch *sw)
318 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
322 val |= ROUTER_CS_5_CV;
324 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
328 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
333 * usb4_switch_read_uid() - Read UID from USB4 router
335 * @uid: UID is stored here
337 * Reads 64-bit UID from USB4 router config space.
339 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
341 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
344 static int usb4_switch_drom_read_block(void *data,
345 unsigned int dwaddress, void *buf,
348 struct tb_switch *sw = data;
353 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
354 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
355 USB4_DROM_ADDRESS_MASK;
357 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
358 &status, NULL, 0, buf, dwords);
362 return status ? -EIO : 0;
366 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
368 * @address: Byte address inside DROM to start reading
369 * @buf: Buffer where the DROM content is stored
370 * @size: Number of bytes to read from DROM
372 * Uses USB4 router operations to read router DROM. For devices this
373 * should always work but for hosts it may return %-EOPNOTSUPP in which
374 * case the host router does not have DROM.
376 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
379 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
380 usb4_switch_drom_read_block, sw);
384 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
387 * Checks whether conditions are met so that lane bonding can be
388 * established with the upstream router. Call only for device routers.
390 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
396 up = tb_upstream_port(sw);
397 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
401 return !!(val & PORT_CS_18_BE);
405 * usb4_switch_set_wake() - Enabled/disable wake
407 * @flags: Wakeup flags (%0 to disable)
409 * Enables/disables router to wake up from sleep.
411 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
413 struct usb4_port *usb4;
414 struct tb_port *port;
415 u64 route = tb_route(sw);
420 * Enable wakes coming from all USB4 downstream ports (from
421 * child routers). For device routers do this also for the
422 * upstream USB4 port.
424 tb_switch_for_each_port(sw, port) {
425 if (!tb_port_is_null(port))
427 if (!route && tb_is_upstream_port(port))
432 ret = tb_port_read(port, &val, TB_CFG_PORT,
433 port->cap_usb4 + PORT_CS_19, 1);
437 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
439 if (tb_is_upstream_port(port)) {
440 val |= PORT_CS_19_WOU4;
442 bool configured = val & PORT_CS_19_PC;
445 if (((flags & TB_WAKE_ON_CONNECT) |
446 device_may_wakeup(&usb4->dev)) && !configured)
447 val |= PORT_CS_19_WOC;
448 if (((flags & TB_WAKE_ON_DISCONNECT) |
449 device_may_wakeup(&usb4->dev)) && configured)
450 val |= PORT_CS_19_WOD;
451 if ((flags & TB_WAKE_ON_USB4) && configured)
452 val |= PORT_CS_19_WOU4;
455 ret = tb_port_write(port, &val, TB_CFG_PORT,
456 port->cap_usb4 + PORT_CS_19, 1);
462 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
463 * needed for device routers.
466 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
470 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
471 if (flags & TB_WAKE_ON_USB3)
472 val |= ROUTER_CS_5_WOU;
473 if (flags & TB_WAKE_ON_PCIE)
474 val |= ROUTER_CS_5_WOP;
475 if (flags & TB_WAKE_ON_DP)
476 val |= ROUTER_CS_5_WOD;
478 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
487 * usb4_switch_set_sleep() - Prepare the router to enter sleep
490 * Sets sleep bit for the router. Returns when the router sleep ready
491 * bit has been asserted.
493 int usb4_switch_set_sleep(struct tb_switch *sw)
498 /* Set sleep bit and wait for sleep ready to be asserted */
499 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
503 val |= ROUTER_CS_5_SLP;
505 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
509 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
510 ROUTER_CS_6_SLPR, 500);
514 * usb4_switch_nvm_sector_size() - Return router NVM sector size
517 * If the router supports NVM operations this function returns the NVM
518 * sector size in bytes. If NVM operations are not supported returns
521 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
527 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
533 return status == 0x2 ? -EOPNOTSUPP : -EIO;
535 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
538 static int usb4_switch_nvm_read_block(void *data,
539 unsigned int dwaddress, void *buf, size_t dwords)
541 struct tb_switch *sw = data;
546 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
547 USB4_NVM_READ_LENGTH_MASK;
548 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
549 USB4_NVM_READ_OFFSET_MASK;
551 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
552 &status, NULL, 0, buf, dwords);
556 return status ? -EIO : 0;
560 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
562 * @address: Starting address in bytes
563 * @buf: Read data is placed here
564 * @size: How many bytes to read
566 * Reads NVM contents of the router. If NVM is not supported returns
569 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
572 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
573 usb4_switch_nvm_read_block, sw);
577 * usb4_switch_nvm_set_offset() - Set NVM write offset
579 * @address: Start offset
581 * Explicitly sets NVM write offset. Normally when writing to NVM this
582 * is done automatically by usb4_switch_nvm_write().
584 * Returns %0 in success and negative errno if there was a failure.
586 int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
588 u32 metadata, dwaddress;
592 dwaddress = address / 4;
593 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
594 USB4_NVM_SET_OFFSET_MASK;
596 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
601 return status ? -EIO : 0;
604 static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
605 const void *buf, size_t dwords)
607 struct tb_switch *sw = data;
611 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
612 buf, dwords, NULL, 0);
616 return status ? -EIO : 0;
620 * usb4_switch_nvm_write() - Write to the router NVM
622 * @address: Start address where to write in bytes
623 * @buf: Pointer to the data to write
624 * @size: Size of @buf in bytes
626 * Writes @buf to the router NVM using USB4 router operations. If NVM
627 * write is not supported returns %-EOPNOTSUPP.
629 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
630 const void *buf, size_t size)
634 ret = usb4_switch_nvm_set_offset(sw, address);
638 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
639 usb4_switch_nvm_write_next_block, sw);
643 * usb4_switch_nvm_authenticate() - Authenticate new NVM
646 * After the new NVM has been written via usb4_switch_nvm_write(), this
647 * function triggers NVM authentication process. The router gets power
648 * cycled and if the authentication is successful the new NVM starts
649 * running. In case of failure returns negative errno.
651 * The caller should call usb4_switch_nvm_authenticate_status() to read
652 * the status of the authentication after power cycle. It should be the
653 * first router operation to avoid the status being lost.
655 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
659 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
662 * The router is power cycled once NVM_AUTH is started so it is
663 * expected to get any of the following errors back.
676 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
678 * @status: Status code of the operation
680 * The function checks if there is status available from the last NVM
681 * authenticate router operation. If there is status then %0 is returned
682 * and the status code is placed in @status. Returns negative errno in case
685 * Must be called before any other router operation.
687 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
689 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
694 if (cm_ops->usb4_switch_nvm_authenticate_status) {
695 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
696 if (ret != -EOPNOTSUPP)
700 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
704 /* Check that the opcode is correct */
705 opcode = val & ROUTER_CS_26_OPCODE_MASK;
706 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
707 if (val & ROUTER_CS_26_OV)
709 if (val & ROUTER_CS_26_ONS)
712 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
713 ROUTER_CS_26_STATUS_SHIFT;
722 * usb4_switch_credits_init() - Read buffer allocation parameters
725 * Reads @sw buffer allocation parameters and initializes @sw buffer
726 * allocation fields accordingly. Specifically @sw->credits_allocation
727 * is set to %true if these parameters can be used in tunneling.
729 * Returns %0 on success and negative errno otherwise.
731 int usb4_switch_credits_init(struct tb_switch *sw)
733 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
734 int ret, length, i, nports;
735 const struct tb_port *port;
736 u32 data[USB4_DATA_DWORDS];
740 memset(data, 0, sizeof(data));
741 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
742 &status, NULL, 0, data, ARRAY_SIZE(data));
748 length = metadata & USB4_BA_LENGTH_MASK;
749 if (WARN_ON(length > ARRAY_SIZE(data)))
758 tb_sw_dbg(sw, "credit allocation parameters:\n");
760 for (i = 0; i < length; i++) {
763 index = data[i] & USB4_BA_INDEX_MASK;
764 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
767 case USB4_BA_MAX_USB3:
768 tb_sw_dbg(sw, " USB3: %u\n", value);
771 case USB4_BA_MIN_DP_AUX:
772 tb_sw_dbg(sw, " DP AUX: %u\n", value);
775 case USB4_BA_MIN_DP_MAIN:
776 tb_sw_dbg(sw, " DP main: %u\n", value);
779 case USB4_BA_MAX_PCIE:
780 tb_sw_dbg(sw, " PCIe: %u\n", value);
784 tb_sw_dbg(sw, " DMA: %u\n", value);
788 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
795 * Validate the buffer allocation preferences. If we find
796 * issues, log a warning and fall back using the hard-coded
800 /* Host router must report baMaxHI */
801 if (!tb_route(sw) && max_dma < 0) {
802 tb_sw_warn(sw, "host router is missing baMaxHI\n");
807 tb_switch_for_each_port(sw, port) {
808 if (tb_port_is_null(port))
812 /* Must have DP buffer allocation (multiple USB4 ports) */
813 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
814 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
818 tb_switch_for_each_port(sw, port) {
819 if (tb_port_is_dpout(port) && min_dp_main < 0) {
820 tb_sw_warn(sw, "missing baMinDPmain");
823 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
825 tb_sw_warn(sw, "missing baMinDPaux");
828 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
830 tb_sw_warn(sw, "missing baMaxUSB3");
833 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
835 tb_sw_warn(sw, "missing baMaxPCIe");
841 * Buffer allocation passed the validation so we can use it in
844 sw->credit_allocation = true;
846 sw->max_usb3_credits = max_usb3;
848 sw->min_dp_aux_credits = min_dp_aux;
850 sw->min_dp_main_credits = min_dp_main;
852 sw->max_pcie_credits = max_pcie;
854 sw->max_dma_credits = max_dma;
863 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
867 * For DP tunneling this function can be used to query availability of
868 * DP IN resource. Returns true if the resource is available for DP
869 * tunneling, false otherwise.
871 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
873 u32 metadata = in->port;
877 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
880 * If DP resource allocation is not supported assume it is
883 if (ret == -EOPNOTSUPP)
892 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
896 * Allocates DP IN resource for DP tunneling using USB4 router
897 * operations. If the resource was allocated returns %0. Otherwise
898 * returns negative errno, in particular %-EBUSY if the resource is
901 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
903 u32 metadata = in->port;
907 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
909 if (ret == -EOPNOTSUPP)
914 return status ? -EBUSY : 0;
918 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
922 * Releases the previously allocated DP IN resource.
924 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
926 u32 metadata = in->port;
930 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
932 if (ret == -EOPNOTSUPP)
937 return status ? -EIO : 0;
940 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
945 /* Assume port is primary */
946 tb_switch_for_each_port(sw, p) {
947 if (!tb_port_is_null(p))
949 if (tb_is_upstream_port(p))
962 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
966 * USB4 routers have direct mapping between USB4 ports and PCIe
967 * downstream adapters where the PCIe topology is extended. This
968 * function returns the corresponding downstream PCIe adapter or %NULL
969 * if no such mapping was possible.
971 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
972 const struct tb_port *port)
974 int usb4_idx = usb4_port_idx(sw, port);
978 /* Find PCIe down port matching usb4_port */
979 tb_switch_for_each_port(sw, p) {
980 if (!tb_port_is_pcie_down(p))
983 if (pcie_idx == usb4_idx)
993 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
997 * USB4 routers have direct mapping between USB4 ports and USB 3.x
998 * downstream adapters where the USB 3.x topology is extended. This
999 * function returns the corresponding downstream USB 3.x adapter or
1000 * %NULL if no such mapping was possible.
1002 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1003 const struct tb_port *port)
1005 int usb4_idx = usb4_port_idx(sw, port);
1009 /* Find USB3 down port matching usb4_port */
1010 tb_switch_for_each_port(sw, p) {
1011 if (!tb_port_is_usb3_down(p))
1014 if (usb_idx == usb4_idx)
1024 * usb4_switch_add_ports() - Add USB4 ports for this router
1027 * For USB4 router finds all USB4 ports and registers devices for each.
1028 * Can be called to any router.
1030 * Return %0 in case of success and negative errno in case of failure.
1032 int usb4_switch_add_ports(struct tb_switch *sw)
1034 struct tb_port *port;
1036 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1039 tb_switch_for_each_port(sw, port) {
1040 struct usb4_port *usb4;
1042 if (!tb_port_is_null(port))
1044 if (!port->cap_usb4)
1047 usb4 = usb4_port_device_add(port);
1049 usb4_switch_remove_ports(sw);
1050 return PTR_ERR(usb4);
1060 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1063 * Unregisters previously registered USB4 ports.
1065 void usb4_switch_remove_ports(struct tb_switch *sw)
1067 struct tb_port *port;
1069 tb_switch_for_each_port(sw, port) {
1071 usb4_port_device_remove(port->usb4);
1078 * usb4_port_unlock() - Unlock USB4 downstream port
1079 * @port: USB4 port to unlock
1081 * Unlocks USB4 downstream port so that the connection manager can
1082 * access the router below this port.
1084 int usb4_port_unlock(struct tb_port *port)
1089 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1093 val &= ~ADP_CS_4_LCK;
1094 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1098 * usb4_port_hotplug_enable() - Enables hotplug for a port
1099 * @port: USB4 port to operate on
1101 * Enables hot plug events on a given port. This is only intended
1102 * to be used on lane, DP-IN, and DP-OUT adapters.
1104 int usb4_port_hotplug_enable(struct tb_port *port)
1109 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1113 val &= ~ADP_CS_5_DHP;
1114 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1118 * usb4_port_reset() - Issue downstream port reset
1119 * @port: USB4 port to reset
1121 * Issues downstream port reset to @port.
1123 int usb4_port_reset(struct tb_port *port)
1128 if (!port->cap_usb4)
1131 ret = tb_port_read(port, &val, TB_CFG_PORT,
1132 port->cap_usb4 + PORT_CS_19, 1);
1136 val |= PORT_CS_19_DPR;
1138 ret = tb_port_write(port, &val, TB_CFG_PORT,
1139 port->cap_usb4 + PORT_CS_19, 1);
1145 ret = tb_port_read(port, &val, TB_CFG_PORT,
1146 port->cap_usb4 + PORT_CS_19, 1);
1150 val &= ~PORT_CS_19_DPR;
1152 return tb_port_write(port, &val, TB_CFG_PORT,
1153 port->cap_usb4 + PORT_CS_19, 1);
1156 static int usb4_port_set_configured(struct tb_port *port, bool configured)
1161 if (!port->cap_usb4)
1164 ret = tb_port_read(port, &val, TB_CFG_PORT,
1165 port->cap_usb4 + PORT_CS_19, 1);
1170 val |= PORT_CS_19_PC;
1172 val &= ~PORT_CS_19_PC;
1174 return tb_port_write(port, &val, TB_CFG_PORT,
1175 port->cap_usb4 + PORT_CS_19, 1);
1179 * usb4_port_configure() - Set USB4 port configured
1180 * @port: USB4 router
1182 * Sets the USB4 link to be configured for power management purposes.
1184 int usb4_port_configure(struct tb_port *port)
1186 return usb4_port_set_configured(port, true);
1190 * usb4_port_unconfigure() - Set USB4 port unconfigured
1191 * @port: USB4 router
1193 * Sets the USB4 link to be unconfigured for power management purposes.
1195 void usb4_port_unconfigure(struct tb_port *port)
1197 usb4_port_set_configured(port, false);
1200 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1205 if (!port->cap_usb4)
1208 ret = tb_port_read(port, &val, TB_CFG_PORT,
1209 port->cap_usb4 + PORT_CS_19, 1);
1214 val |= PORT_CS_19_PID;
1216 val &= ~PORT_CS_19_PID;
1218 return tb_port_write(port, &val, TB_CFG_PORT,
1219 port->cap_usb4 + PORT_CS_19, 1);
1223 * usb4_port_configure_xdomain() - Configure port for XDomain
1224 * @port: USB4 port connected to another host
1225 * @xd: XDomain that is connected to the port
1227 * Marks the USB4 port as being connected to another host and updates
1228 * the link type. Returns %0 in success and negative errno in failure.
1230 int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1232 xd->link_usb4 = link_is_usb4(port);
1233 return usb4_set_xdomain_configured(port, true);
1237 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1238 * @port: USB4 port that was connected to another host
1240 * Clears USB4 port from being marked as XDomain.
1242 void usb4_port_unconfigure_xdomain(struct tb_port *port)
1244 usb4_set_xdomain_configured(port, false);
1247 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1248 u32 value, int timeout_msec)
1250 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1256 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1260 if ((val & bit) == value)
1263 usleep_range(50, 100);
1264 } while (ktime_before(ktime_get(), timeout));
1269 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1271 if (dwords > USB4_DATA_DWORDS)
1274 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1278 static int usb4_port_write_data(struct tb_port *port, const void *data,
1281 if (dwords > USB4_DATA_DWORDS)
1284 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1288 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
1289 u8 index, u8 reg, void *buf, u8 size)
1291 size_t dwords = DIV_ROUND_UP(size, 4);
1295 if (!port->cap_usb4)
1299 val |= size << PORT_CS_1_LENGTH_SHIFT;
1300 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1301 if (target == USB4_SB_TARGET_RETIMER)
1302 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1303 val |= PORT_CS_1_PND;
1305 ret = tb_port_write(port, &val, TB_CFG_PORT,
1306 port->cap_usb4 + PORT_CS_1, 1);
1310 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1311 PORT_CS_1_PND, 0, 500);
1315 ret = tb_port_read(port, &val, TB_CFG_PORT,
1316 port->cap_usb4 + PORT_CS_1, 1);
1320 if (val & PORT_CS_1_NR)
1322 if (val & PORT_CS_1_RC)
1325 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1328 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1329 u8 index, u8 reg, const void *buf, u8 size)
1331 size_t dwords = DIV_ROUND_UP(size, 4);
1335 if (!port->cap_usb4)
1339 ret = usb4_port_write_data(port, buf, dwords);
1345 val |= size << PORT_CS_1_LENGTH_SHIFT;
1346 val |= PORT_CS_1_WNR_WRITE;
1347 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1348 if (target == USB4_SB_TARGET_RETIMER)
1349 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1350 val |= PORT_CS_1_PND;
1352 ret = tb_port_write(port, &val, TB_CFG_PORT,
1353 port->cap_usb4 + PORT_CS_1, 1);
1357 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1358 PORT_CS_1_PND, 0, 500);
1362 ret = tb_port_read(port, &val, TB_CFG_PORT,
1363 port->cap_usb4 + PORT_CS_1, 1);
1367 if (val & PORT_CS_1_NR)
1369 if (val & PORT_CS_1_RC)
1375 static int usb4_port_sb_opcode_err_to_errno(u32 val)
1380 case USB4_SB_OPCODE_ERR:
1382 case USB4_SB_OPCODE_ONS:
1389 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1390 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1397 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1402 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1406 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1412 return usb4_port_sb_opcode_err_to_errno(val);
1413 } while (ktime_before(ktime_get(), timeout));
1418 static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1423 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1424 USB4_SB_METADATA, &val, sizeof(val));
1428 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1429 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1430 USB4_SB_OPCODE, &val, sizeof(val));
1434 * usb4_port_router_offline() - Put the USB4 port to offline mode
1437 * This function puts the USB4 port into offline mode. In this mode the
1438 * port does not react on hotplug events anymore. This needs to be
1439 * called before retimer access is done when the USB4 links is not up.
1441 * Returns %0 in case of success and negative errno if there was an
1444 int usb4_port_router_offline(struct tb_port *port)
1446 return usb4_port_set_router_offline(port, true);
1450 * usb4_port_router_online() - Put the USB4 port back to online
1453 * Makes the USB4 port functional again.
1455 int usb4_port_router_online(struct tb_port *port)
1457 return usb4_port_set_router_offline(port, false);
1461 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1464 * This forces the USB4 port to send broadcast RT transaction which
1465 * makes the retimers on the link to assign index to themselves. Returns
1466 * %0 in case of success and negative errno if there was an error.
1468 int usb4_port_enumerate_retimers(struct tb_port *port)
1472 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1473 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1474 USB4_SB_OPCODE, &val, sizeof(val));
1478 * usb4_port_clx_supported() - Check if CLx is supported by the link
1479 * @port: Port to check for CLx support for
1481 * PORT_CS_18_CPS bit reflects if the link supports CLx including
1482 * active cables (if connected on the link).
1484 bool usb4_port_clx_supported(struct tb_port *port)
1489 ret = tb_port_read(port, &val, TB_CFG_PORT,
1490 port->cap_usb4 + PORT_CS_18, 1);
1494 return !!(val & PORT_CS_18_CPS);
1498 * usb4_port_asym_supported() - If the port supports asymmetric link
1501 * Checks if the port and the cable supports asymmetric link and returns
1502 * %true in that case.
1504 bool usb4_port_asym_supported(struct tb_port *port)
1508 if (!port->cap_usb4)
1511 if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
1514 return !!(val & PORT_CS_18_CSA);
1518 * usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1520 * @width: Asymmetric width to configure
1522 * Sets USB4 port link width to @width. Can be called for widths where
1523 * usb4_port_asym_width_supported() returned @true.
1525 int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1533 ret = tb_port_read(port, &val, TB_CFG_PORT,
1534 port->cap_phy + LANE_ADP_CS_1, 1);
1538 val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1540 case TB_LINK_WIDTH_DUAL:
1541 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1542 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1544 case TB_LINK_WIDTH_ASYM_TX:
1545 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1546 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1548 case TB_LINK_WIDTH_ASYM_RX:
1549 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1550 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1556 return tb_port_write(port, &val, TB_CFG_PORT,
1557 port->cap_phy + LANE_ADP_CS_1, 1);
1561 * usb4_port_asym_start() - Start symmetry change and wait for completion
1564 * Start symmetry change of the link to asymmetric or symmetric
1565 * (according to what was previously set in tb_port_set_link_width().
1566 * Wait for completion of the change.
1568 * Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
1569 * a negative errno in case of a failure.
1571 int usb4_port_asym_start(struct tb_port *port)
1576 ret = tb_port_read(port, &val, TB_CFG_PORT,
1577 port->cap_usb4 + PORT_CS_19, 1);
1581 val &= ~PORT_CS_19_START_ASYM;
1582 val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1584 ret = tb_port_write(port, &val, TB_CFG_PORT,
1585 port->cap_usb4 + PORT_CS_19, 1);
1590 * Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1591 * port started the symmetry transition.
1593 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
1594 PORT_CS_19_START_ASYM, 0, 1000);
1598 /* Then wait for the transtion to be completed */
1599 return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
1600 PORT_CS_18_TIP, 0, 5000);
1604 * usb4_port_margining_caps() - Read USB4 port marginig capabilities
1606 * @caps: Array with at least two elements to hold the results
1608 * Reads the USB4 port lane margining capabilities into @caps.
1610 int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
1614 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1615 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1619 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1620 USB4_SB_DATA, caps, sizeof(*caps) * 2);
1624 * usb4_port_hw_margin() - Run hardware lane margining on port
1626 * @lanes: Which lanes to run (must match the port capabilities). Can be
1628 * @ber_level: BER level contour value
1629 * @timing: Perform timing margining instead of voltage
1630 * @right_high: Use Right/high margin instead of left/low
1631 * @results: Array with at least two elements to hold the results
1633 * Runs hardware lane margining on USB4 port and returns the result in
1636 int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
1637 unsigned int ber_level, bool timing, bool right_high,
1645 val |= USB4_MARGIN_HW_TIME;
1647 val |= USB4_MARGIN_HW_RH;
1649 val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
1650 USB4_MARGIN_HW_BER_MASK;
1652 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1653 USB4_SB_METADATA, &val, sizeof(val));
1657 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1658 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1662 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1663 USB4_SB_DATA, results, sizeof(*results) * 2);
1667 * usb4_port_sw_margin() - Run software lane margining on port
1669 * @lanes: Which lanes to run (must match the port capabilities). Can be
1671 * @timing: Perform timing margining instead of voltage
1672 * @right_high: Use Right/high margin instead of left/low
1673 * @counter: What to do with the error counter
1675 * Runs software lane margining on USB4 port. Read back the error
1676 * counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1677 * success and negative errno otherwise.
1679 int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
1680 bool right_high, u32 counter)
1687 val |= USB4_MARGIN_SW_TIME;
1689 val |= USB4_MARGIN_SW_RH;
1690 val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
1691 USB4_MARGIN_SW_COUNTER_MASK;
1693 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1694 USB4_SB_METADATA, &val, sizeof(val));
1698 return usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1699 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1703 * usb4_port_sw_margin_errors() - Read the software margining error counters
1705 * @errors: Error metadata is copied here.
1707 * This reads back the software margining error counters from the port.
1708 * Returns %0 in success and negative errno otherwise.
1710 int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors)
1714 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1715 USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1719 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1720 USB4_SB_METADATA, errors, sizeof(*errors));
1723 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1724 enum usb4_sb_opcode opcode,
1727 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1732 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1734 * @index: Retimer index
1736 * Enables sideband channel transations on SBTX. Can be used when USB4
1737 * link does not go up, for example if there is no device connected.
1739 int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1743 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1750 * Per the USB4 retimer spec, the retimer is not required to
1751 * send an RT (Retimer Transaction) response for the first
1752 * SET_INBOUND_SBTX command
1754 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1759 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1761 * @index: Retimer index
1763 * Disables sideband channel transations on SBTX. The reverse of
1764 * usb4_port_retimer_set_inbound_sbtx().
1766 int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1768 return usb4_port_retimer_op(port, index,
1769 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1773 * usb4_port_retimer_read() - Read from retimer sideband registers
1775 * @index: Retimer index
1776 * @reg: Sideband register to read
1777 * @buf: Data from @reg is stored here
1778 * @size: Number of bytes to read
1780 * Function reads retimer sideband registers starting from @reg. The
1781 * retimer is connected to @port at @index. Returns %0 in case of
1782 * success, and read data is copied to @buf. If there is no retimer
1783 * present at given @index returns %-ENODEV. In any other failure
1784 * returns negative errno.
1786 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1789 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1794 * usb4_port_retimer_write() - Write to retimer sideband registers
1796 * @index: Retimer index
1797 * @reg: Sideband register to write
1798 * @buf: Data that is written starting from @reg
1799 * @size: Number of bytes to write
1801 * Writes retimer sideband registers starting from @reg. The retimer is
1802 * connected to @port at @index. Returns %0 in case of success. If there
1803 * is no retimer present at given @index returns %-ENODEV. In any other
1804 * failure returns negative errno.
1806 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1807 const void *buf, u8 size)
1809 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1814 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1816 * @index: Retimer index
1818 * If the retimer at @index is last one (connected directly to the
1819 * Type-C port) this function returns %1. If it is not returns %0. If
1820 * the retimer is not present returns %-ENODEV. Otherwise returns
1823 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1828 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1833 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1835 return ret ? ret : metadata & 1;
1839 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1841 * @index: Retimer index
1843 * Reads NVM sector size (in bytes) of a retimer at @index. This
1844 * operation can be used to determine whether the retimer supports NVM
1845 * upgrade for example. Returns sector size in bytes or negative errno
1846 * in case of error. Specifically returns %-ENODEV if there is no
1847 * retimer at @index.
1849 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1854 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1859 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1861 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1865 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1867 * @index: Retimer index
1868 * @address: Start offset
1870 * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1871 * done automatically by usb4_port_retimer_nvm_write().
1873 * Returns %0 in success and negative errno if there was a failure.
1875 int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1876 unsigned int address)
1878 u32 metadata, dwaddress;
1881 dwaddress = address / 4;
1882 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1883 USB4_NVM_SET_OFFSET_MASK;
1885 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1890 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1894 struct retimer_info {
1895 struct tb_port *port;
1899 static int usb4_port_retimer_nvm_write_next_block(void *data,
1900 unsigned int dwaddress, const void *buf, size_t dwords)
1903 const struct retimer_info *info = data;
1904 struct tb_port *port = info->port;
1905 u8 index = info->index;
1908 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1913 return usb4_port_retimer_op(port, index,
1914 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1918 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1920 * @index: Retimer index
1921 * @address: Byte address where to start the write
1922 * @buf: Data to write
1923 * @size: Size in bytes how much to write
1925 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1926 * upgrade. Returns %0 if the data was written successfully and negative
1927 * errno in case of failure. Specifically returns %-ENODEV if there is
1928 * no retimer at @index.
1930 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1931 const void *buf, size_t size)
1933 struct retimer_info info = { .port = port, .index = index };
1936 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1940 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1941 usb4_port_retimer_nvm_write_next_block, &info);
1945 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1947 * @index: Retimer index
1949 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1950 * this function can be used to trigger the NVM upgrade process. If
1951 * successful the retimer restarts with the new NVM and may not have the
1952 * index set so one needs to call usb4_port_enumerate_retimers() to
1953 * force index to be assigned.
1955 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1960 * We need to use the raw operation here because once the
1961 * authentication completes the retimer index is not set anymore
1962 * so we do not get back the status now.
1964 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1965 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1966 USB4_SB_OPCODE, &val, sizeof(val));
1970 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1972 * @index: Retimer index
1973 * @status: Raw status code read from metadata
1975 * This can be called after usb4_port_retimer_nvm_authenticate() and
1976 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1978 * Returns %0 if the authentication status was successfully read. The
1979 * completion metadata (the result) is then stored into @status. If
1980 * reading the status fails, returns negative errno.
1982 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1988 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1993 ret = usb4_port_sb_opcode_err_to_errno(val);
2000 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
2001 &metadata, sizeof(metadata));
2005 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
2013 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
2014 void *buf, size_t dwords)
2016 const struct retimer_info *info = data;
2017 struct tb_port *port = info->port;
2018 u8 index = info->index;
2022 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
2023 if (dwords < USB4_DATA_DWORDS)
2024 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
2026 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
2031 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
2035 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
2040 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2042 * @index: Retimer index
2043 * @address: NVM address (in bytes) to start reading
2044 * @buf: Data read from NVM is stored here
2045 * @size: Number of bytes to read
2047 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
2048 * read was successful and negative errno in case of failure.
2049 * Specifically returns %-ENODEV if there is no retimer at @index.
2051 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2052 unsigned int address, void *buf, size_t size)
2054 struct retimer_info info = { .port = port, .index = index };
2056 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2057 usb4_port_retimer_nvm_read_block, &info);
2060 static inline unsigned int
2061 usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2063 /* Take the possible bandwidth limitation into account */
2065 return min(bw, port->max_bw);
2070 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
2071 * @port: USB3 adapter port
2073 * Return maximum supported link rate of a USB3 adapter in Mb/s.
2074 * Negative errno in case of error.
2076 int usb4_usb3_port_max_link_rate(struct tb_port *port)
2081 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2084 ret = tb_port_read(port, &val, TB_CFG_PORT,
2085 port->cap_adap + ADP_USB3_CS_4, 1);
2089 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2090 ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2092 return usb4_usb3_port_max_bandwidth(port, ret);
2095 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2100 if (!tb_port_is_usb3_down(port))
2102 if (tb_route(port->sw))
2105 ret = tb_port_read(port, &val, TB_CFG_PORT,
2106 port->cap_adap + ADP_USB3_CS_2, 1);
2111 val |= ADP_USB3_CS_2_CMR;
2113 val &= ~ADP_USB3_CS_2_CMR;
2115 ret = tb_port_write(port, &val, TB_CFG_PORT,
2116 port->cap_adap + ADP_USB3_CS_2, 1);
2121 * We can use val here directly as the CMR bit is in the same place
2122 * as HCA. Just mask out others.
2124 val &= ADP_USB3_CS_2_CMR;
2125 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2126 ADP_USB3_CS_1_HCA, val, 1500);
2129 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2131 return usb4_usb3_port_cm_request(port, true);
2134 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2136 return usb4_usb3_port_cm_request(port, false);
2139 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2141 unsigned long uframes;
2143 uframes = bw * 512UL << scale;
2144 return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2147 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2149 unsigned long uframes;
2151 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2152 uframes = ((unsigned long)mbps * MEGA) / 8000;
2153 return DIV_ROUND_UP(uframes, 512UL << scale);
2156 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2163 ret = tb_port_read(port, &val, TB_CFG_PORT,
2164 port->cap_adap + ADP_USB3_CS_2, 1);
2168 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2169 port->cap_adap + ADP_USB3_CS_3, 1);
2173 scale &= ADP_USB3_CS_3_SCALE_MASK;
2175 bw = val & ADP_USB3_CS_2_AUBW_MASK;
2176 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2178 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2179 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2185 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2186 * @port: USB3 adapter port
2187 * @upstream_bw: Allocated upstream bandwidth is stored here
2188 * @downstream_bw: Allocated downstream bandwidth is stored here
2190 * Stores currently allocated USB3 bandwidth into @upstream_bw and
2191 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
2194 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2199 ret = usb4_usb3_port_set_cm_request(port);
2203 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2205 usb4_usb3_port_clear_cm_request(port);
2210 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2217 ret = tb_port_read(port, &val, TB_CFG_PORT,
2218 port->cap_adap + ADP_USB3_CS_1, 1);
2222 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2223 port->cap_adap + ADP_USB3_CS_3, 1);
2227 scale &= ADP_USB3_CS_3_SCALE_MASK;
2229 bw = val & ADP_USB3_CS_1_CUBW_MASK;
2230 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2232 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2233 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2238 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2242 u32 val, ubw, dbw, scale;
2245 /* Figure out suitable scale */
2247 max_bw = max(upstream_bw, downstream_bw);
2248 while (scale < 64) {
2249 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2254 if (WARN_ON(scale >= 64))
2257 ret = tb_port_write(port, &scale, TB_CFG_PORT,
2258 port->cap_adap + ADP_USB3_CS_3, 1);
2262 ubw = mbps_to_usb3_bw(upstream_bw, scale);
2263 dbw = mbps_to_usb3_bw(downstream_bw, scale);
2265 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2267 ret = tb_port_read(port, &val, TB_CFG_PORT,
2268 port->cap_adap + ADP_USB3_CS_2, 1);
2272 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2273 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2276 return tb_port_write(port, &val, TB_CFG_PORT,
2277 port->cap_adap + ADP_USB3_CS_2, 1);
2281 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2282 * @port: USB3 adapter port
2283 * @upstream_bw: New upstream bandwidth
2284 * @downstream_bw: New downstream bandwidth
2286 * This can be used to set how much bandwidth is allocated for the USB3
2287 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2288 * new values programmed to the USB3 adapter allocation registers. If
2289 * the values are lower than what is currently consumed the allocation
2290 * is set to what is currently consumed instead (consumed bandwidth
2291 * cannot be taken away by CM). The actual new values are returned in
2292 * @upstream_bw and @downstream_bw.
2294 * Returns %0 in case of success and negative errno if there was a
2297 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2300 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2302 ret = usb4_usb3_port_set_cm_request(port);
2306 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2311 /* Don't allow it go lower than what is consumed */
2312 allocate_up = max(*upstream_bw, consumed_up);
2313 allocate_down = max(*downstream_bw, consumed_down);
2315 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2320 *upstream_bw = allocate_up;
2321 *downstream_bw = allocate_down;
2324 usb4_usb3_port_clear_cm_request(port);
2329 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2330 * @port: USB3 adapter port
2331 * @upstream_bw: New allocated upstream bandwidth
2332 * @downstream_bw: New allocated downstream bandwidth
2334 * Releases USB3 allocated bandwidth down to what is actually consumed.
2335 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2337 * Returns 0% in success and negative errno in case of failure.
2339 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2342 int ret, consumed_up, consumed_down;
2344 ret = usb4_usb3_port_set_cm_request(port);
2348 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2354 * Always keep 900 Mb/s to make sure xHCI has at least some
2355 * bandwidth available for isochronous traffic.
2357 if (consumed_up < 900)
2359 if (consumed_down < 900)
2360 consumed_down = 900;
2362 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2367 *upstream_bw = consumed_up;
2368 *downstream_bw = consumed_down;
2371 usb4_usb3_port_clear_cm_request(port);
2375 static bool is_usb4_dpin(const struct tb_port *port)
2377 if (!tb_port_is_dpin(port))
2379 if (!tb_switch_is_usb4(port->sw))
2385 * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2386 * @port: DP IN adapter
2387 * @cm_id: CM ID to assign
2389 * Sets CM ID for the @port. Returns %0 on success and negative errno
2390 * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2393 int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2398 if (!is_usb4_dpin(port))
2401 ret = tb_port_read(port, &val, TB_CFG_PORT,
2402 port->cap_adap + ADP_DP_CS_2, 1);
2406 val &= ~ADP_DP_CS_2_CM_ID_MASK;
2407 val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2409 return tb_port_write(port, &val, TB_CFG_PORT,
2410 port->cap_adap + ADP_DP_CS_2, 1);
2414 * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2416 * @port: DP IN adapter to check
2418 * Can be called to any DP IN adapter. Returns true if the adapter
2419 * supports USB4 bandwidth allocation mode, false otherwise.
2421 bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2426 if (!is_usb4_dpin(port))
2429 ret = tb_port_read(port, &val, TB_CFG_PORT,
2430 port->cap_adap + DP_LOCAL_CAP, 1);
2434 return !!(val & DP_COMMON_CAP_BW_MODE);
2438 * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2440 * @port: DP IN adapter to check
2442 * Can be called to any DP IN adapter. Returns true if the bandwidth
2443 * allocation mode has been enabled, false otherwise.
2445 bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2450 if (!is_usb4_dpin(port))
2453 ret = tb_port_read(port, &val, TB_CFG_PORT,
2454 port->cap_adap + ADP_DP_CS_8, 1);
2458 return !!(val & ADP_DP_CS_8_DPME);
2462 * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2463 * bandwidth allocation mode
2464 * @port: DP IN adapter
2465 * @supported: Does the CM support bandwidth allocation mode
2467 * Can be called to any DP IN adapter. Sets or clears the CM support bit
2468 * of the DP IN adapter. Returns %0 in success and negative errno
2469 * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2470 * does not support this.
2472 int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2478 if (!is_usb4_dpin(port))
2481 ret = tb_port_read(port, &val, TB_CFG_PORT,
2482 port->cap_adap + ADP_DP_CS_2, 1);
2487 val |= ADP_DP_CS_2_CMMS;
2489 val &= ~ADP_DP_CS_2_CMMS;
2491 return tb_port_write(port, &val, TB_CFG_PORT,
2492 port->cap_adap + ADP_DP_CS_2, 1);
2496 * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2497 * @port: DP IN adapter
2499 * Reads bandwidth allocation Group ID from the DP IN adapter and
2500 * returns it. If the adapter does not support setting Group_ID
2501 * %-EOPNOTSUPP is returned.
2503 int usb4_dp_port_group_id(struct tb_port *port)
2508 if (!is_usb4_dpin(port))
2511 ret = tb_port_read(port, &val, TB_CFG_PORT,
2512 port->cap_adap + ADP_DP_CS_2, 1);
2516 return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2520 * usb4_dp_port_set_group_id() - Set adapter Group ID
2521 * @port: DP IN adapter
2522 * @group_id: Group ID for the adapter
2524 * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2525 * Returns %0 in case of success and negative errno otherwise.
2526 * Specifically returns %-EOPNOTSUPP if the adapter does not support
2529 int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2534 if (!is_usb4_dpin(port))
2537 ret = tb_port_read(port, &val, TB_CFG_PORT,
2538 port->cap_adap + ADP_DP_CS_2, 1);
2542 val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2543 val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2545 return tb_port_write(port, &val, TB_CFG_PORT,
2546 port->cap_adap + ADP_DP_CS_2, 1);
2550 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2551 * @port: DP IN adapter
2552 * @rate: Non-reduced rate in Mb/s is placed here
2553 * @lanes: Non-reduced lanes are placed here
2555 * Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2556 * %0 in success and negative errno otherwise. Specifically returns
2557 * %-EOPNOTSUPP if the adapter does not support this.
2559 int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2564 if (!is_usb4_dpin(port))
2567 ret = tb_port_read(port, &val, TB_CFG_PORT,
2568 port->cap_adap + ADP_DP_CS_2, 1);
2572 tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2574 case DP_COMMON_CAP_RATE_RBR:
2577 case DP_COMMON_CAP_RATE_HBR:
2580 case DP_COMMON_CAP_RATE_HBR2:
2583 case DP_COMMON_CAP_RATE_HBR3:
2588 tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2590 case DP_COMMON_CAP_1_LANE:
2593 case DP_COMMON_CAP_2_LANES:
2596 case DP_COMMON_CAP_4_LANES:
2605 * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2606 * @port: DP IN adapter
2607 * @rate: Non-reduced rate in Mb/s
2608 * @lanes: Non-reduced lanes
2610 * Before the capabilities reduction this function can be used to set
2611 * the non-reduced values for the DP IN adapter. Returns %0 in success
2612 * and negative errno otherwise. If the adapter does not support this
2613 * %-EOPNOTSUPP is returned.
2615 int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2620 if (!is_usb4_dpin(port))
2623 ret = tb_port_read(port, &val, TB_CFG_PORT,
2624 port->cap_adap + ADP_DP_CS_2, 1);
2628 val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2634 val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2635 & ADP_DP_CS_2_NRD_MLR_MASK;
2638 val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2639 & ADP_DP_CS_2_NRD_MLR_MASK;
2642 val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2643 & ADP_DP_CS_2_NRD_MLR_MASK;
2649 val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2655 val |= DP_COMMON_CAP_2_LANES;
2658 val |= DP_COMMON_CAP_4_LANES;
2664 return tb_port_write(port, &val, TB_CFG_PORT,
2665 port->cap_adap + ADP_DP_CS_2, 1);
2669 * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2670 * @port: DP IN adapter
2672 * Reads the programmed granularity from @port. If the DP IN adapter does
2673 * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2674 * errno in other error cases.
2676 int usb4_dp_port_granularity(struct tb_port *port)
2681 if (!is_usb4_dpin(port))
2684 ret = tb_port_read(port, &val, TB_CFG_PORT,
2685 port->cap_adap + ADP_DP_CS_2, 1);
2689 val &= ADP_DP_CS_2_GR_MASK;
2690 val >>= ADP_DP_CS_2_GR_SHIFT;
2693 case ADP_DP_CS_2_GR_0_25G:
2695 case ADP_DP_CS_2_GR_0_5G:
2697 case ADP_DP_CS_2_GR_1G:
2705 * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2706 * @port: DP IN adapter
2707 * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2709 * Sets the granularity used with the estimated, allocated and requested
2710 * bandwidth. Returns %0 in success and negative errno otherwise. If the
2711 * adapter does not support this %-EOPNOTSUPP is returned.
2713 int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2718 if (!is_usb4_dpin(port))
2721 ret = tb_port_read(port, &val, TB_CFG_PORT,
2722 port->cap_adap + ADP_DP_CS_2, 1);
2726 val &= ~ADP_DP_CS_2_GR_MASK;
2728 switch (granularity) {
2730 val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2733 val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2736 val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2742 return tb_port_write(port, &val, TB_CFG_PORT,
2743 port->cap_adap + ADP_DP_CS_2, 1);
2747 * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2748 * @port: DP IN adapter
2749 * @bw: Estimated bandwidth in Mb/s.
2751 * Sets the estimated bandwidth to @bw. Set the granularity by calling
2752 * usb4_dp_port_set_granularity() before calling this. The @bw is round
2753 * down to the closest granularity multiplier. Returns %0 in success
2754 * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2755 * the adapter does not support this.
2757 int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2759 u32 val, granularity;
2762 if (!is_usb4_dpin(port))
2765 ret = usb4_dp_port_granularity(port);
2770 ret = tb_port_read(port, &val, TB_CFG_PORT,
2771 port->cap_adap + ADP_DP_CS_2, 1);
2775 val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2776 val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2778 return tb_port_write(port, &val, TB_CFG_PORT,
2779 port->cap_adap + ADP_DP_CS_2, 1);
2783 * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2784 * @port: DP IN adapter
2786 * Reads and returns allocated bandwidth for @port in Mb/s (taking into
2787 * account the programmed granularity). Returns negative errno in case
2790 int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2792 u32 val, granularity;
2795 if (!is_usb4_dpin(port))
2798 ret = usb4_dp_port_granularity(port);
2803 ret = tb_port_read(port, &val, TB_CFG_PORT,
2804 port->cap_adap + DP_STATUS, 1);
2808 val &= DP_STATUS_ALLOCATED_BW_MASK;
2809 val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2811 return val * granularity;
2814 static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2819 ret = tb_port_read(port, &val, TB_CFG_PORT,
2820 port->cap_adap + ADP_DP_CS_2, 1);
2825 val |= ADP_DP_CS_2_CA;
2827 val &= ~ADP_DP_CS_2_CA;
2829 return tb_port_write(port, &val, TB_CFG_PORT,
2830 port->cap_adap + ADP_DP_CS_2, 1);
2833 static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2835 return __usb4_dp_port_set_cm_ack(port, true);
2838 static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2845 ret = __usb4_dp_port_set_cm_ack(port, false);
2849 end = ktime_add_ms(ktime_get(), timeout_msec);
2851 ret = tb_port_read(port, &val, TB_CFG_PORT,
2852 port->cap_adap + ADP_DP_CS_8, 1);
2856 if (!(val & ADP_DP_CS_8_DR))
2859 usleep_range(50, 100);
2860 } while (ktime_before(ktime_get(), end));
2862 if (val & ADP_DP_CS_8_DR) {
2863 tb_port_warn(port, "timeout waiting for DPTX request to clear\n");
2867 ret = tb_port_read(port, &val, TB_CFG_PORT,
2868 port->cap_adap + ADP_DP_CS_2, 1);
2872 val &= ~ADP_DP_CS_2_CA;
2873 return tb_port_write(port, &val, TB_CFG_PORT,
2874 port->cap_adap + ADP_DP_CS_2, 1);
2878 * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2879 * @port: DP IN adapter
2880 * @bw: New allocated bandwidth in Mb/s
2882 * Communicates the new allocated bandwidth with the DPCD (graphics
2883 * driver). Takes into account the programmed granularity. Returns %0 in
2884 * success and negative errno in case of error.
2886 int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2888 u32 val, granularity;
2891 if (!is_usb4_dpin(port))
2894 ret = usb4_dp_port_granularity(port);
2899 ret = tb_port_read(port, &val, TB_CFG_PORT,
2900 port->cap_adap + DP_STATUS, 1);
2904 val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2905 val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2907 ret = tb_port_write(port, &val, TB_CFG_PORT,
2908 port->cap_adap + DP_STATUS, 1);
2912 ret = usb4_dp_port_set_cm_ack(port);
2916 return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
2920 * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2921 * @port: DP IN adapter
2923 * Reads the DPCD (graphics driver) requested bandwidth and returns it
2924 * in Mb/s. Takes the programmed granularity into account. In case of
2925 * error returns negative errno. Specifically returns %-EOPNOTSUPP if
2926 * the adapter does not support bandwidth allocation mode, and %ENODATA
2927 * if there is no active bandwidth request from the graphics driver.
2929 int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2931 u32 val, granularity;
2934 if (!is_usb4_dpin(port))
2937 ret = usb4_dp_port_granularity(port);
2942 ret = tb_port_read(port, &val, TB_CFG_PORT,
2943 port->cap_adap + ADP_DP_CS_8, 1);
2947 if (!(val & ADP_DP_CS_8_DR))
2950 return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2954 * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2955 * @port: PCIe adapter
2956 * @enable: Enable/disable extended encapsulation
2958 * Enables or disables extended encapsulation used in PCIe tunneling. Caller
2959 * needs to make sure both adapters support this before enabling. Returns %0 on
2960 * success and negative errno otherwise.
2962 int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2967 if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2970 ret = tb_port_read(port, &val, TB_CFG_PORT,
2971 port->cap_adap + ADP_PCIE_CS_1, 1);
2976 val |= ADP_PCIE_CS_1_EE;
2978 val &= ~ADP_PCIE_CS_1_EE;
2980 return tb_port_write(port, &val, TB_CFG_PORT,
2981 port->cap_adap + ADP_PCIE_CS_1, 1);