drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma/imx-dma.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/slab.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/spi/spi_bitbang.h>
  27 #include <linux/types.h>
  28
  29 #define DRIVER_NAME "fsl_lpspi"
  30
  31 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  32
  33 /* The maximum bytes that edma can transfer once.*/
  34 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
  35
  36 /* i.MX7ULP LPSPI registers */
  37 #define IMX7ULP_VERID   0x0
  38 #define IMX7ULP_PARAM   0x4
  39 #define IMX7ULP_CR      0x10
  40 #define IMX7ULP_SR      0x14
  41 #define IMX7ULP_IER     0x18
  42 #define IMX7ULP_DER     0x1c
  43 #define IMX7ULP_CFGR0   0x20
  44 #define IMX7ULP_CFGR1   0x24
  45 #define IMX7ULP_DMR0    0x30
  46 #define IMX7ULP_DMR1    0x34
  47 #define IMX7ULP_CCR     0x40
  48 #define IMX7ULP_FCR     0x58
  49 #define IMX7ULP_FSR     0x5c
  50 #define IMX7ULP_TCR     0x60
  51 #define IMX7ULP_TDR     0x64
  52 #define IMX7ULP_RSR     0x70
  53 #define IMX7ULP_RDR     0x74
  54
  55 /* General control register field define */
  56 #define CR_RRF          BIT(9)
  57 #define CR_RTF          BIT(8)
  58 #define CR_RST          BIT(1)
  59 #define CR_MEN          BIT(0)
  60 #define SR_MBF          BIT(24)
  61 #define SR_TCF          BIT(10)
  62 #define SR_FCF          BIT(9)
  63 #define SR_RDF          BIT(1)
  64 #define SR_TDF          BIT(0)
  65 #define IER_TCIE        BIT(10)
  66 #define IER_FCIE        BIT(9)
  67 #define IER_RDIE        BIT(1)
  68 #define IER_TDIE        BIT(0)
  69 #define DER_RDDE        BIT(1)
  70 #define DER_TDDE        BIT(0)
  71 #define CFGR1_PCSCFG    BIT(27)
  72 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  73 #define CFGR1_PCSPOL    BIT(8)
  74 #define CFGR1_NOSTALL   BIT(3)
  75 #define CFGR1_HOST      BIT(0)
  76 #define FSR_TXCOUNT     (0xFF)
  77 #define RSR_RXEMPTY     BIT(1)
  78 #define TCR_CPOL        BIT(31)
  79 #define TCR_CPHA        BIT(30)
  80 #define TCR_CONT        BIT(21)
  81 #define TCR_CONTC       BIT(20)
  82 #define TCR_RXMSK       BIT(19)
  83 #define TCR_TXMSK       BIT(18)
  84
  85 struct lpspi_config {
  86         u8 bpw;
  87         u8 chip_select;
  88         u8 prescale;
  89         u16 mode;
  90         u32 speed_hz;
  91 };
  92
  93 struct fsl_lpspi_data {
  94         struct device *dev;
  95         void __iomem *base;
  96         unsigned long base_phys;
  97         struct clk *clk_ipg;
  98         struct clk *clk_per;
  99         bool is_target;
 100         bool is_only_cs1;
 101         bool is_first_byte;
 102
 103         void *rx_buf;
 104         const void *tx_buf;
 105         void (*tx)(struct fsl_lpspi_data *);
 106         void (*rx)(struct fsl_lpspi_data *);
 107
 108         u32 remain;
 109         u8 watermark;
 110         u8 txfifosize;
 111         u8 rxfifosize;
 112
 113         struct lpspi_config config;
 114         struct completion xfer_done;
 115
 116         bool target_aborted;
 117
 118         /* DMA */
 119         bool usedma;
 120         struct completion dma_rx_completion;
 121         struct completion dma_tx_completion;
 122 };
 123
 124 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 125         { .compatible = "fsl,imx7ulp-spi", },
 126         { /* sentinel */ }
 127 };
 128 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 129
 130 #define LPSPI_BUF_RX(type)                                              \
 131 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 132 {                                                                       \
 133         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 134                                                                         \
 135         if (fsl_lpspi->rx_buf) {                                        \
 136                 *(type *)fsl_lpspi->rx_buf = val;                       \
 137                 fsl_lpspi->rx_buf += sizeof(type);                      \
 138         }                                                               \
 139 }
 140
 141 #define LPSPI_BUF_TX(type)                                              \
 142 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 143 {                                                                       \
 144         type val = 0;                                                   \
 145                                                                         \
 146         if (fsl_lpspi->tx_buf) {                                        \
 147                 val = *(type *)fsl_lpspi->tx_buf;                       \
 148                 fsl_lpspi->tx_buf += sizeof(type);                      \
 149         }                                                               \
 150                                                                         \
 151         fsl_lpspi->remain -= sizeof(type);                              \
 152         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 153 }
 154
 155 LPSPI_BUF_RX(u8)
 156 LPSPI_BUF_TX(u8)
 157 LPSPI_BUF_RX(u16)
 158 LPSPI_BUF_TX(u16)
 159 LPSPI_BUF_RX(u32)
 160 LPSPI_BUF_TX(u32)
 161
 162 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 163                               unsigned int enable)
 164 {
 165         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 166 }
 167
 168 static int fsl_lpspi_bytes_per_word(const int bpw)
 169 {
 170         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 171 }
 172
 173 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
 174                               struct spi_device *spi,
 175                               struct spi_transfer *transfer)
 176 {
 177         unsigned int bytes_per_word;
 178
 179         if (!controller->dma_rx)
 180                 return false;
 181
 182         bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
 183
 184         switch (bytes_per_word) {
 185         case 1:
 186         case 2:
 187         case 4:
 188                 break;
 189         default:
 190                 return false;
 191         }
 192
 193         return true;
 194 }
 195
 196 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 197 {
 198         struct fsl_lpspi_data *fsl_lpspi =
 199                                 spi_controller_get_devdata(controller);
 200         int ret;
 201
 202         ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
 203         if (ret < 0) {
 204                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 205                 return ret;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 212 {
 213         struct fsl_lpspi_data *fsl_lpspi =
 214                                 spi_controller_get_devdata(controller);
 215
 216         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 217         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 218
 219         return 0;
 220 }
 221
 222 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 223 {
 224         u8 txfifo_cnt;
 225         u32 temp;
 226
 227         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 228
 229         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 230                 if (!fsl_lpspi->remain)
 231                         break;
 232                 fsl_lpspi->tx(fsl_lpspi);
 233                 txfifo_cnt++;
 234         }
 235
 236         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 237                 if (!fsl_lpspi->is_target) {
 238                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 239                         temp &= ~TCR_CONTC;
 240                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 241                 }
 242
 243                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 244         } else
 245                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 246 }
 247
 248 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 249 {
 250         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 251                 fsl_lpspi->rx(fsl_lpspi);
 252 }
 253
 254 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
 255 {
 256         u32 temp = 0;
 257
 258         temp |= fsl_lpspi->config.bpw - 1;
 259         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 260         temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 261         if (!fsl_lpspi->is_target) {
 262                 temp |= fsl_lpspi->config.prescale << 27;
 263                 /*
 264                  * Set TCR_CONT will keep SS asserted after current transfer.
 265                  * For the first transfer, clear TCR_CONTC to assert SS.
 266                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 267                  */
 268                 if (!fsl_lpspi->usedma) {
 269                         temp |= TCR_CONT;
 270                         if (fsl_lpspi->is_first_byte)
 271                                 temp &= ~TCR_CONTC;
 272                         else
 273                                 temp |= TCR_CONTC;
 274                 }
 275         }
 276         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 277
 278         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 279 }
 280
 281 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 282 {
 283         u32 temp;
 284
 285         if (!fsl_lpspi->usedma)
 286                 temp = fsl_lpspi->watermark >> 1 |
 287                        (fsl_lpspi->watermark >> 1) << 16;
 288         else
 289                 temp = fsl_lpspi->watermark >> 1;
 290
 291         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 292
 293         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 294 }
 295
 296 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 297 {
 298         struct lpspi_config config = fsl_lpspi->config;
 299         unsigned int perclk_rate, scldiv;
 300         u8 prescale;
 301
 302         perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
 303
 304         if (!config.speed_hz) {
 305                 dev_err(fsl_lpspi->dev,
 306                         "error: the transmission speed provided is 0!\n");
 307                 return -EINVAL;
 308         }
 309
 310         if (config.speed_hz > perclk_rate / 2) {
 311                 dev_err(fsl_lpspi->dev,
 312                       "per-clk should be at least two times of transfer speed");
 313                 return -EINVAL;
 314         }
 315
 316         for (prescale = 0; prescale < 8; prescale++) {
 317                 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
 318                 if (scldiv < 256) {
 319                         fsl_lpspi->config.prescale = prescale;
 320                         break;
 321                 }
 322         }
 323
 324         if (scldiv >= 256)
 325                 return -EINVAL;
 326
 327         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 328                                         fsl_lpspi->base + IMX7ULP_CCR);
 329
 330         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
 331                 perclk_rate, config.speed_hz, prescale, scldiv);
 332
 333         return 0;
 334 }
 335
 336 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
 337 {
 338         int ret;
 339         enum dma_slave_buswidth buswidth;
 340         struct dma_slave_config rx = {}, tx = {};
 341         struct fsl_lpspi_data *fsl_lpspi =
 342                                 spi_controller_get_devdata(controller);
 343
 344         switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
 345         case 4:
 346                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 347                 break;
 348         case 2:
 349                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 350                 break;
 351         case 1:
 352                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 353                 break;
 354         default:
 355                 return -EINVAL;
 356         }
 357
 358         tx.direction = DMA_MEM_TO_DEV;
 359         tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
 360         tx.dst_addr_width = buswidth;
 361         tx.dst_maxburst = 1;
 362         ret = dmaengine_slave_config(controller->dma_tx, &tx);
 363         if (ret) {
 364                 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
 365                         ret);
 366                 return ret;
 367         }
 368
 369         rx.direction = DMA_DEV_TO_MEM;
 370         rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
 371         rx.src_addr_width = buswidth;
 372         rx.src_maxburst = 1;
 373         ret = dmaengine_slave_config(controller->dma_rx, &rx);
 374         if (ret) {
 375                 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
 376                         ret);
 377                 return ret;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 384 {
 385         u32 temp;
 386         int ret;
 387
 388         if (!fsl_lpspi->is_target) {
 389                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 390                 if (ret)
 391                         return ret;
 392         }
 393
 394         fsl_lpspi_set_watermark(fsl_lpspi);
 395
 396         if (!fsl_lpspi->is_target)
 397                 temp = CFGR1_HOST;
 398         else
 399                 temp = CFGR1_PINCFG;
 400         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 401                 temp |= CFGR1_PCSPOL;
 402         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 403
 404         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 405         temp |= CR_RRF | CR_RTF | CR_MEN;
 406         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 407
 408         temp = 0;
 409         if (fsl_lpspi->usedma)
 410                 temp = DER_TDDE | DER_RDDE;
 411         writel(temp, fsl_lpspi->base + IMX7ULP_DER);
 412
 413         return 0;
 414 }
 415
 416 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
 417                                      struct spi_device *spi,
 418                                      struct spi_transfer *t)
 419 {
 420         struct fsl_lpspi_data *fsl_lpspi =
 421                                 spi_controller_get_devdata(spi->controller);
 422
 423         if (t == NULL)
 424                 return -EINVAL;
 425
 426         fsl_lpspi->config.mode = spi->mode;
 427         fsl_lpspi->config.bpw = t->bits_per_word;
 428         fsl_lpspi->config.speed_hz = t->speed_hz;
 429         if (fsl_lpspi->is_only_cs1)
 430                 fsl_lpspi->config.chip_select = 1;
 431         else
 432                 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
 433
 434         if (!fsl_lpspi->config.speed_hz)
 435                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 436         if (!fsl_lpspi->config.bpw)
 437                 fsl_lpspi->config.bpw = spi->bits_per_word;
 438
 439         /* Initialize the functions for transfer */
 440         if (fsl_lpspi->config.bpw <= 8) {
 441                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 442                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 443         } else if (fsl_lpspi->config.bpw <= 16) {
 444                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 445                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 446         } else {
 447                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 448                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 449         }
 450
 451         if (t->len <= fsl_lpspi->txfifosize)
 452                 fsl_lpspi->watermark = t->len;
 453         else
 454                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 455
 456         if (fsl_lpspi_can_dma(controller, spi, t))
 457                 fsl_lpspi->usedma = true;
 458         else
 459                 fsl_lpspi->usedma = false;
 460
 461         return fsl_lpspi_config(fsl_lpspi);
 462 }
 463
 464 static int fsl_lpspi_target_abort(struct spi_controller *controller)
 465 {
 466         struct fsl_lpspi_data *fsl_lpspi =
 467                                 spi_controller_get_devdata(controller);
 468
 469         fsl_lpspi->target_aborted = true;
 470         if (!fsl_lpspi->usedma)
 471                 complete(&fsl_lpspi->xfer_done);
 472         else {
 473                 complete(&fsl_lpspi->dma_tx_completion);
 474                 complete(&fsl_lpspi->dma_rx_completion);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 481 {
 482         struct fsl_lpspi_data *fsl_lpspi =
 483                                 spi_controller_get_devdata(controller);
 484
 485         if (fsl_lpspi->is_target) {
 486                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 487                         fsl_lpspi->target_aborted) {
 488                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 489                         return -EINTR;
 490                 }
 491         } else {
 492                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 493                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 494                         return -ETIMEDOUT;
 495                 }
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 502 {
 503         u32 temp;
 504
 505         if (!fsl_lpspi->usedma) {
 506                 /* Disable all interrupt */
 507                 fsl_lpspi_intctrl(fsl_lpspi, 0);
 508         }
 509
 510         /* W1C for all flags in SR */
 511         temp = 0x3F << 8;
 512         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 513
 514         /* Clear FIFO and disable module */
 515         temp = CR_RRF | CR_RTF;
 516         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 517
 518         return 0;
 519 }
 520
 521 static void fsl_lpspi_dma_rx_callback(void *cookie)
 522 {
 523         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 524
 525         complete(&fsl_lpspi->dma_rx_completion);
 526 }
 527
 528 static void fsl_lpspi_dma_tx_callback(void *cookie)
 529 {
 530         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 531
 532         complete(&fsl_lpspi->dma_tx_completion);
 533 }
 534
 535 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
 536                                        int size)
 537 {
 538         unsigned long timeout = 0;
 539
 540         /* Time with actual data transfer and CS change delay related to HW */
 541         timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
 542
 543         /* Add extra second for scheduler related activities */
 544         timeout += 1;
 545
 546         /* Double calculated timeout */
 547         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
 548 }
 549
 550 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
 551                                 struct fsl_lpspi_data *fsl_lpspi,
 552                                 struct spi_transfer *transfer)
 553 {
 554         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
 555         unsigned long transfer_timeout;
 556         unsigned long timeout;
 557         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
 558         int ret;
 559
 560         ret = fsl_lpspi_dma_configure(controller);
 561         if (ret)
 562                 return ret;
 563
 564         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
 565                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
 566                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 567         if (!desc_rx)
 568                 return -EINVAL;
 569
 570         desc_rx->callback = fsl_lpspi_dma_rx_callback;
 571         desc_rx->callback_param = (void *)fsl_lpspi;
 572         dmaengine_submit(desc_rx);
 573         reinit_completion(&fsl_lpspi->dma_rx_completion);
 574         dma_async_issue_pending(controller->dma_rx);
 575
 576         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
 577                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
 578                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 579         if (!desc_tx) {
 580                 dmaengine_terminate_all(controller->dma_tx);
 581                 return -EINVAL;
 582         }
 583
 584         desc_tx->callback = fsl_lpspi_dma_tx_callback;
 585         desc_tx->callback_param = (void *)fsl_lpspi;
 586         dmaengine_submit(desc_tx);
 587         reinit_completion(&fsl_lpspi->dma_tx_completion);
 588         dma_async_issue_pending(controller->dma_tx);
 589
 590         fsl_lpspi->target_aborted = false;
 591
 592         if (!fsl_lpspi->is_target) {
 593                 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
 594                                                                transfer->len);
 595
 596                 /* Wait eDMA to finish the data transfer.*/
 597                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
 598                                                       transfer_timeout);
 599                 if (!timeout) {
 600                         dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
 601                         dmaengine_terminate_all(controller->dma_tx);
 602                         dmaengine_terminate_all(controller->dma_rx);
 603                         fsl_lpspi_reset(fsl_lpspi);
 604                         return -ETIMEDOUT;
 605                 }
 606
 607                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
 608                                                       transfer_timeout);
 609                 if (!timeout) {
 610                         dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
 611                         dmaengine_terminate_all(controller->dma_tx);
 612                         dmaengine_terminate_all(controller->dma_rx);
 613                         fsl_lpspi_reset(fsl_lpspi);
 614                         return -ETIMEDOUT;
 615                 }
 616         } else {
 617                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
 618                         fsl_lpspi->target_aborted) {
 619                         dev_dbg(fsl_lpspi->dev,
 620                                 "I/O Error in DMA TX interrupted\n");
 621                         dmaengine_terminate_all(controller->dma_tx);
 622                         dmaengine_terminate_all(controller->dma_rx);
 623                         fsl_lpspi_reset(fsl_lpspi);
 624                         return -EINTR;
 625                 }
 626
 627                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
 628                         fsl_lpspi->target_aborted) {
 629                         dev_dbg(fsl_lpspi->dev,
 630                                 "I/O Error in DMA RX interrupted\n");
 631                         dmaengine_terminate_all(controller->dma_tx);
 632                         dmaengine_terminate_all(controller->dma_rx);
 633                         fsl_lpspi_reset(fsl_lpspi);
 634                         return -EINTR;
 635                 }
 636         }
 637
 638         fsl_lpspi_reset(fsl_lpspi);
 639
 640         return 0;
 641 }
 642
 643 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
 644 {
 645         if (controller->dma_rx) {
 646                 dma_release_channel(controller->dma_rx);
 647                 controller->dma_rx = NULL;
 648         }
 649
 650         if (controller->dma_tx) {
 651                 dma_release_channel(controller->dma_tx);
 652                 controller->dma_tx = NULL;
 653         }
 654 }
 655
 656 static int fsl_lpspi_dma_init(struct device *dev,
 657                               struct fsl_lpspi_data *fsl_lpspi,
 658                               struct spi_controller *controller)
 659 {
 660         int ret;
 661
 662         /* Prepare for TX DMA: */
 663         controller->dma_tx = dma_request_chan(dev, "tx");
 664         if (IS_ERR(controller->dma_tx)) {
 665                 ret = PTR_ERR(controller->dma_tx);
 666                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
 667                 controller->dma_tx = NULL;
 668                 goto err;
 669         }
 670
 671         /* Prepare for RX DMA: */
 672         controller->dma_rx = dma_request_chan(dev, "rx");
 673         if (IS_ERR(controller->dma_rx)) {
 674                 ret = PTR_ERR(controller->dma_rx);
 675                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
 676                 controller->dma_rx = NULL;
 677                 goto err;
 678         }
 679
 680         init_completion(&fsl_lpspi->dma_rx_completion);
 681         init_completion(&fsl_lpspi->dma_tx_completion);
 682         controller->can_dma = fsl_lpspi_can_dma;
 683         controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
 684
 685         return 0;
 686 err:
 687         fsl_lpspi_dma_exit(controller);
 688         return ret;
 689 }
 690
 691 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 692                                   struct spi_transfer *t)
 693 {
 694         struct fsl_lpspi_data *fsl_lpspi =
 695                                 spi_controller_get_devdata(controller);
 696         int ret;
 697
 698         fsl_lpspi->tx_buf = t->tx_buf;
 699         fsl_lpspi->rx_buf = t->rx_buf;
 700         fsl_lpspi->remain = t->len;
 701
 702         reinit_completion(&fsl_lpspi->xfer_done);
 703         fsl_lpspi->target_aborted = false;
 704
 705         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 706
 707         ret = fsl_lpspi_wait_for_completion(controller);
 708         if (ret)
 709                 return ret;
 710
 711         fsl_lpspi_reset(fsl_lpspi);
 712
 713         return 0;
 714 }
 715
 716 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 717                                   struct spi_device *spi,
 718                                   struct spi_transfer *t)
 719 {
 720         struct fsl_lpspi_data *fsl_lpspi =
 721                                         spi_controller_get_devdata(controller);
 722         int ret;
 723
 724         fsl_lpspi->is_first_byte = true;
 725         ret = fsl_lpspi_setup_transfer(controller, spi, t);
 726         if (ret < 0)
 727                 return ret;
 728
 729         fsl_lpspi_set_cmd(fsl_lpspi);
 730         fsl_lpspi->is_first_byte = false;
 731
 732         if (fsl_lpspi->usedma)
 733                 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
 734         else
 735                 ret = fsl_lpspi_pio_transfer(controller, t);
 736         if (ret < 0)
 737                 return ret;
 738
 739         return 0;
 740 }
 741
 742 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 743 {
 744         u32 temp_SR, temp_IER;
 745         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 746
 747         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 748         fsl_lpspi_intctrl(fsl_lpspi, 0);
 749         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 750
 751         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 752
 753         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 754                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 755                 return IRQ_HANDLED;
 756         }
 757
 758         if (temp_SR & SR_MBF ||
 759             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
 760                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 761                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 762                 return IRQ_HANDLED;
 763         }
 764
 765         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 766                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 767                 complete(&fsl_lpspi->xfer_done);
 768                 return IRQ_HANDLED;
 769         }
 770
 771         return IRQ_NONE;
 772 }
 773
 774 #ifdef CONFIG_PM
 775 static int fsl_lpspi_runtime_resume(struct device *dev)
 776 {
 777         struct spi_controller *controller = dev_get_drvdata(dev);
 778         struct fsl_lpspi_data *fsl_lpspi;
 779         int ret;
 780
 781         fsl_lpspi = spi_controller_get_devdata(controller);
 782
 783         ret = clk_prepare_enable(fsl_lpspi->clk_per);
 784         if (ret)
 785                 return ret;
 786
 787         ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
 788         if (ret) {
 789                 clk_disable_unprepare(fsl_lpspi->clk_per);
 790                 return ret;
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int fsl_lpspi_runtime_suspend(struct device *dev)
 797 {
 798         struct spi_controller *controller = dev_get_drvdata(dev);
 799         struct fsl_lpspi_data *fsl_lpspi;
 800
 801         fsl_lpspi = spi_controller_get_devdata(controller);
 802
 803         clk_disable_unprepare(fsl_lpspi->clk_per);
 804         clk_disable_unprepare(fsl_lpspi->clk_ipg);
 805
 806         return 0;
 807 }
 808 #endif
 809
 810 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
 811 {
 812         struct device *dev = fsl_lpspi->dev;
 813
 814         pm_runtime_enable(dev);
 815         pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
 816         pm_runtime_use_autosuspend(dev);
 817
 818         return 0;
 819 }
 820
 821 static int fsl_lpspi_probe(struct platform_device *pdev)
 822 {
 823         struct fsl_lpspi_data *fsl_lpspi;
 824         struct spi_controller *controller;
 825         struct resource *res;
 826         int ret, irq;
 827         u32 num_cs;
 828         u32 temp;
 829         bool is_target;
 830
 831         is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
 832         if (is_target)
 833                 controller = devm_spi_alloc_target(&pdev->dev,
 834                                                    sizeof(struct fsl_lpspi_data));
 835         else
 836                 controller = devm_spi_alloc_host(&pdev->dev,
 837                                                  sizeof(struct fsl_lpspi_data));
 838
 839         if (!controller)
 840                 return -ENOMEM;
 841
 842         platform_set_drvdata(pdev, controller);
 843
 844         fsl_lpspi = spi_controller_get_devdata(controller);
 845         fsl_lpspi->dev = &pdev->dev;
 846         fsl_lpspi->is_target = is_target;
 847         fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
 848                                                 "fsl,spi-only-use-cs1-sel");
 849
 850         init_completion(&fsl_lpspi->xfer_done);
 851
 852         fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 853         if (IS_ERR(fsl_lpspi->base)) {
 854                 ret = PTR_ERR(fsl_lpspi->base);
 855                 goto out_controller_put;
 856         }
 857         fsl_lpspi->base_phys = res->start;
 858
 859         irq = platform_get_irq(pdev, 0);
 860         if (irq < 0) {
 861                 ret = irq;
 862                 goto out_controller_put;
 863         }
 864
 865         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 866                                dev_name(&pdev->dev), fsl_lpspi);
 867         if (ret) {
 868                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 869                 goto out_controller_put;
 870         }
 871
 872         fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
 873         if (IS_ERR(fsl_lpspi->clk_per)) {
 874                 ret = PTR_ERR(fsl_lpspi->clk_per);
 875                 goto out_controller_put;
 876         }
 877
 878         fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 879         if (IS_ERR(fsl_lpspi->clk_ipg)) {
 880                 ret = PTR_ERR(fsl_lpspi->clk_ipg);
 881                 goto out_controller_put;
 882         }
 883
 884         /* enable the clock */
 885         ret = fsl_lpspi_init_rpm(fsl_lpspi);
 886         if (ret)
 887                 goto out_controller_put;
 888
 889         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 890         if (ret < 0) {
 891                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 892                 goto out_pm_get;
 893         }
 894
 895         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 896         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 897         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 898         if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
 899                                  &num_cs)) {
 900                 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
 901                         num_cs = ((temp >> 16) & 0xf);
 902                 else
 903                         num_cs = 1;
 904         }
 905
 906         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 907         controller->transfer_one = fsl_lpspi_transfer_one;
 908         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 909         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 910         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 911         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
 912         controller->dev.of_node = pdev->dev.of_node;
 913         controller->bus_num = pdev->id;
 914         controller->num_chipselect = num_cs;
 915         controller->target_abort = fsl_lpspi_target_abort;
 916         if (!fsl_lpspi->is_target)
 917                 controller->use_gpio_descriptors = true;
 918
 919         ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
 920         if (ret == -EPROBE_DEFER)
 921                 goto out_pm_get;
 922         if (ret < 0)
 923                 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
 924         else
 925                 /*
 926                  * disable LPSPI module IRQ when enable DMA mode successfully,
 927                  * to prevent the unexpected LPSPI module IRQ events.
 928                  */
 929                 disable_irq(irq);
 930
 931         ret = devm_spi_register_controller(&pdev->dev, controller);
 932         if (ret < 0) {
 933                 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
 934                 goto free_dma;
 935         }
 936
 937         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 938         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 939
 940         return 0;
 941
 942 free_dma:
 943         fsl_lpspi_dma_exit(controller);
 944 out_pm_get:
 945         pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
 946         pm_runtime_put_sync(fsl_lpspi->dev);
 947         pm_runtime_disable(fsl_lpspi->dev);
 948 out_controller_put:
 949         spi_controller_put(controller);
 950
 951         return ret;
 952 }
 953
 954 static void fsl_lpspi_remove(struct platform_device *pdev)
 955 {
 956         struct spi_controller *controller = platform_get_drvdata(pdev);
 957         struct fsl_lpspi_data *fsl_lpspi =
 958                                 spi_controller_get_devdata(controller);
 959
 960         fsl_lpspi_dma_exit(controller);
 961
 962         pm_runtime_disable(fsl_lpspi->dev);
 963 }
 964
 965 static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
 966 {
 967         pinctrl_pm_select_sleep_state(dev);
 968         return pm_runtime_force_suspend(dev);
 969 }
 970
 971 static int __maybe_unused fsl_lpspi_resume(struct device *dev)
 972 {
 973         int ret;
 974
 975         ret = pm_runtime_force_resume(dev);
 976         if (ret) {
 977                 dev_err(dev, "Error in resume: %d\n", ret);
 978                 return ret;
 979         }
 980
 981         pinctrl_pm_select_default_state(dev);
 982
 983         return 0;
 984 }
 985
 986 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
 987         SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
 988                                 fsl_lpspi_runtime_resume, NULL)
 989         SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
 990 };
 991
 992 static struct platform_driver fsl_lpspi_driver = {
 993         .driver = {
 994                 .name = DRIVER_NAME,
 995                 .of_match_table = fsl_lpspi_dt_ids,
 996                 .pm = &fsl_lpspi_pm_ops,
 997         },
 998         .probe = fsl_lpspi_probe,
 999         .remove_new = fsl_lpspi_remove,
1000 };
1001 module_platform_driver(fsl_lpspi_driver);
1002
1003 MODULE_DESCRIPTION("LPSPI Controller driver");
1004 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1005 MODULE_LICENSE("GPL");