drivers/gpu/drm/xe/xe_sched_job_types.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  */
   5
   6 #ifndef _XE_SCHED_JOB_TYPES_H_
   7 #define _XE_SCHED_JOB_TYPES_H_
   8
   9 #include <linux/kref.h>
  10
  11 #include <drm/gpu_scheduler.h>
  12
  13 struct xe_exec_queue;
  14
  15 /**
  16  * struct xe_sched_job - XE schedule job (batch buffer tracking)
  17  */
  18 struct xe_sched_job {
  19         /** @drm: base DRM scheduler job */
  20         struct drm_sched_job drm;
  21         /** @q: Exec queue */
  22         struct xe_exec_queue *q;
  23         /** @refcount: ref count of this job */
  24         struct kref refcount;
  25         /**
  26          * @fence: dma fence to indicate completion. 1 way relationship - job
  27          * can safely reference fence, fence cannot safely reference job.
  28          */
  29 #define JOB_FLAG_SUBMIT         DMA_FENCE_FLAG_USER_BITS
  30         struct dma_fence *fence;
  31         /** @user_fence: write back value when BB is complete */
  32         struct {
  33                 /** @user_fence.used: user fence is used */
  34                 bool used;
  35                 /** @user_fence.addr: address to write to */
  36                 u64 addr;
  37                 /** @user_fence.value: write back value */
  38                 u64 value;
  39         } user_fence;
  40         /** @migrate_flush_flags: Additional flush flags for migration jobs */
  41         u32 migrate_flush_flags;
  42         /** @batch_addr: batch buffer address of job */
  43         u64 batch_addr[];
  44 };
  45
  46 struct xe_sched_job_snapshot {
  47         u16 batch_addr_len;
  48         u64 batch_addr[];
  49 };
  50
  51 #endif