drivers/gpu/drm/nouveau/core/include/core/class.h

   1 #ifndef __NOUVEAU_CLASS_H__
   2 #define __NOUVEAU_CLASS_H__
   3
   4 #include <nvif/class.h>
   5
   6 /* DMA FIFO channel classes
   7  *
   8  * 006b: NV03_CHANNEL_DMA
   9  * 006e: NV10_CHANNEL_DMA
  10  * 176e: NV17_CHANNEL_DMA
  11  * 406e: NV40_CHANNEL_DMA
  12  * 506e: NV50_CHANNEL_DMA
  13  * 826e: NV84_CHANNEL_DMA
  14  */
  15 #define NV03_CHANNEL_DMA_CLASS                                       0x0000006b
  16 #define NV10_CHANNEL_DMA_CLASS                                       0x0000006e
  17 #define NV17_CHANNEL_DMA_CLASS                                       0x0000176e
  18 #define NV40_CHANNEL_DMA_CLASS                                       0x0000406e
  19 #define NV50_CHANNEL_DMA_CLASS                                       0x0000506e
  20 #define NV84_CHANNEL_DMA_CLASS                                       0x0000826e
  21
  22 struct nv03_channel_dma_class {
  23         u32 pushbuf;
  24         u32 pad0;
  25         u64 offset;
  26 };
  27
  28 /* Indirect FIFO channel classes
  29  *
  30  * 506f: NV50_CHANNEL_IND
  31  * 826f: NV84_CHANNEL_IND
  32  * 906f: NVC0_CHANNEL_IND
  33  * a06f: NVE0_CHANNEL_IND
  34  */
  35
  36 #define NV50_CHANNEL_IND_CLASS                                       0x0000506f
  37 #define NV84_CHANNEL_IND_CLASS                                       0x0000826f
  38 #define NVC0_CHANNEL_IND_CLASS                                       0x0000906f
  39 #define NVE0_CHANNEL_IND_CLASS                                       0x0000a06f
  40
  41 struct nv50_channel_ind_class {
  42         u32 pushbuf;
  43         u32 ilength;
  44         u64 ioffset;
  45 };
  46
  47 #define NVE0_CHANNEL_IND_ENGINE_GR                                   0x00000001
  48 #define NVE0_CHANNEL_IND_ENGINE_VP                                   0x00000002
  49 #define NVE0_CHANNEL_IND_ENGINE_PPP                                  0x00000004
  50 #define NVE0_CHANNEL_IND_ENGINE_BSP                                  0x00000008
  51 #define NVE0_CHANNEL_IND_ENGINE_CE0                                  0x00000010
  52 #define NVE0_CHANNEL_IND_ENGINE_CE1                                  0x00000020
  53 #define NVE0_CHANNEL_IND_ENGINE_ENC                                  0x00000040
  54
  55 struct nve0_channel_ind_class {
  56         u32 pushbuf;
  57         u32 ilength;
  58         u64 ioffset;
  59         u32 engine;
  60 };
  61
  62 /* 0046: NV04_DISP
  63  */
  64
  65 #define NV04_DISP_CLASS                                              0x00000046
  66
  67 #define NV04_DISP_MTHD                                               0x00000000
  68 #define NV04_DISP_MTHD_HEAD                                          0x00000001
  69
  70 #define NV04_DISP_SCANOUTPOS                                         0x00000000
  71
  72 struct nv04_display_class {
  73 };
  74
  75 struct nv04_display_scanoutpos {
  76         s64 time[2];
  77         u32 vblanks;
  78         u32 vblanke;
  79         u32 vtotal;
  80         u32 vline;
  81         u32 hblanks;
  82         u32 hblanke;
  83         u32 htotal;
  84         u32 hline;
  85 };
  86
  87 /* 5070: NV50_DISP
  88  * 8270: NV84_DISP
  89  * 8370: NVA0_DISP
  90  * 8870: NV94_DISP
  91  * 8570: NVA3_DISP
  92  * 9070: NVD0_DISP
  93  * 9170: NVE0_DISP
  94  * 9270: NVF0_DISP
  95  * 9470: GM107_DISP
  96  */
  97
  98 #define NV50_DISP_CLASS                                              0x00005070
  99 #define NV84_DISP_CLASS                                              0x00008270
 100 #define NVA0_DISP_CLASS                                              0x00008370
 101 #define NV94_DISP_CLASS                                              0x00008870
 102 #define NVA3_DISP_CLASS                                              0x00008570
 103 #define NVD0_DISP_CLASS                                              0x00009070
 104 #define NVE0_DISP_CLASS                                              0x00009170
 105 #define NVF0_DISP_CLASS                                              0x00009270
 106 #define GM107_DISP_CLASS                                             0x00009470
 107
 108 #define NV50_DISP_MTHD                                               0x00000000
 109 #define NV50_DISP_MTHD_HEAD                                          0x00000003
 110
 111 #define NV50_DISP_SCANOUTPOS                                         0x00000000
 112
 113 #define NV50_DISP_SOR_MTHD                                           0x00010000
 114 #define NV50_DISP_SOR_MTHD_TYPE                                      0x0000f000
 115 #define NV50_DISP_SOR_MTHD_HEAD                                      0x00000018
 116 #define NV50_DISP_SOR_MTHD_LINK                                      0x00000004
 117 #define NV50_DISP_SOR_MTHD_OR                                        0x00000003
 118
 119 #define NV50_DISP_SOR_PWR                                            0x00010000
 120 #define NV50_DISP_SOR_PWR_STATE                                      0x00000001
 121 #define NV50_DISP_SOR_PWR_STATE_ON                                   0x00000001
 122 #define NV50_DISP_SOR_PWR_STATE_OFF                                  0x00000000
 123 #define NVA3_DISP_SOR_HDA_ELD                                        0x00010100
 124 #define NV84_DISP_SOR_HDMI_PWR                                       0x00012000
 125 #define NV84_DISP_SOR_HDMI_PWR_STATE                                 0x40000000
 126 #define NV84_DISP_SOR_HDMI_PWR_STATE_OFF                             0x00000000
 127 #define NV84_DISP_SOR_HDMI_PWR_STATE_ON                              0x40000000
 128 #define NV84_DISP_SOR_HDMI_PWR_MAX_AC_PACKET                         0x001f0000
 129 #define NV84_DISP_SOR_HDMI_PWR_REKEY                                 0x0000007f
 130 #define NV50_DISP_SOR_LVDS_SCRIPT                                    0x00013000
 131 #define NV50_DISP_SOR_LVDS_SCRIPT_ID                                 0x0000ffff
 132 #define NV94_DISP_SOR_DP_PWR                                         0x00016000
 133 #define NV94_DISP_SOR_DP_PWR_STATE                                   0x00000001
 134 #define NV94_DISP_SOR_DP_PWR_STATE_OFF                               0x00000000
 135 #define NV94_DISP_SOR_DP_PWR_STATE_ON                                0x00000001
 136
 137 #define NV50_DISP_DAC_MTHD                                           0x00020000
 138 #define NV50_DISP_DAC_MTHD_TYPE                                      0x0000f000
 139 #define NV50_DISP_DAC_MTHD_OR                                        0x00000003
 140
 141 #define NV50_DISP_DAC_PWR                                            0x00020000
 142 #define NV50_DISP_DAC_PWR_HSYNC                                      0x00000001
 143 #define NV50_DISP_DAC_PWR_HSYNC_ON                                   0x00000000
 144 #define NV50_DISP_DAC_PWR_HSYNC_LO                                   0x00000001
 145 #define NV50_DISP_DAC_PWR_VSYNC                                      0x00000004
 146 #define NV50_DISP_DAC_PWR_VSYNC_ON                                   0x00000000
 147 #define NV50_DISP_DAC_PWR_VSYNC_LO                                   0x00000004
 148 #define NV50_DISP_DAC_PWR_DATA                                       0x00000010
 149 #define NV50_DISP_DAC_PWR_DATA_ON                                    0x00000000
 150 #define NV50_DISP_DAC_PWR_DATA_LO                                    0x00000010
 151 #define NV50_DISP_DAC_PWR_STATE                                      0x00000040
 152 #define NV50_DISP_DAC_PWR_STATE_ON                                   0x00000000
 153 #define NV50_DISP_DAC_PWR_STATE_OFF                                  0x00000040
 154 #define NV50_DISP_DAC_LOAD                                           0x00020100
 155 #define NV50_DISP_DAC_LOAD_VALUE                                     0x00000007
 156
 157 #define NV50_DISP_PIOR_MTHD                                          0x00030000
 158 #define NV50_DISP_PIOR_MTHD_TYPE                                     0x0000f000
 159 #define NV50_DISP_PIOR_MTHD_OR                                       0x00000003
 160
 161 #define NV50_DISP_PIOR_PWR                                           0x00030000
 162 #define NV50_DISP_PIOR_PWR_STATE                                     0x00000001
 163 #define NV50_DISP_PIOR_PWR_STATE_ON                                  0x00000001
 164 #define NV50_DISP_PIOR_PWR_STATE_OFF                                 0x00000000
 165 #define NV50_DISP_PIOR_TMDS_PWR                                      0x00032000
 166 #define NV50_DISP_PIOR_TMDS_PWR_STATE                                0x00000001
 167 #define NV50_DISP_PIOR_TMDS_PWR_STATE_ON                             0x00000001
 168 #define NV50_DISP_PIOR_TMDS_PWR_STATE_OFF                            0x00000000
 169 #define NV50_DISP_PIOR_DP_PWR                                        0x00036000
 170 #define NV50_DISP_PIOR_DP_PWR_STATE                                  0x00000001
 171 #define NV50_DISP_PIOR_DP_PWR_STATE_ON                               0x00000001
 172 #define NV50_DISP_PIOR_DP_PWR_STATE_OFF                              0x00000000
 173
 174 struct nv50_display_class {
 175 };
 176
 177 /* 507a: NV50_DISP_CURS
 178  * 827a: NV84_DISP_CURS
 179  * 837a: NVA0_DISP_CURS
 180  * 887a: NV94_DISP_CURS
 181  * 857a: NVA3_DISP_CURS
 182  * 907a: NVD0_DISP_CURS
 183  * 917a: NVE0_DISP_CURS
 184  * 927a: NVF0_DISP_CURS
 185  * 947a: GM107_DISP_CURS
 186  */
 187
 188 #define NV50_DISP_CURS_CLASS                                         0x0000507a
 189 #define NV84_DISP_CURS_CLASS                                         0x0000827a
 190 #define NVA0_DISP_CURS_CLASS                                         0x0000837a
 191 #define NV94_DISP_CURS_CLASS                                         0x0000887a
 192 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
 193 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
 194 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
 195 #define NVF0_DISP_CURS_CLASS                                         0x0000927a
 196 #define GM107_DISP_CURS_CLASS                                        0x0000947a
 197
 198 struct nv50_display_curs_class {
 199         u32 head;
 200 };
 201
 202 /* 507b: NV50_DISP_OIMM
 203  * 827b: NV84_DISP_OIMM
 204  * 837b: NVA0_DISP_OIMM
 205  * 887b: NV94_DISP_OIMM
 206  * 857b: NVA3_DISP_OIMM
 207  * 907b: NVD0_DISP_OIMM
 208  * 917b: NVE0_DISP_OIMM
 209  * 927b: NVE0_DISP_OIMM
 210  * 947b: GM107_DISP_OIMM
 211  */
 212
 213 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
 214 #define NV84_DISP_OIMM_CLASS                                         0x0000827b
 215 #define NVA0_DISP_OIMM_CLASS                                         0x0000837b
 216 #define NV94_DISP_OIMM_CLASS                                         0x0000887b
 217 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
 218 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
 219 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
 220 #define NVF0_DISP_OIMM_CLASS                                         0x0000927b
 221 #define GM107_DISP_OIMM_CLASS                                        0x0000947b
 222
 223 struct nv50_display_oimm_class {
 224         u32 head;
 225 };
 226
 227 /* 507c: NV50_DISP_SYNC
 228  * 827c: NV84_DISP_SYNC
 229  * 837c: NVA0_DISP_SYNC
 230  * 887c: NV94_DISP_SYNC
 231  * 857c: NVA3_DISP_SYNC
 232  * 907c: NVD0_DISP_SYNC
 233  * 917c: NVE0_DISP_SYNC
 234  * 927c: NVF0_DISP_SYNC
 235  * 947c: GM107_DISP_SYNC
 236  */
 237
 238 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
 239 #define NV84_DISP_SYNC_CLASS                                         0x0000827c
 240 #define NVA0_DISP_SYNC_CLASS                                         0x0000837c
 241 #define NV94_DISP_SYNC_CLASS                                         0x0000887c
 242 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 243 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 244 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
 245 #define NVF0_DISP_SYNC_CLASS                                         0x0000927c
 246 #define GM107_DISP_SYNC_CLASS                                        0x0000947c
 247
 248 struct nv50_display_sync_class {
 249         u32 pushbuf;
 250         u32 head;
 251 };
 252
 253 /* 507d: NV50_DISP_MAST
 254  * 827d: NV84_DISP_MAST
 255  * 837d: NVA0_DISP_MAST
 256  * 887d: NV94_DISP_MAST
 257  * 857d: NVA3_DISP_MAST
 258  * 907d: NVD0_DISP_MAST
 259  * 917d: NVE0_DISP_MAST
 260  * 927d: NVF0_DISP_MAST
 261  * 947d: GM107_DISP_MAST
 262  */
 263
 264 #define NV50_DISP_MAST_CLASS                                         0x0000507d
 265 #define NV84_DISP_MAST_CLASS                                         0x0000827d
 266 #define NVA0_DISP_MAST_CLASS                                         0x0000837d
 267 #define NV94_DISP_MAST_CLASS                                         0x0000887d
 268 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 269 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 270 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
 271 #define NVF0_DISP_MAST_CLASS                                         0x0000927d
 272 #define GM107_DISP_MAST_CLASS                                        0x0000947d
 273
 274 struct nv50_display_mast_class {
 275         u32 pushbuf;
 276 };
 277
 278 /* 507e: NV50_DISP_OVLY
 279  * 827e: NV84_DISP_OVLY
 280  * 837e: NVA0_DISP_OVLY
 281  * 887e: NV94_DISP_OVLY
 282  * 857e: NVA3_DISP_OVLY
 283  * 907e: NVD0_DISP_OVLY
 284  * 917e: NVE0_DISP_OVLY
 285  * 927e: NVF0_DISP_OVLY
 286  * 947e: GM107_DISP_OVLY
 287  */
 288
 289 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
 290 #define NV84_DISP_OVLY_CLASS                                         0x0000827e
 291 #define NVA0_DISP_OVLY_CLASS                                         0x0000837e
 292 #define NV94_DISP_OVLY_CLASS                                         0x0000887e
 293 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 294 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 295 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
 296 #define NVF0_DISP_OVLY_CLASS                                         0x0000927e
 297 #define GM107_DISP_OVLY_CLASS                                        0x0000947e
 298
 299 struct nv50_display_ovly_class {
 300         u32 pushbuf;
 301         u32 head;
 302 };
 303
 304 #endif