2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/client.h>
26 #include <core/device.h>
27 #include <core/gpuobj.h>
28 #include <core/class.h>
29 #include <nvif/unpack.h>
30 #include <nvif/class.h>
32 #include <subdev/fb.h>
36 struct nvc0_dmaobj_priv {
37 struct nouveau_dmaobj base;
43 nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
44 struct nouveau_object *parent,
45 struct nouveau_gpuobj **pgpuobj)
47 struct nvc0_dmaobj_priv *priv = (void *)dmaobj;
50 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
51 switch (nv_mclass(parent->parent)) {
52 case NVA3_DISP_MAST_CLASS:
53 case NVA3_DISP_SYNC_CLASS:
54 case NVA3_DISP_OVLY_CLASS:
62 ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
64 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
65 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
66 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
67 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
68 upper_32_bits(priv->base.start));
69 nv_wo32(*pgpuobj, 0x10, 0x00000000);
70 nv_wo32(*pgpuobj, 0x14, priv->flags5);
77 nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
78 struct nouveau_oclass *oclass, void *data, u32 size,
79 struct nouveau_object **pobject)
81 struct nouveau_dmaeng *dmaeng = (void *)engine;
83 struct gf100_dma_v0 v0;
85 struct nvc0_dmaobj_priv *priv;
89 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
90 *pobject = nv_object(priv);
95 nv_ioctl(parent, "create gf100 dma size %d\n", size);
96 if (nvif_unpack(args->v0, 0, 0, false)) {
97 nv_ioctl(parent, "create gf100 dma vers %d priv %d kind %02x\n",
98 args->v0.version, args->v0.priv, args->v0.kind);
100 user = args->v0.priv;
104 if (priv->base.target != NV_MEM_TARGET_VM) {
105 kind = GF100_DMA_V0_KIND_PITCH;
106 user = GF100_DMA_V0_PRIV_US;
109 kind = GF100_DMA_V0_KIND_VM;
110 user = GF100_DMA_V0_PRIV_VM;
118 priv->flags0 |= (kind << 22) | (user << 20);
119 priv->flags5 |= (unkn << 16);
121 switch (priv->base.target) {
122 case NV_MEM_TARGET_VM:
123 priv->flags0 |= 0x00000000;
125 case NV_MEM_TARGET_VRAM:
126 priv->flags0 |= 0x00010000;
128 case NV_MEM_TARGET_PCI:
129 priv->flags0 |= 0x00020000;
131 case NV_MEM_TARGET_PCI_NOSNOOP:
132 priv->flags0 |= 0x00030000;
138 switch (priv->base.access) {
139 case NV_MEM_ACCESS_VM:
141 case NV_MEM_ACCESS_RO:
142 priv->flags0 |= 0x00040000;
144 case NV_MEM_ACCESS_WO:
145 case NV_MEM_ACCESS_RW:
146 priv->flags0 |= 0x00080000;
150 return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
153 static struct nouveau_ofuncs
154 nvc0_dmaobj_ofuncs = {
155 .ctor = nvc0_dmaobj_ctor,
156 .dtor = _nvkm_dmaobj_dtor,
157 .init = _nvkm_dmaobj_init,
158 .fini = _nvkm_dmaobj_fini,
161 static struct nouveau_oclass
162 nvc0_dmaeng_sclass[] = {
163 { NV_DMA_FROM_MEMORY, &nvc0_dmaobj_ofuncs },
164 { NV_DMA_TO_MEMORY, &nvc0_dmaobj_ofuncs },
165 { NV_DMA_IN_MEMORY, &nvc0_dmaobj_ofuncs },
169 struct nouveau_oclass *
170 nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
171 .base.handle = NV_ENGINE(DMAOBJ, 0xc0),
172 .base.ofuncs = &(struct nouveau_ofuncs) {
173 .ctor = _nvkm_dmaeng_ctor,
174 .dtor = _nvkm_dmaeng_dtor,
175 .init = _nvkm_dmaeng_init,
176 .fini = _nvkm_dmaeng_fini,
178 .sclass = nvc0_dmaeng_sclass,
179 .bind = nvc0_dmaobj_bind,