drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 /* PPGTT stuff */
  32 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  33
  34 #define GEN6_PDE_VALID                  (1 << 0)
  35 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  36 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  37
  38 #define GEN6_PTE_VALID                  (1 << 0)
  39 #define GEN6_PTE_UNCACHED               (1 << 1)
  40 #define HSW_PTE_UNCACHED                (0)
  41 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  42 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  43 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  44
  45 static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  46                                       dma_addr_t addr,
  47                                       enum i915_cache_level level)
  48 {
  49         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  50         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  51
  52         switch (level) {
  53         case I915_CACHE_LLC_MLC:
  54                 pte |= GEN6_PTE_CACHE_LLC_MLC;
  55                 break;
  56         case I915_CACHE_LLC:
  57                 pte |= GEN6_PTE_CACHE_LLC;
  58                 break;
  59         case I915_CACHE_NONE:
  60                 pte |= GEN6_PTE_UNCACHED;
  61                 break;
  62         default:
  63                 BUG();
  64         }
  65
  66         return pte;
  67 }
  68
  69 #define BYT_PTE_WRITEABLE               (1 << 1)
  70 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
  71
  72 static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
  73                                      dma_addr_t addr,
  74                                      enum i915_cache_level level)
  75 {
  76         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  77         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  78
  79         /* Mark the page as writeable.  Other platforms don't have a
  80          * setting for read-only/writable, so this matches that behavior.
  81          */
  82         pte |= BYT_PTE_WRITEABLE;
  83
  84         if (level != I915_CACHE_NONE)
  85                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
  86
  87         return pte;
  88 }
  89
  90 static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,
  91                                      dma_addr_t addr,
  92                                      enum i915_cache_level level)
  93 {
  94         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  95         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  96
  97         if (level != I915_CACHE_NONE)
  98                 pte |= GEN6_PTE_CACHE_LLC;
  99
 100         return pte;
 101 }
 102
 103 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 104 {
 105         struct drm_i915_private *dev_priv = ppgtt->dev->dev_private;
 106         gen6_gtt_pte_t __iomem *pd_addr;
 107         uint32_t pd_entry;
 108         int i;
 109
 110         WARN_ON(ppgtt->pd_offset & 0x3f);
 111         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 112                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 113         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 114                 dma_addr_t pt_addr;
 115
 116                 pt_addr = ppgtt->pt_dma_addr[i];
 117                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 118                 pd_entry |= GEN6_PDE_VALID;
 119
 120                 writel(pd_entry, pd_addr + i);
 121         }
 122         readl(pd_addr);
 123 }
 124
 125 static int gen6_ppgtt_enable(struct drm_device *dev)
 126 {
 127         drm_i915_private_t *dev_priv = dev->dev_private;
 128         uint32_t pd_offset;
 129         struct intel_ring_buffer *ring;
 130         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 131         int i;
 132
 133         BUG_ON(ppgtt->pd_offset & 0x3f);
 134
 135         gen6_write_pdes(ppgtt);
 136
 137         pd_offset = ppgtt->pd_offset;
 138         pd_offset /= 64; /* in cachelines, */
 139         pd_offset <<= 16;
 140
 141         if (INTEL_INFO(dev)->gen == 6) {
 142                 uint32_t ecochk, gab_ctl, ecobits;
 143
 144                 ecobits = I915_READ(GAC_ECO_BITS);
 145                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 146                                          ECOBITS_PPGTT_CACHE64B);
 147
 148                 gab_ctl = I915_READ(GAB_CTL);
 149                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 150
 151                 ecochk = I915_READ(GAM_ECOCHK);
 152                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 153                                        ECOCHK_PPGTT_CACHE64B);
 154                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 155         } else if (INTEL_INFO(dev)->gen >= 7) {
 156                 uint32_t ecochk, ecobits;
 157
 158                 ecobits = I915_READ(GAC_ECO_BITS);
 159                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 160
 161                 ecochk = I915_READ(GAM_ECOCHK);
 162                 if (IS_HASWELL(dev)) {
 163                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 164                 } else {
 165                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 166                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 167                 }
 168                 I915_WRITE(GAM_ECOCHK, ecochk);
 169                 /* GFX_MODE is per-ring on gen7+ */
 170         }
 171
 172         for_each_ring(ring, dev_priv, i) {
 173                 if (INTEL_INFO(dev)->gen >= 7)
 174                         I915_WRITE(RING_MODE_GEN7(ring),
 175                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 176
 177                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 178                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 179         }
 180         return 0;
 181 }
 182
 183 /* PPGTT support for Sandybdrige/Gen6 and later */
 184 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 185                                    unsigned first_entry,
 186                                    unsigned num_entries)
 187 {
 188         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 189         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 190         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 191         unsigned last_pte, i;
 192
 193         scratch_pte = ppgtt->pte_encode(ppgtt->dev,
 194                                         ppgtt->scratch_page_dma_addr,
 195                                         I915_CACHE_LLC);
 196
 197         while (num_entries) {
 198                 last_pte = first_pte + num_entries;
 199                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 200                         last_pte = I915_PPGTT_PT_ENTRIES;
 201
 202                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 203
 204                 for (i = first_pte; i < last_pte; i++)
 205                         pt_vaddr[i] = scratch_pte;
 206
 207                 kunmap_atomic(pt_vaddr);
 208
 209                 num_entries -= last_pte - first_pte;
 210                 first_pte = 0;
 211                 act_pt++;
 212         }
 213 }
 214
 215 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 216                                       struct sg_table *pages,
 217                                       unsigned first_entry,
 218                                       enum i915_cache_level cache_level)
 219 {
 220         gen6_gtt_pte_t *pt_vaddr;
 221         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 222         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 223         struct sg_page_iter sg_iter;
 224
 225         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 226         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 227                 dma_addr_t page_addr;
 228
 229                 page_addr = sg_page_iter_dma_address(&sg_iter);
 230                 pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,
 231                                                       cache_level);
 232                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 233                         kunmap_atomic(pt_vaddr);
 234                         act_pt++;
 235                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 236                         act_pte = 0;
 237
 238                 }
 239         }
 240         kunmap_atomic(pt_vaddr);
 241 }
 242
 243 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 244 {
 245         int i;
 246
 247         if (ppgtt->pt_dma_addr) {
 248                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 249                         pci_unmap_page(ppgtt->dev->pdev,
 250                                        ppgtt->pt_dma_addr[i],
 251                                        4096, PCI_DMA_BIDIRECTIONAL);
 252         }
 253
 254         kfree(ppgtt->pt_dma_addr);
 255         for (i = 0; i < ppgtt->num_pd_entries; i++)
 256                 __free_page(ppgtt->pt_pages[i]);
 257         kfree(ppgtt->pt_pages);
 258         kfree(ppgtt);
 259 }
 260
 261 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 262 {
 263         struct drm_device *dev = ppgtt->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         unsigned first_pd_entry_in_global_pt;
 266         int i;
 267         int ret = -ENOMEM;
 268
 269         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 270          * entries. For aliasing ppgtt support we just steal them at the end for
 271          * now. */
 272         first_pd_entry_in_global_pt =
 273                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 274
 275         if (IS_HASWELL(dev)) {
 276                 ppgtt->pte_encode = hsw_pte_encode;
 277         } else if (IS_VALLEYVIEW(dev)) {
 278                 ppgtt->pte_encode = byt_pte_encode;
 279         } else {
 280                 ppgtt->pte_encode = gen6_pte_encode;
 281         }
 282         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 283         ppgtt->enable = gen6_ppgtt_enable;
 284         ppgtt->clear_range = gen6_ppgtt_clear_range;
 285         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 286         ppgtt->cleanup = gen6_ppgtt_cleanup;
 287         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 288                                   GFP_KERNEL);
 289         if (!ppgtt->pt_pages)
 290                 return -ENOMEM;
 291
 292         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 293                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 294                 if (!ppgtt->pt_pages[i])
 295                         goto err_pt_alloc;
 296         }
 297
 298         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 299                                      GFP_KERNEL);
 300         if (!ppgtt->pt_dma_addr)
 301                 goto err_pt_alloc;
 302
 303         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 304                 dma_addr_t pt_addr;
 305
 306                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 307                                        PCI_DMA_BIDIRECTIONAL);
 308
 309                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 310                         ret = -EIO;
 311                         goto err_pd_pin;
 312
 313                 }
 314                 ppgtt->pt_dma_addr[i] = pt_addr;
 315         }
 316
 317         ppgtt->clear_range(ppgtt, 0,
 318                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 319
 320         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 321
 322         return 0;
 323
 324 err_pd_pin:
 325         if (ppgtt->pt_dma_addr) {
 326                 for (i--; i >= 0; i--)
 327                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 328                                        4096, PCI_DMA_BIDIRECTIONAL);
 329         }
 330 err_pt_alloc:
 331         kfree(ppgtt->pt_dma_addr);
 332         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 333                 if (ppgtt->pt_pages[i])
 334                         __free_page(ppgtt->pt_pages[i]);
 335         }
 336         kfree(ppgtt->pt_pages);
 337
 338         return ret;
 339 }
 340
 341 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 342 {
 343         struct drm_i915_private *dev_priv = dev->dev_private;
 344         struct i915_hw_ppgtt *ppgtt;
 345         int ret;
 346
 347         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 348         if (!ppgtt)
 349                 return -ENOMEM;
 350
 351         ppgtt->dev = dev;
 352         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 353
 354         if (INTEL_INFO(dev)->gen < 8)
 355                 ret = gen6_ppgtt_init(ppgtt);
 356         else
 357                 BUG();
 358
 359         if (ret)
 360                 kfree(ppgtt);
 361         else
 362                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 363
 364         return ret;
 365 }
 366
 367 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 368 {
 369         struct drm_i915_private *dev_priv = dev->dev_private;
 370         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 371
 372         if (!ppgtt)
 373                 return;
 374
 375         ppgtt->cleanup(ppgtt);
 376         dev_priv->mm.aliasing_ppgtt = NULL;
 377 }
 378
 379 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 380                             struct drm_i915_gem_object *obj,
 381                             enum i915_cache_level cache_level)
 382 {
 383         ppgtt->insert_entries(ppgtt, obj->pages,
 384                               obj->gtt_space->start >> PAGE_SHIFT,
 385                               cache_level);
 386 }
 387
 388 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 389                               struct drm_i915_gem_object *obj)
 390 {
 391         ppgtt->clear_range(ppgtt,
 392                            obj->gtt_space->start >> PAGE_SHIFT,
 393                            obj->base.size >> PAGE_SHIFT);
 394 }
 395
 396 extern int intel_iommu_gfx_mapped;
 397 /* Certain Gen5 chipsets require require idling the GPU before
 398  * unmapping anything from the GTT when VT-d is enabled.
 399  */
 400 static inline bool needs_idle_maps(struct drm_device *dev)
 401 {
 402 #ifdef CONFIG_INTEL_IOMMU
 403         /* Query intel_iommu to see if we need the workaround. Presumably that
 404          * was loaded first.
 405          */
 406         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 407                 return true;
 408 #endif
 409         return false;
 410 }
 411
 412 static bool do_idling(struct drm_i915_private *dev_priv)
 413 {
 414         bool ret = dev_priv->mm.interruptible;
 415
 416         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 417                 dev_priv->mm.interruptible = false;
 418                 if (i915_gpu_idle(dev_priv->dev)) {
 419                         DRM_ERROR("Couldn't idle GPU\n");
 420                         /* Wait a bit, in hopes it avoids the hang */
 421                         udelay(10);
 422                 }
 423         }
 424
 425         return ret;
 426 }
 427
 428 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 429 {
 430         if (unlikely(dev_priv->gtt.do_idle_maps))
 431                 dev_priv->mm.interruptible = interruptible;
 432 }
 433
 434 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 435 {
 436         struct drm_i915_private *dev_priv = dev->dev_private;
 437         struct drm_i915_gem_object *obj;
 438
 439         /* First fill our portion of the GTT with scratch pages */
 440         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 441                                       dev_priv->gtt.total / PAGE_SIZE);
 442
 443         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 444                 i915_gem_clflush_object(obj);
 445                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 446         }
 447
 448         i915_gem_chipset_flush(dev);
 449 }
 450
 451 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 452 {
 453         if (obj->has_dma_mapping)
 454                 return 0;
 455
 456         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 457                         obj->pages->sgl, obj->pages->nents,
 458                         PCI_DMA_BIDIRECTIONAL))
 459                 return -ENOSPC;
 460
 461         return 0;
 462 }
 463
 464 /*
 465  * Binds an object into the global gtt with the specified cache level. The object
 466  * will be accessible to the GPU via commands whose operands reference offsets
 467  * within the global GTT as well as accessible by the GPU through the GMADR
 468  * mapped BAR (dev_priv->mm.gtt->gtt).
 469  */
 470 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 471                                      struct sg_table *st,
 472                                      unsigned int first_entry,
 473                                      enum i915_cache_level level)
 474 {
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476         gen6_gtt_pte_t __iomem *gtt_entries =
 477                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 478         int i = 0;
 479         struct sg_page_iter sg_iter;
 480         dma_addr_t addr;
 481
 482         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 483                 addr = sg_page_iter_dma_address(&sg_iter);
 484                 iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),
 485                           &gtt_entries[i]);
 486                 i++;
 487         }
 488
 489         /* XXX: This serves as a posting read to make sure that the PTE has
 490          * actually been updated. There is some concern that even though
 491          * registers and PTEs are within the same BAR that they are potentially
 492          * of NUMA access patterns. Therefore, even with the way we assume
 493          * hardware should work, we must keep this posting read for paranoia.
 494          */
 495         if (i != 0)
 496                 WARN_ON(readl(&gtt_entries[i-1])
 497                         != dev_priv->gtt.pte_encode(dev, addr, level));
 498
 499         /* This next bit makes the above posting read even more important. We
 500          * want to flush the TLBs only after we're certain all the PTE updates
 501          * have finished.
 502          */
 503         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 504         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 505 }
 506
 507 static void gen6_ggtt_clear_range(struct drm_device *dev,
 508                                   unsigned int first_entry,
 509                                   unsigned int num_entries)
 510 {
 511         struct drm_i915_private *dev_priv = dev->dev_private;
 512         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 513                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 514         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 515         int i;
 516
 517         if (WARN(num_entries > max_entries,
 518                  "First entry = %d; Num entries = %d (max=%d)\n",
 519                  first_entry, num_entries, max_entries))
 520                 num_entries = max_entries;
 521
 522         scratch_pte = dev_priv->gtt.pte_encode(dev,
 523                                                dev_priv->gtt.scratch_page_dma,
 524                                                I915_CACHE_LLC);
 525         for (i = 0; i < num_entries; i++)
 526                 iowrite32(scratch_pte, &gtt_base[i]);
 527         readl(gtt_base);
 528 }
 529
 530
 531 static void i915_ggtt_insert_entries(struct drm_device *dev,
 532                                      struct sg_table *st,
 533                                      unsigned int pg_start,
 534                                      enum i915_cache_level cache_level)
 535 {
 536         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 537                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 538
 539         intel_gtt_insert_sg_entries(st, pg_start, flags);
 540
 541 }
 542
 543 static void i915_ggtt_clear_range(struct drm_device *dev,
 544                                   unsigned int first_entry,
 545                                   unsigned int num_entries)
 546 {
 547         intel_gtt_clear_range(first_entry, num_entries);
 548 }
 549
 550
 551 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 552                               enum i915_cache_level cache_level)
 553 {
 554         struct drm_device *dev = obj->base.dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556
 557         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 558                                          obj->gtt_space->start >> PAGE_SHIFT,
 559                                          cache_level);
 560
 561         obj->has_global_gtt_mapping = 1;
 562 }
 563
 564 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 565 {
 566         struct drm_device *dev = obj->base.dev;
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568
 569         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 570                                       obj->gtt_space->start >> PAGE_SHIFT,
 571                                       obj->base.size >> PAGE_SHIFT);
 572
 573         obj->has_global_gtt_mapping = 0;
 574 }
 575
 576 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 577 {
 578         struct drm_device *dev = obj->base.dev;
 579         struct drm_i915_private *dev_priv = dev->dev_private;
 580         bool interruptible;
 581
 582         interruptible = do_idling(dev_priv);
 583
 584         if (!obj->has_dma_mapping)
 585                 dma_unmap_sg(&dev->pdev->dev,
 586                              obj->pages->sgl, obj->pages->nents,
 587                              PCI_DMA_BIDIRECTIONAL);
 588
 589         undo_idling(dev_priv, interruptible);
 590 }
 591
 592 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 593                                   unsigned long color,
 594                                   unsigned long *start,
 595                                   unsigned long *end)
 596 {
 597         if (node->color != color)
 598                 *start += 4096;
 599
 600         if (!list_empty(&node->node_list)) {
 601                 node = list_entry(node->node_list.next,
 602                                   struct drm_mm_node,
 603                                   node_list);
 604                 if (node->allocated && node->color != color)
 605                         *end -= 4096;
 606         }
 607 }
 608 void i915_gem_setup_global_gtt(struct drm_device *dev,
 609                                unsigned long start,
 610                                unsigned long mappable_end,
 611                                unsigned long end)
 612 {
 613         /* Let GEM Manage all of the aperture.
 614          *
 615          * However, leave one page at the end still bound to the scratch page.
 616          * There are a number of places where the hardware apparently prefetches
 617          * past the end of the object, and we've seen multiple hangs with the
 618          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 619          * aperture.  One page should be enough to keep any prefetching inside
 620          * of the aperture.
 621          */
 622         drm_i915_private_t *dev_priv = dev->dev_private;
 623         struct drm_mm_node *entry;
 624         struct drm_i915_gem_object *obj;
 625         unsigned long hole_start, hole_end;
 626
 627         BUG_ON(mappable_end > end);
 628
 629         /* Subtract the guard page ... */
 630         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 631         if (!HAS_LLC(dev))
 632                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 633
 634         /* Mark any preallocated objects as occupied */
 635         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 636                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 637                               obj->gtt_offset, obj->base.size);
 638
 639                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 640                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 641                                                      obj->gtt_offset,
 642                                                      obj->base.size,
 643                                                      false);
 644                 obj->has_global_gtt_mapping = 1;
 645         }
 646
 647         dev_priv->gtt.start = start;
 648         dev_priv->gtt.total = end - start;
 649
 650         /* Clear any non-preallocated blocks */
 651         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 652                              hole_start, hole_end) {
 653                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 654                               hole_start, hole_end);
 655                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 656                                               (hole_end-hole_start) / PAGE_SIZE);
 657         }
 658
 659         /* And finally clear the reserved guard page */
 660         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 661 }
 662
 663 static bool
 664 intel_enable_ppgtt(struct drm_device *dev)
 665 {
 666         if (i915_enable_ppgtt >= 0)
 667                 return i915_enable_ppgtt;
 668
 669 #ifdef CONFIG_INTEL_IOMMU
 670         /* Disable ppgtt on SNB if VT-d is on. */
 671         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 672                 return false;
 673 #endif
 674
 675         return true;
 676 }
 677
 678 void i915_gem_init_global_gtt(struct drm_device *dev)
 679 {
 680         struct drm_i915_private *dev_priv = dev->dev_private;
 681         unsigned long gtt_size, mappable_size;
 682
 683         gtt_size = dev_priv->gtt.total;
 684         mappable_size = dev_priv->gtt.mappable_end;
 685
 686         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 687                 int ret;
 688
 689                 if (INTEL_INFO(dev)->gen <= 7) {
 690                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 691                          * aperture accordingly when using aliasing ppgtt. */
 692                         gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 693                 }
 694
 695                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 696
 697                 ret = i915_gem_init_aliasing_ppgtt(dev);
 698                 if (!ret)
 699                         return;
 700
 701                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 702                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 703                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 704         }
 705         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 706 }
 707
 708 static int setup_scratch_page(struct drm_device *dev)
 709 {
 710         struct drm_i915_private *dev_priv = dev->dev_private;
 711         struct page *page;
 712         dma_addr_t dma_addr;
 713
 714         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 715         if (page == NULL)
 716                 return -ENOMEM;
 717         get_page(page);
 718         set_pages_uc(page, 1);
 719
 720 #ifdef CONFIG_INTEL_IOMMU
 721         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 722                                 PCI_DMA_BIDIRECTIONAL);
 723         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 724                 return -EINVAL;
 725 #else
 726         dma_addr = page_to_phys(page);
 727 #endif
 728         dev_priv->gtt.scratch_page = page;
 729         dev_priv->gtt.scratch_page_dma = dma_addr;
 730
 731         return 0;
 732 }
 733
 734 static void teardown_scratch_page(struct drm_device *dev)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 738         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 739                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 740         put_page(dev_priv->gtt.scratch_page);
 741         __free_page(dev_priv->gtt.scratch_page);
 742 }
 743
 744 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 745 {
 746         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 747         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 748         return snb_gmch_ctl << 20;
 749 }
 750
 751 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 752 {
 753         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 754         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 755         return snb_gmch_ctl << 25; /* 32 MB units */
 756 }
 757
 758 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 759 {
 760         static const int stolen_decoder[] = {
 761                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 762         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 763         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 764         return stolen_decoder[snb_gmch_ctl] << 20;
 765 }
 766
 767 static int gen6_gmch_probe(struct drm_device *dev,
 768                            size_t *gtt_total,
 769                            size_t *stolen,
 770                            phys_addr_t *mappable_base,
 771                            unsigned long *mappable_end)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         phys_addr_t gtt_bus_addr;
 775         unsigned int gtt_size;
 776         u16 snb_gmch_ctl;
 777         int ret;
 778
 779         *mappable_base = pci_resource_start(dev->pdev, 2);
 780         *mappable_end = pci_resource_len(dev->pdev, 2);
 781
 782         /* 64/512MB is the current min/max we actually know of, but this is just
 783          * a coarse sanity check.
 784          */
 785         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 786                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 787                           dev_priv->gtt.mappable_end);
 788                 return -ENXIO;
 789         }
 790
 791         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 792                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 793         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 794         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 795
 796         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 797                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 798         else
 799                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 800
 801         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 802
 803         /* For Modern GENs the PTEs and register space are split in the BAR */
 804         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 805                 (pci_resource_len(dev->pdev, 0) / 2);
 806
 807         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 808         if (!dev_priv->gtt.gsm) {
 809                 DRM_ERROR("Failed to map the gtt page table\n");
 810                 return -ENOMEM;
 811         }
 812
 813         ret = setup_scratch_page(dev);
 814         if (ret)
 815                 DRM_ERROR("Scratch setup failed\n");
 816
 817         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 818         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 819
 820         return ret;
 821 }
 822
 823 static void gen6_gmch_remove(struct drm_device *dev)
 824 {
 825         struct drm_i915_private *dev_priv = dev->dev_private;
 826         iounmap(dev_priv->gtt.gsm);
 827         teardown_scratch_page(dev_priv->dev);
 828 }
 829
 830 static int i915_gmch_probe(struct drm_device *dev,
 831                            size_t *gtt_total,
 832                            size_t *stolen,
 833                            phys_addr_t *mappable_base,
 834                            unsigned long *mappable_end)
 835 {
 836         struct drm_i915_private *dev_priv = dev->dev_private;
 837         int ret;
 838
 839         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 840         if (!ret) {
 841                 DRM_ERROR("failed to set up gmch\n");
 842                 return -EIO;
 843         }
 844
 845         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 846
 847         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 848         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 849         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 850
 851         return 0;
 852 }
 853
 854 static void i915_gmch_remove(struct drm_device *dev)
 855 {
 856         intel_gmch_remove();
 857 }
 858
 859 int i915_gem_gtt_init(struct drm_device *dev)
 860 {
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862         struct i915_gtt *gtt = &dev_priv->gtt;
 863         int ret;
 864
 865         if (INTEL_INFO(dev)->gen <= 5) {
 866                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 867                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 868         } else {
 869                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 870                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 871                 if (IS_HASWELL(dev)) {
 872                         dev_priv->gtt.pte_encode = hsw_pte_encode;
 873                 } else if (IS_VALLEYVIEW(dev)) {
 874                         dev_priv->gtt.pte_encode = byt_pte_encode;
 875                 } else {
 876                         dev_priv->gtt.pte_encode = gen6_pte_encode;
 877                 }
 878         }
 879
 880         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 881                                      &dev_priv->gtt.stolen_size,
 882                                      &gtt->mappable_base,
 883                                      &gtt->mappable_end);
 884         if (ret)
 885                 return ret;
 886
 887         /* GMADR is the PCI mmio aperture into the global GTT. */
 888         DRM_INFO("Memory usable by graphics device = %zdM\n",
 889                  dev_priv->gtt.total >> 20);
 890         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 891                          dev_priv->gtt.mappable_end >> 20);
 892         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 893                          dev_priv->gtt.stolen_size >> 20);
 894
 895         return 0;
 896 }