drivers/gpu/drm/i915/display/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/time.h>
  25
  26 #include "hsw_ips.h"
  27 #include "i915_reg.h"
  28 #include "intel_atomic.h"
  29 #include "intel_atomic_plane.h"
  30 #include "intel_audio.h"
  31 #include "intel_bw.h"
  32 #include "intel_cdclk.h"
  33 #include "intel_crtc.h"
  34 #include "intel_de.h"
  35 #include "intel_dp.h"
  36 #include "intel_display_types.h"
  37 #include "intel_mchbar_regs.h"
  38 #include "intel_pci_config.h"
  39 #include "intel_pcode.h"
  40 #include "intel_psr.h"
  41 #include "intel_vdsc.h"
  42 #include "vlv_sideband.h"
  43
  44 /**
  45  * DOC: CDCLK / RAWCLK
  46  *
  47  * The display engine uses several different clocks to do its work. There
  48  * are two main clocks involved that aren't directly related to the actual
  49  * pixel clock or any symbol/bit clock of the actual output port. These
  50  * are the core display clock (CDCLK) and RAWCLK.
  51  *
  52  * CDCLK clocks most of the display pipe logic, and thus its frequency
  53  * must be high enough to support the rate at which pixels are flowing
  54  * through the pipes. Downscaling must also be accounted as that increases
  55  * the effective pixel rate.
  56  *
  57  * On several platforms the CDCLK frequency can be changed dynamically
  58  * to minimize power consumption for a given display configuration.
  59  * Typically changes to the CDCLK frequency require all the display pipes
  60  * to be shut down while the frequency is being changed.
  61  *
  62  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  63  * DMC will not change the active CDCLK frequency however, so that part
  64  * will still be performed by the driver directly.
  65  *
  66  * Several methods exist to change the CDCLK frequency, which ones are
  67  * supported depends on the platform:
  68  *
  69  * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
  70  * - CD2X divider update. Single pipe can be active as the divider update
  71  *   can be synchronized with the pipe's start of vblank.
  72  * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
  73  * - Squash waveform update. Pipes can be active.
  74  * - Crawl and squash can also be done back to back. Pipes can be active.
  75  *
  76  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  77  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  78  * really need to know about RAWCLK is its frequency so that various
  79  * dividers can be programmed correctly.
  80  */
  81
  82 struct intel_cdclk_funcs {
  83         void (*get_cdclk)(struct drm_i915_private *i915,
  84                           struct intel_cdclk_config *cdclk_config);
  85         void (*set_cdclk)(struct drm_i915_private *i915,
  86                           const struct intel_cdclk_config *cdclk_config,
  87                           enum pipe pipe);
  88         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
  89         u8 (*calc_voltage_level)(int cdclk);
  90 };
  91
  92 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
  93                            struct intel_cdclk_config *cdclk_config)
  94 {
  95         dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
  96 }
  97
  98 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  99                                   const struct intel_cdclk_config *cdclk_config,
 100                                   enum pipe pipe)
 101 {
 102         dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
 103 }
 104
 105 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
 106                                           struct intel_cdclk_state *cdclk_config)
 107 {
 108         return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
 109 }
 110
 111 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 112                                          int cdclk)
 113 {
 114         return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
 115 }
 116
 117 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
 118                                    struct intel_cdclk_config *cdclk_config)
 119 {
 120         cdclk_config->cdclk = 133333;
 121 }
 122
 123 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
 124                                    struct intel_cdclk_config *cdclk_config)
 125 {
 126         cdclk_config->cdclk = 200000;
 127 }
 128
 129 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
 130                                    struct intel_cdclk_config *cdclk_config)
 131 {
 132         cdclk_config->cdclk = 266667;
 133 }
 134
 135 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
 136                                    struct intel_cdclk_config *cdclk_config)
 137 {
 138         cdclk_config->cdclk = 333333;
 139 }
 140
 141 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
 142                                    struct intel_cdclk_config *cdclk_config)
 143 {
 144         cdclk_config->cdclk = 400000;
 145 }
 146
 147 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
 148                                    struct intel_cdclk_config *cdclk_config)
 149 {
 150         cdclk_config->cdclk = 450000;
 151 }
 152
 153 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
 154                            struct intel_cdclk_config *cdclk_config)
 155 {
 156         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 157         u16 hpllcc = 0;
 158
 159         /*
 160          * 852GM/852GMV only supports 133 MHz and the HPLLCC
 161          * encoding is different :(
 162          * FIXME is this the right way to detect 852GM/852GMV?
 163          */
 164         if (pdev->revision == 0x1) {
 165                 cdclk_config->cdclk = 133333;
 166                 return;
 167         }
 168
 169         pci_bus_read_config_word(pdev->bus,
 170                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 171
 172         /* Assume that the hardware is in the high speed state.  This
 173          * should be the default.
 174          */
 175         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 176         case GC_CLOCK_133_200:
 177         case GC_CLOCK_133_200_2:
 178         case GC_CLOCK_100_200:
 179                 cdclk_config->cdclk = 200000;
 180                 break;
 181         case GC_CLOCK_166_250:
 182                 cdclk_config->cdclk = 250000;
 183                 break;
 184         case GC_CLOCK_100_133:
 185                 cdclk_config->cdclk = 133333;
 186                 break;
 187         case GC_CLOCK_133_266:
 188         case GC_CLOCK_133_266_2:
 189         case GC_CLOCK_166_266:
 190                 cdclk_config->cdclk = 266667;
 191                 break;
 192         }
 193 }
 194
 195 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 196                              struct intel_cdclk_config *cdclk_config)
 197 {
 198         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 199         u16 gcfgc = 0;
 200
 201         pci_read_config_word(pdev, GCFGC, &gcfgc);
 202
 203         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 204                 cdclk_config->cdclk = 133333;
 205                 return;
 206         }
 207
 208         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 209         case GC_DISPLAY_CLOCK_333_320_MHZ:
 210                 cdclk_config->cdclk = 333333;
 211                 break;
 212         default:
 213         case GC_DISPLAY_CLOCK_190_200_MHZ:
 214                 cdclk_config->cdclk = 190000;
 215                 break;
 216         }
 217 }
 218
 219 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 220                              struct intel_cdclk_config *cdclk_config)
 221 {
 222         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 223         u16 gcfgc = 0;
 224
 225         pci_read_config_word(pdev, GCFGC, &gcfgc);
 226
 227         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 228                 cdclk_config->cdclk = 133333;
 229                 return;
 230         }
 231
 232         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 233         case GC_DISPLAY_CLOCK_333_320_MHZ:
 234                 cdclk_config->cdclk = 320000;
 235                 break;
 236         default:
 237         case GC_DISPLAY_CLOCK_190_200_MHZ:
 238                 cdclk_config->cdclk = 200000;
 239                 break;
 240         }
 241 }
 242
 243 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 244 {
 245         static const unsigned int blb_vco[8] = {
 246                 [0] = 3200000,
 247                 [1] = 4000000,
 248                 [2] = 5333333,
 249                 [3] = 4800000,
 250                 [4] = 6400000,
 251         };
 252         static const unsigned int pnv_vco[8] = {
 253                 [0] = 3200000,
 254                 [1] = 4000000,
 255                 [2] = 5333333,
 256                 [3] = 4800000,
 257                 [4] = 2666667,
 258         };
 259         static const unsigned int cl_vco[8] = {
 260                 [0] = 3200000,
 261                 [1] = 4000000,
 262                 [2] = 5333333,
 263                 [3] = 6400000,
 264                 [4] = 3333333,
 265                 [5] = 3566667,
 266                 [6] = 4266667,
 267         };
 268         static const unsigned int elk_vco[8] = {
 269                 [0] = 3200000,
 270                 [1] = 4000000,
 271                 [2] = 5333333,
 272                 [3] = 4800000,
 273         };
 274         static const unsigned int ctg_vco[8] = {
 275                 [0] = 3200000,
 276                 [1] = 4000000,
 277                 [2] = 5333333,
 278                 [3] = 6400000,
 279                 [4] = 2666667,
 280                 [5] = 4266667,
 281         };
 282         const unsigned int *vco_table;
 283         unsigned int vco;
 284         u8 tmp = 0;
 285
 286         /* FIXME other chipsets? */
 287         if (IS_GM45(dev_priv))
 288                 vco_table = ctg_vco;
 289         else if (IS_G45(dev_priv))
 290                 vco_table = elk_vco;
 291         else if (IS_I965GM(dev_priv))
 292                 vco_table = cl_vco;
 293         else if (IS_PINEVIEW(dev_priv))
 294                 vco_table = pnv_vco;
 295         else if (IS_G33(dev_priv))
 296                 vco_table = blb_vco;
 297         else
 298                 return 0;
 299
 300         tmp = intel_de_read(dev_priv,
 301                             IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 302
 303         vco = vco_table[tmp & 0x7];
 304         if (vco == 0)
 305                 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
 306                         tmp);
 307         else
 308                 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
 309
 310         return vco;
 311 }
 312
 313 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 314                           struct intel_cdclk_config *cdclk_config)
 315 {
 316         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 317         static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
 318         static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
 319         static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
 320         static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
 321         const u8 *div_table;
 322         unsigned int cdclk_sel;
 323         u16 tmp = 0;
 324
 325         cdclk_config->vco = intel_hpll_vco(dev_priv);
 326
 327         pci_read_config_word(pdev, GCFGC, &tmp);
 328
 329         cdclk_sel = (tmp >> 4) & 0x7;
 330
 331         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 332                 goto fail;
 333
 334         switch (cdclk_config->vco) {
 335         case 3200000:
 336                 div_table = div_3200;
 337                 break;
 338         case 4000000:
 339                 div_table = div_4000;
 340                 break;
 341         case 4800000:
 342                 div_table = div_4800;
 343                 break;
 344         case 5333333:
 345                 div_table = div_5333;
 346                 break;
 347         default:
 348                 goto fail;
 349         }
 350
 351         cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
 352                                                 div_table[cdclk_sel]);
 353         return;
 354
 355 fail:
 356         drm_err(&dev_priv->drm,
 357                 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 358                 cdclk_config->vco, tmp);
 359         cdclk_config->cdclk = 190476;
 360 }
 361
 362 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 363                           struct intel_cdclk_config *cdclk_config)
 364 {
 365         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 366         u16 gcfgc = 0;
 367
 368         pci_read_config_word(pdev, GCFGC, &gcfgc);
 369
 370         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 371         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 372                 cdclk_config->cdclk = 266667;
 373                 break;
 374         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 375                 cdclk_config->cdclk = 333333;
 376                 break;
 377         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 378                 cdclk_config->cdclk = 444444;
 379                 break;
 380         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 381                 cdclk_config->cdclk = 200000;
 382                 break;
 383         default:
 384                 drm_err(&dev_priv->drm,
 385                         "Unknown pnv display core clock 0x%04x\n", gcfgc);
 386                 fallthrough;
 387         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 388                 cdclk_config->cdclk = 133333;
 389                 break;
 390         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 391                 cdclk_config->cdclk = 166667;
 392                 break;
 393         }
 394 }
 395
 396 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 397                              struct intel_cdclk_config *cdclk_config)
 398 {
 399         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 400         static const u8 div_3200[] = { 16, 10,  8 };
 401         static const u8 div_4000[] = { 20, 12, 10 };
 402         static const u8 div_5333[] = { 24, 16, 14 };
 403         const u8 *div_table;
 404         unsigned int cdclk_sel;
 405         u16 tmp = 0;
 406
 407         cdclk_config->vco = intel_hpll_vco(dev_priv);
 408
 409         pci_read_config_word(pdev, GCFGC, &tmp);
 410
 411         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 412
 413         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 414                 goto fail;
 415
 416         switch (cdclk_config->vco) {
 417         case 3200000:
 418                 div_table = div_3200;
 419                 break;
 420         case 4000000:
 421                 div_table = div_4000;
 422                 break;
 423         case 5333333:
 424                 div_table = div_5333;
 425                 break;
 426         default:
 427                 goto fail;
 428         }
 429
 430         cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
 431                                                 div_table[cdclk_sel]);
 432         return;
 433
 434 fail:
 435         drm_err(&dev_priv->drm,
 436                 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 437                 cdclk_config->vco, tmp);
 438         cdclk_config->cdclk = 200000;
 439 }
 440
 441 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 442                            struct intel_cdclk_config *cdclk_config)
 443 {
 444         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 445         unsigned int cdclk_sel;
 446         u16 tmp = 0;
 447
 448         cdclk_config->vco = intel_hpll_vco(dev_priv);
 449
 450         pci_read_config_word(pdev, GCFGC, &tmp);
 451
 452         cdclk_sel = (tmp >> 12) & 0x1;
 453
 454         switch (cdclk_config->vco) {
 455         case 2666667:
 456         case 4000000:
 457         case 5333333:
 458                 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
 459                 break;
 460         case 3200000:
 461                 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
 462                 break;
 463         default:
 464                 drm_err(&dev_priv->drm,
 465                         "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 466                         cdclk_config->vco, tmp);
 467                 cdclk_config->cdclk = 222222;
 468                 break;
 469         }
 470 }
 471
 472 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 473                           struct intel_cdclk_config *cdclk_config)
 474 {
 475         u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
 476         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 477
 478         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 479                 cdclk_config->cdclk = 800000;
 480         else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
 481                 cdclk_config->cdclk = 450000;
 482         else if (freq == LCPLL_CLK_FREQ_450)
 483                 cdclk_config->cdclk = 450000;
 484         else if (IS_HASWELL_ULT(dev_priv))
 485                 cdclk_config->cdclk = 337500;
 486         else
 487                 cdclk_config->cdclk = 540000;
 488 }
 489
 490 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 491 {
 492         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 493                 333333 : 320000;
 494
 495         /*
 496          * We seem to get an unstable or solid color picture at 200MHz.
 497          * Not sure what's wrong. For now use 200MHz only when all pipes
 498          * are off.
 499          */
 500         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 501                 return 400000;
 502         else if (min_cdclk > 266667)
 503                 return freq_320;
 504         else if (min_cdclk > 0)
 505                 return 266667;
 506         else
 507                 return 200000;
 508 }
 509
 510 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 511 {
 512         if (IS_VALLEYVIEW(dev_priv)) {
 513                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 514                         return 2;
 515                 else if (cdclk >= 266667)
 516                         return 1;
 517                 else
 518                         return 0;
 519         } else {
 520                 /*
 521                  * Specs are full of misinformation, but testing on actual
 522                  * hardware has shown that we just need to write the desired
 523                  * CCK divider into the Punit register.
 524                  */
 525                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 526         }
 527 }
 528
 529 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 530                           struct intel_cdclk_config *cdclk_config)
 531 {
 532         u32 val;
 533
 534         vlv_iosf_sb_get(dev_priv,
 535                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 536
 537         cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
 538         cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 539                                                 CCK_DISPLAY_CLOCK_CONTROL,
 540                                                 cdclk_config->vco);
 541
 542         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 543
 544         vlv_iosf_sb_put(dev_priv,
 545                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 546
 547         if (IS_VALLEYVIEW(dev_priv))
 548                 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
 549                         DSPFREQGUAR_SHIFT;
 550         else
 551                 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 552                         DSPFREQGUAR_SHIFT_CHV;
 553 }
 554
 555 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 556 {
 557         unsigned int credits, default_credits;
 558
 559         if (IS_CHERRYVIEW(dev_priv))
 560                 default_credits = PFI_CREDIT(12);
 561         else
 562                 default_credits = PFI_CREDIT(8);
 563
 564         if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 565                 /* CHV suggested value is 31 or 63 */
 566                 if (IS_CHERRYVIEW(dev_priv))
 567                         credits = PFI_CREDIT_63;
 568                 else
 569                         credits = PFI_CREDIT(15);
 570         } else {
 571                 credits = default_credits;
 572         }
 573
 574         /*
 575          * WA - write default credits before re-programming
 576          * FIXME: should we also set the resend bit here?
 577          */
 578         intel_de_write(dev_priv, GCI_CONTROL,
 579                        VGA_FAST_MODE_DISABLE | default_credits);
 580
 581         intel_de_write(dev_priv, GCI_CONTROL,
 582                        VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
 583
 584         /*
 585          * FIXME is this guaranteed to clear
 586          * immediately or should we poll for it?
 587          */
 588         drm_WARN_ON(&dev_priv->drm,
 589                     intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
 590 }
 591
 592 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 593                           const struct intel_cdclk_config *cdclk_config,
 594                           enum pipe pipe)
 595 {
 596         int cdclk = cdclk_config->cdclk;
 597         u32 val, cmd = cdclk_config->voltage_level;
 598         intel_wakeref_t wakeref;
 599
 600         switch (cdclk) {
 601         case 400000:
 602         case 333333:
 603         case 320000:
 604         case 266667:
 605         case 200000:
 606                 break;
 607         default:
 608                 MISSING_CASE(cdclk);
 609                 return;
 610         }
 611
 612         /* There are cases where we can end up here with power domains
 613          * off and a CDCLK frequency other than the minimum, like when
 614          * issuing a modeset without actually changing any display after
 615          * a system suspend.  So grab the display core domain, which covers
 616          * the HW blocks needed for the following programming.
 617          */
 618         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 619
 620         vlv_iosf_sb_get(dev_priv,
 621                         BIT(VLV_IOSF_SB_CCK) |
 622                         BIT(VLV_IOSF_SB_BUNIT) |
 623                         BIT(VLV_IOSF_SB_PUNIT));
 624
 625         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 626         val &= ~DSPFREQGUAR_MASK;
 627         val |= (cmd << DSPFREQGUAR_SHIFT);
 628         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 629         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 630                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 631                      50)) {
 632                 drm_err(&dev_priv->drm,
 633                         "timed out waiting for CDclk change\n");
 634         }
 635
 636         if (cdclk == 400000) {
 637                 u32 divider;
 638
 639                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 640                                             cdclk) - 1;
 641
 642                 /* adjust cdclk divider */
 643                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 644                 val &= ~CCK_FREQUENCY_VALUES;
 645                 val |= divider;
 646                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 647
 648                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 649                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 650                              50))
 651                         drm_err(&dev_priv->drm,
 652                                 "timed out waiting for CDclk change\n");
 653         }
 654
 655         /* adjust self-refresh exit latency value */
 656         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 657         val &= ~0x7f;
 658
 659         /*
 660          * For high bandwidth configs, we set a higher latency in the bunit
 661          * so that the core display fetch happens in time to avoid underruns.
 662          */
 663         if (cdclk == 400000)
 664                 val |= 4500 / 250; /* 4.5 usec */
 665         else
 666                 val |= 3000 / 250; /* 3.0 usec */
 667         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 668
 669         vlv_iosf_sb_put(dev_priv,
 670                         BIT(VLV_IOSF_SB_CCK) |
 671                         BIT(VLV_IOSF_SB_BUNIT) |
 672                         BIT(VLV_IOSF_SB_PUNIT));
 673
 674         intel_update_cdclk(dev_priv);
 675
 676         vlv_program_pfi_credits(dev_priv);
 677
 678         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 679 }
 680
 681 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 682                           const struct intel_cdclk_config *cdclk_config,
 683                           enum pipe pipe)
 684 {
 685         int cdclk = cdclk_config->cdclk;
 686         u32 val, cmd = cdclk_config->voltage_level;
 687         intel_wakeref_t wakeref;
 688
 689         switch (cdclk) {
 690         case 333333:
 691         case 320000:
 692         case 266667:
 693         case 200000:
 694                 break;
 695         default:
 696                 MISSING_CASE(cdclk);
 697                 return;
 698         }
 699
 700         /* There are cases where we can end up here with power domains
 701          * off and a CDCLK frequency other than the minimum, like when
 702          * issuing a modeset without actually changing any display after
 703          * a system suspend.  So grab the display core domain, which covers
 704          * the HW blocks needed for the following programming.
 705          */
 706         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 707
 708         vlv_punit_get(dev_priv);
 709         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 710         val &= ~DSPFREQGUAR_MASK_CHV;
 711         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 712         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 713         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 714                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 715                      50)) {
 716                 drm_err(&dev_priv->drm,
 717                         "timed out waiting for CDclk change\n");
 718         }
 719
 720         vlv_punit_put(dev_priv);
 721
 722         intel_update_cdclk(dev_priv);
 723
 724         vlv_program_pfi_credits(dev_priv);
 725
 726         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 727 }
 728
 729 static int bdw_calc_cdclk(int min_cdclk)
 730 {
 731         if (min_cdclk > 540000)
 732                 return 675000;
 733         else if (min_cdclk > 450000)
 734                 return 540000;
 735         else if (min_cdclk > 337500)
 736                 return 450000;
 737         else
 738                 return 337500;
 739 }
 740
 741 static u8 bdw_calc_voltage_level(int cdclk)
 742 {
 743         switch (cdclk) {
 744         default:
 745         case 337500:
 746                 return 2;
 747         case 450000:
 748                 return 0;
 749         case 540000:
 750                 return 1;
 751         case 675000:
 752                 return 3;
 753         }
 754 }
 755
 756 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 757                           struct intel_cdclk_config *cdclk_config)
 758 {
 759         u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
 760         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 761
 762         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 763                 cdclk_config->cdclk = 800000;
 764         else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
 765                 cdclk_config->cdclk = 450000;
 766         else if (freq == LCPLL_CLK_FREQ_450)
 767                 cdclk_config->cdclk = 450000;
 768         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 769                 cdclk_config->cdclk = 540000;
 770         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 771                 cdclk_config->cdclk = 337500;
 772         else
 773                 cdclk_config->cdclk = 675000;
 774
 775         /*
 776          * Can't read this out :( Let's assume it's
 777          * at least what the CDCLK frequency requires.
 778          */
 779         cdclk_config->voltage_level =
 780                 bdw_calc_voltage_level(cdclk_config->cdclk);
 781 }
 782
 783 static u32 bdw_cdclk_freq_sel(int cdclk)
 784 {
 785         switch (cdclk) {
 786         default:
 787                 MISSING_CASE(cdclk);
 788                 fallthrough;
 789         case 337500:
 790                 return LCPLL_CLK_FREQ_337_5_BDW;
 791         case 450000:
 792                 return LCPLL_CLK_FREQ_450;
 793         case 540000:
 794                 return LCPLL_CLK_FREQ_54O_BDW;
 795         case 675000:
 796                 return LCPLL_CLK_FREQ_675_BDW;
 797         }
 798 }
 799
 800 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 801                           const struct intel_cdclk_config *cdclk_config,
 802                           enum pipe pipe)
 803 {
 804         int cdclk = cdclk_config->cdclk;
 805         int ret;
 806
 807         if (drm_WARN(&dev_priv->drm,
 808                      (intel_de_read(dev_priv, LCPLL_CTL) &
 809                       (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 810                        LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 811                        LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 812                        LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 813                      "trying to change cdclk frequency with cdclk not enabled\n"))
 814                 return;
 815
 816         ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 817         if (ret) {
 818                 drm_err(&dev_priv->drm,
 819                         "failed to inform pcode about cdclk change\n");
 820                 return;
 821         }
 822
 823         intel_de_rmw(dev_priv, LCPLL_CTL,
 824                      0, LCPLL_CD_SOURCE_FCLK);
 825
 826         /*
 827          * According to the spec, it should be enough to poll for this 1 us.
 828          * However, extensive testing shows that this can take longer.
 829          */
 830         if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
 831                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 832                 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
 833
 834         intel_de_rmw(dev_priv, LCPLL_CTL,
 835                      LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
 836
 837         intel_de_rmw(dev_priv, LCPLL_CTL,
 838                      LCPLL_CD_SOURCE_FCLK, 0);
 839
 840         if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
 841                          LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 842                 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
 843
 844         snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
 845                         cdclk_config->voltage_level);
 846
 847         intel_de_write(dev_priv, CDCLK_FREQ,
 848                        DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 849
 850         intel_update_cdclk(dev_priv);
 851 }
 852
 853 static int skl_calc_cdclk(int min_cdclk, int vco)
 854 {
 855         if (vco == 8640000) {
 856                 if (min_cdclk > 540000)
 857                         return 617143;
 858                 else if (min_cdclk > 432000)
 859                         return 540000;
 860                 else if (min_cdclk > 308571)
 861                         return 432000;
 862                 else
 863                         return 308571;
 864         } else {
 865                 if (min_cdclk > 540000)
 866                         return 675000;
 867                 else if (min_cdclk > 450000)
 868                         return 540000;
 869                 else if (min_cdclk > 337500)
 870                         return 450000;
 871                 else
 872                         return 337500;
 873         }
 874 }
 875
 876 static u8 skl_calc_voltage_level(int cdclk)
 877 {
 878         if (cdclk > 540000)
 879                 return 3;
 880         else if (cdclk > 450000)
 881                 return 2;
 882         else if (cdclk > 337500)
 883                 return 1;
 884         else
 885                 return 0;
 886 }
 887
 888 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 889                              struct intel_cdclk_config *cdclk_config)
 890 {
 891         u32 val;
 892
 893         cdclk_config->ref = 24000;
 894         cdclk_config->vco = 0;
 895
 896         val = intel_de_read(dev_priv, LCPLL1_CTL);
 897         if ((val & LCPLL_PLL_ENABLE) == 0)
 898                 return;
 899
 900         if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
 901                 return;
 902
 903         val = intel_de_read(dev_priv, DPLL_CTRL1);
 904
 905         if (drm_WARN_ON(&dev_priv->drm,
 906                         (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 907                                 DPLL_CTRL1_SSC(SKL_DPLL0) |
 908                                 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 909                         DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 910                 return;
 911
 912         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 913         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 914         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 915         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 916         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 917                 cdclk_config->vco = 8100000;
 918                 break;
 919         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 920         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 921                 cdclk_config->vco = 8640000;
 922                 break;
 923         default:
 924                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 925                 break;
 926         }
 927 }
 928
 929 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 930                           struct intel_cdclk_config *cdclk_config)
 931 {
 932         u32 cdctl;
 933
 934         skl_dpll0_update(dev_priv, cdclk_config);
 935
 936         cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
 937
 938         if (cdclk_config->vco == 0)
 939                 goto out;
 940
 941         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
 942
 943         if (cdclk_config->vco == 8640000) {
 944                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 945                 case CDCLK_FREQ_450_432:
 946                         cdclk_config->cdclk = 432000;
 947                         break;
 948                 case CDCLK_FREQ_337_308:
 949                         cdclk_config->cdclk = 308571;
 950                         break;
 951                 case CDCLK_FREQ_540:
 952                         cdclk_config->cdclk = 540000;
 953                         break;
 954                 case CDCLK_FREQ_675_617:
 955                         cdclk_config->cdclk = 617143;
 956                         break;
 957                 default:
 958                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 959                         break;
 960                 }
 961         } else {
 962                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 963                 case CDCLK_FREQ_450_432:
 964                         cdclk_config->cdclk = 450000;
 965                         break;
 966                 case CDCLK_FREQ_337_308:
 967                         cdclk_config->cdclk = 337500;
 968                         break;
 969                 case CDCLK_FREQ_540:
 970                         cdclk_config->cdclk = 540000;
 971                         break;
 972                 case CDCLK_FREQ_675_617:
 973                         cdclk_config->cdclk = 675000;
 974                         break;
 975                 default:
 976                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 977                         break;
 978                 }
 979         }
 980
 981  out:
 982         /*
 983          * Can't read this out :( Let's assume it's
 984          * at least what the CDCLK frequency requires.
 985          */
 986         cdclk_config->voltage_level =
 987                 skl_calc_voltage_level(cdclk_config->cdclk);
 988 }
 989
 990 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 991 static int skl_cdclk_decimal(int cdclk)
 992 {
 993         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 994 }
 995
 996 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 997                                         int vco)
 998 {
 999         bool changed = dev_priv->skl_preferred_vco_freq != vco;
1000
1001         dev_priv->skl_preferred_vco_freq = vco;
1002
1003         if (changed)
1004                 intel_update_max_cdclk(dev_priv);
1005 }
1006
1007 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
1008 {
1009         drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
1010
1011         /*
1012          * We always enable DPLL0 with the lowest link rate possible, but still
1013          * taking into account the VCO required to operate the eDP panel at the
1014          * desired frequency. The usual DP link rates operate with a VCO of
1015          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1016          * The modeset code is responsible for the selection of the exact link
1017          * rate later on, with the constraint of choosing a frequency that
1018          * works with vco.
1019          */
1020         if (vco == 8640000)
1021                 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1022         else
1023                 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1024 }
1025
1026 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
1027 {
1028         intel_de_rmw(dev_priv, DPLL_CTRL1,
1029                      DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1030                      DPLL_CTRL1_SSC(SKL_DPLL0) |
1031                      DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1032                      DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1033                      skl_dpll0_link_rate(dev_priv, vco));
1034         intel_de_posting_read(dev_priv, DPLL_CTRL1);
1035
1036         intel_de_rmw(dev_priv, LCPLL1_CTL,
1037                      0, LCPLL_PLL_ENABLE);
1038
1039         if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1040                 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
1041
1042         dev_priv->display.cdclk.hw.vco = vco;
1043
1044         /* We'll want to keep using the current vco from now on. */
1045         skl_set_preferred_cdclk_vco(dev_priv, vco);
1046 }
1047
1048 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
1049 {
1050         intel_de_rmw(dev_priv, LCPLL1_CTL,
1051                      LCPLL_PLL_ENABLE, 0);
1052
1053         if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1054                 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1055
1056         dev_priv->display.cdclk.hw.vco = 0;
1057 }
1058
1059 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
1060                               int cdclk, int vco)
1061 {
1062         switch (cdclk) {
1063         default:
1064                 drm_WARN_ON(&dev_priv->drm,
1065                             cdclk != dev_priv->display.cdclk.hw.bypass);
1066                 drm_WARN_ON(&dev_priv->drm, vco != 0);
1067                 fallthrough;
1068         case 308571:
1069         case 337500:
1070                 return CDCLK_FREQ_337_308;
1071         case 450000:
1072         case 432000:
1073                 return CDCLK_FREQ_450_432;
1074         case 540000:
1075                 return CDCLK_FREQ_540;
1076         case 617143:
1077         case 675000:
1078                 return CDCLK_FREQ_675_617;
1079         }
1080 }
1081
1082 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1083                           const struct intel_cdclk_config *cdclk_config,
1084                           enum pipe pipe)
1085 {
1086         int cdclk = cdclk_config->cdclk;
1087         int vco = cdclk_config->vco;
1088         u32 freq_select, cdclk_ctl;
1089         int ret;
1090
1091         /*
1092          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1093          * unsupported on SKL. In theory this should never happen since only
1094          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1095          * supported on SKL either, see the above WA. WARN whenever trying to
1096          * use the corresponding VCO freq as that always leads to using the
1097          * minimum 308MHz CDCLK.
1098          */
1099         drm_WARN_ON_ONCE(&dev_priv->drm,
1100                          IS_SKYLAKE(dev_priv) && vco == 8640000);
1101
1102         ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1103                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1104                                 SKL_CDCLK_READY_FOR_CHANGE,
1105                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1106         if (ret) {
1107                 drm_err(&dev_priv->drm,
1108                         "Failed to inform PCU about cdclk change (%d)\n", ret);
1109                 return;
1110         }
1111
1112         freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1113
1114         if (dev_priv->display.cdclk.hw.vco != 0 &&
1115             dev_priv->display.cdclk.hw.vco != vco)
1116                 skl_dpll0_disable(dev_priv);
1117
1118         cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1119
1120         if (dev_priv->display.cdclk.hw.vco != vco) {
1121                 /* Wa Display #1183: skl,kbl,cfl */
1122                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1123                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1124                 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1125         }
1126
1127         /* Wa Display #1183: skl,kbl,cfl */
1128         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1129         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1130         intel_de_posting_read(dev_priv, CDCLK_CTL);
1131
1132         if (dev_priv->display.cdclk.hw.vco != vco)
1133                 skl_dpll0_enable(dev_priv, vco);
1134
1135         /* Wa Display #1183: skl,kbl,cfl */
1136         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1137         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1138
1139         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1140         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1141
1142         /* Wa Display #1183: skl,kbl,cfl */
1143         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1144         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1145         intel_de_posting_read(dev_priv, CDCLK_CTL);
1146
1147         /* inform PCU of the change */
1148         snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1149                         cdclk_config->voltage_level);
1150
1151         intel_update_cdclk(dev_priv);
1152 }
1153
1154 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1155 {
1156         u32 cdctl, expected;
1157
1158         /*
1159          * check if the pre-os initialized the display
1160          * There is SWF18 scratchpad register defined which is set by the
1161          * pre-os which can be used by the OS drivers to check the status
1162          */
1163         if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1164                 goto sanitize;
1165
1166         intel_update_cdclk(dev_priv);
1167         intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1168
1169         /* Is PLL enabled and locked ? */
1170         if (dev_priv->display.cdclk.hw.vco == 0 ||
1171             dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
1172                 goto sanitize;
1173
1174         /* DPLL okay; verify the cdclock
1175          *
1176          * Noticed in some instances that the freq selection is correct but
1177          * decimal part is programmed wrong from BIOS where pre-os does not
1178          * enable display. Verify the same as well.
1179          */
1180         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1181         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1182                 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
1183         if (cdctl == expected)
1184                 /* All well; nothing to sanitize */
1185                 return;
1186
1187 sanitize:
1188         drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1189
1190         /* force cdclk programming */
1191         dev_priv->display.cdclk.hw.cdclk = 0;
1192         /* force full PLL disable + enable */
1193         dev_priv->display.cdclk.hw.vco = ~0;
1194 }
1195
1196 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1197 {
1198         struct intel_cdclk_config cdclk_config;
1199
1200         skl_sanitize_cdclk(dev_priv);
1201
1202         if (dev_priv->display.cdclk.hw.cdclk != 0 &&
1203             dev_priv->display.cdclk.hw.vco != 0) {
1204                 /*
1205                  * Use the current vco as our initial
1206                  * guess as to what the preferred vco is.
1207                  */
1208                 if (dev_priv->skl_preferred_vco_freq == 0)
1209                         skl_set_preferred_cdclk_vco(dev_priv,
1210                                                     dev_priv->display.cdclk.hw.vco);
1211                 return;
1212         }
1213
1214         cdclk_config = dev_priv->display.cdclk.hw;
1215
1216         cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1217         if (cdclk_config.vco == 0)
1218                 cdclk_config.vco = 8100000;
1219         cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1220         cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1221
1222         skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1223 }
1224
1225 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1226 {
1227         struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
1228
1229         cdclk_config.cdclk = cdclk_config.bypass;
1230         cdclk_config.vco = 0;
1231         cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1232
1233         skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1234 }
1235
1236 struct intel_cdclk_vals {
1237         u32 cdclk;
1238         u16 refclk;
1239         u16 waveform;
1240         u8 ratio;
1241 };
1242
1243 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1244         { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1245         { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1246         { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1247         { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1248         { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1249         {}
1250 };
1251
1252 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1253         { .refclk = 19200, .cdclk =  79200, .ratio = 33 },
1254         { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1255         { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1256         {}
1257 };
1258
1259 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1260         { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1261         { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1262         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1263         { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1264         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1265         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1266
1267         { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1268         { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1269         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1270         { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1271         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1272         { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1273
1274         { .refclk = 38400, .cdclk = 172800, .ratio =  9 },
1275         { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1276         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1277         { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1278         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1279         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1280         {}
1281 };
1282
1283 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1284         { .refclk = 19200, .cdclk = 172800, .ratio =  36 },
1285         { .refclk = 19200, .cdclk = 192000, .ratio =  40 },
1286         { .refclk = 19200, .cdclk = 307200, .ratio =  64 },
1287         { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1288         { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1289         { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1290
1291         { .refclk = 24000, .cdclk = 180000, .ratio =  30 },
1292         { .refclk = 24000, .cdclk = 192000, .ratio =  32 },
1293         { .refclk = 24000, .cdclk = 312000, .ratio =  52 },
1294         { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1295         { .refclk = 24000, .cdclk = 552000, .ratio =  92 },
1296         { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1297
1298         { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1299         { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1300         { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1301         { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1302         { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1303         { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1304         {}
1305 };
1306
1307 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1308         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1309         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1310         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1311
1312         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1313         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1314         { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1315
1316         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1317         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1318         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1319         {}
1320 };
1321
1322 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1323         { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1324         { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1325         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1326         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1327         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1328
1329         { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1330         { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1331         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1332         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1333         { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1334
1335         { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1336         { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1337         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1338         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1339         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1340         {}
1341 };
1342
1343 static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1344         { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1345         { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1346         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1347         { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1348         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1349         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1350
1351         { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1352         { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1353         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1354         { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1355         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1356         { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1357
1358         { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1359         { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1360         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1361         { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1362         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1363         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1364         {}
1365 };
1366
1367 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1368         { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1369         { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1370         { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1371         { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1372         { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1373         { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1374         { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1375         { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1376         { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1377         { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1378         { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1379         { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1380         { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1381         {}
1382 };
1383
1384 static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1385         { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1386         { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1387         { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1388         { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1389         { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1390         { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1391         {}
1392 };
1393
1394 static const struct intel_cdclk_vals lnl_cdclk_table[] = {
1395         { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1396         { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1397         { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1398         { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1399         { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1400         { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1401         { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1402         { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1403         { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1404         { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1405         { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1406         { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1407         { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1408         { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1409         { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1410         { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1411         { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1412         { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1413         { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1414         { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1415         { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1416         {}
1417 };
1418
1419 static const int cdclk_squash_len = 16;
1420
1421 static int cdclk_squash_divider(u16 waveform)
1422 {
1423         return hweight16(waveform ?: 0xffff);
1424 }
1425
1426 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1427 {
1428         /* 2 * cd2x divider */
1429         return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1430                                  cdclk * cdclk_squash_len);
1431 }
1432
1433 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1434 {
1435         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1436         int i;
1437
1438         for (i = 0; table[i].refclk; i++)
1439                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1440                     table[i].cdclk >= min_cdclk)
1441                         return table[i].cdclk;
1442
1443         drm_WARN(&dev_priv->drm, 1,
1444                  "Cannot satisfy minimum cdclk %d with refclk %u\n",
1445                  min_cdclk, dev_priv->display.cdclk.hw.ref);
1446         return 0;
1447 }
1448
1449 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1450 {
1451         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1452         int i;
1453
1454         if (cdclk == dev_priv->display.cdclk.hw.bypass)
1455                 return 0;
1456
1457         for (i = 0; table[i].refclk; i++)
1458                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1459                     table[i].cdclk == cdclk)
1460                         return dev_priv->display.cdclk.hw.ref * table[i].ratio;
1461
1462         drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1463                  cdclk, dev_priv->display.cdclk.hw.ref);
1464         return 0;
1465 }
1466
1467 static u8 bxt_calc_voltage_level(int cdclk)
1468 {
1469         return DIV_ROUND_UP(cdclk, 25000);
1470 }
1471
1472 static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1473                              const int voltage_level_max_cdclk[])
1474 {
1475         int voltage_level;
1476
1477         for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1478                 if (cdclk <= voltage_level_max_cdclk[voltage_level])
1479                         return voltage_level;
1480         }
1481
1482         MISSING_CASE(cdclk);
1483         return num_voltage_levels - 1;
1484 }
1485
1486 static u8 icl_calc_voltage_level(int cdclk)
1487 {
1488         static const int icl_voltage_level_max_cdclk[] = {
1489                 [0] = 312000,
1490                 [1] = 556800,
1491                 [2] = 652800,
1492         };
1493
1494         return calc_voltage_level(cdclk,
1495                                   ARRAY_SIZE(icl_voltage_level_max_cdclk),
1496                                   icl_voltage_level_max_cdclk);
1497 }
1498
1499 static u8 ehl_calc_voltage_level(int cdclk)
1500 {
1501         static const int ehl_voltage_level_max_cdclk[] = {
1502                 [0] = 180000,
1503                 [1] = 312000,
1504                 [2] = 326400,
1505                 /*
1506                  * Bspec lists the limit as 556.8 MHz, but some JSL
1507                  * development boards (at least) boot with 652.8 MHz
1508                  */
1509                 [3] = 652800,
1510         };
1511
1512         return calc_voltage_level(cdclk,
1513                                   ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1514                                   ehl_voltage_level_max_cdclk);
1515 }
1516
1517 static u8 tgl_calc_voltage_level(int cdclk)
1518 {
1519         static const int tgl_voltage_level_max_cdclk[] = {
1520                 [0] = 312000,
1521                 [1] = 326400,
1522                 [2] = 556800,
1523                 [3] = 652800,
1524         };
1525
1526         return calc_voltage_level(cdclk,
1527                                   ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1528                                   tgl_voltage_level_max_cdclk);
1529 }
1530
1531 static u8 rplu_calc_voltage_level(int cdclk)
1532 {
1533         static const int rplu_voltage_level_max_cdclk[] = {
1534                 [0] = 312000,
1535                 [1] = 480000,
1536                 [2] = 556800,
1537                 [3] = 652800,
1538         };
1539
1540         return calc_voltage_level(cdclk,
1541                                   ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1542                                   rplu_voltage_level_max_cdclk);
1543 }
1544
1545 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1546                                struct intel_cdclk_config *cdclk_config)
1547 {
1548         u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1549
1550         switch (dssm) {
1551         default:
1552                 MISSING_CASE(dssm);
1553                 fallthrough;
1554         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1555                 cdclk_config->ref = 24000;
1556                 break;
1557         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1558                 cdclk_config->ref = 19200;
1559                 break;
1560         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1561                 cdclk_config->ref = 38400;
1562                 break;
1563         }
1564 }
1565
1566 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1567                                struct intel_cdclk_config *cdclk_config)
1568 {
1569         u32 val, ratio;
1570
1571         if (IS_DG2(dev_priv))
1572                 cdclk_config->ref = 38400;
1573         else if (DISPLAY_VER(dev_priv) >= 11)
1574                 icl_readout_refclk(dev_priv, cdclk_config);
1575         else
1576                 cdclk_config->ref = 19200;
1577
1578         val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1579         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1580             (val & BXT_DE_PLL_LOCK) == 0) {
1581                 /*
1582                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1583                  * setting it to zero is a way to signal that.
1584                  */
1585                 cdclk_config->vco = 0;
1586                 return;
1587         }
1588
1589         /*
1590          * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1591          * gen9lp had it in a separate PLL control register.
1592          */
1593         if (DISPLAY_VER(dev_priv) >= 11)
1594                 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1595         else
1596                 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1597
1598         cdclk_config->vco = ratio * cdclk_config->ref;
1599 }
1600
1601 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1602                           struct intel_cdclk_config *cdclk_config)
1603 {
1604         u32 squash_ctl = 0;
1605         u32 divider;
1606         int div;
1607
1608         bxt_de_pll_readout(dev_priv, cdclk_config);
1609
1610         if (DISPLAY_VER(dev_priv) >= 12)
1611                 cdclk_config->bypass = cdclk_config->ref / 2;
1612         else if (DISPLAY_VER(dev_priv) >= 11)
1613                 cdclk_config->bypass = 50000;
1614         else
1615                 cdclk_config->bypass = cdclk_config->ref;
1616
1617         if (cdclk_config->vco == 0) {
1618                 cdclk_config->cdclk = cdclk_config->bypass;
1619                 goto out;
1620         }
1621
1622         divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1623
1624         switch (divider) {
1625         case BXT_CDCLK_CD2X_DIV_SEL_1:
1626                 div = 2;
1627                 break;
1628         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1629                 div = 3;
1630                 break;
1631         case BXT_CDCLK_CD2X_DIV_SEL_2:
1632                 div = 4;
1633                 break;
1634         case BXT_CDCLK_CD2X_DIV_SEL_4:
1635                 div = 8;
1636                 break;
1637         default:
1638                 MISSING_CASE(divider);
1639                 return;
1640         }
1641
1642         if (HAS_CDCLK_SQUASH(dev_priv))
1643                 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
1644
1645         if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1646                 u16 waveform;
1647                 int size;
1648
1649                 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1650                 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1651
1652                 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1653                                                         cdclk_config->vco, size * div);
1654         } else {
1655                 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1656         }
1657
1658  out:
1659         /*
1660          * Can't read this out :( Let's assume it's
1661          * at least what the CDCLK frequency requires.
1662          */
1663         cdclk_config->voltage_level =
1664                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
1665 }
1666
1667 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1668 {
1669         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1670
1671         /* Timeout 200us */
1672         if (intel_de_wait_for_clear(dev_priv,
1673                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1674                 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1675
1676         dev_priv->display.cdclk.hw.vco = 0;
1677 }
1678
1679 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1680 {
1681         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1682
1683         intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
1684                      BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1685
1686         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1687
1688         /* Timeout 200us */
1689         if (intel_de_wait_for_set(dev_priv,
1690                                   BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1691                 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1692
1693         dev_priv->display.cdclk.hw.vco = vco;
1694 }
1695
1696 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1697 {
1698         intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
1699                      BXT_DE_PLL_PLL_ENABLE, 0);
1700
1701         /* Timeout 200us */
1702         if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1703                 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
1704
1705         dev_priv->display.cdclk.hw.vco = 0;
1706 }
1707
1708 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1709 {
1710         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1711         u32 val;
1712
1713         val = ICL_CDCLK_PLL_RATIO(ratio);
1714         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1715
1716         val |= BXT_DE_PLL_PLL_ENABLE;
1717         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1718
1719         /* Timeout 200us */
1720         if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1721                 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
1722
1723         dev_priv->display.cdclk.hw.vco = vco;
1724 }
1725
1726 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
1727 {
1728         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1729         u32 val;
1730
1731         /* Write PLL ratio without disabling */
1732         val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1733         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1734
1735         /* Submit freq change request */
1736         val |= BXT_DE_PLL_FREQ_REQ;
1737         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1738
1739         /* Timeout 200us */
1740         if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
1741                                   BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1742                 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
1743
1744         val &= ~BXT_DE_PLL_FREQ_REQ;
1745         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1746
1747         dev_priv->display.cdclk.hw.vco = vco;
1748 }
1749
1750 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1751 {
1752         if (DISPLAY_VER(dev_priv) >= 12) {
1753                 if (pipe == INVALID_PIPE)
1754                         return TGL_CDCLK_CD2X_PIPE_NONE;
1755                 else
1756                         return TGL_CDCLK_CD2X_PIPE(pipe);
1757         } else if (DISPLAY_VER(dev_priv) >= 11) {
1758                 if (pipe == INVALID_PIPE)
1759                         return ICL_CDCLK_CD2X_PIPE_NONE;
1760                 else
1761                         return ICL_CDCLK_CD2X_PIPE(pipe);
1762         } else {
1763                 if (pipe == INVALID_PIPE)
1764                         return BXT_CDCLK_CD2X_PIPE_NONE;
1765                 else
1766                         return BXT_CDCLK_CD2X_PIPE(pipe);
1767         }
1768 }
1769
1770 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
1771                                   int cdclk, int vco, u16 waveform)
1772 {
1773         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1774         switch (cdclk_divider(cdclk, vco, waveform)) {
1775         default:
1776                 drm_WARN_ON(&dev_priv->drm,
1777                             cdclk != dev_priv->display.cdclk.hw.bypass);
1778                 drm_WARN_ON(&dev_priv->drm, vco != 0);
1779                 fallthrough;
1780         case 2:
1781                 return BXT_CDCLK_CD2X_DIV_SEL_1;
1782         case 3:
1783                 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1784         case 4:
1785                 return BXT_CDCLK_CD2X_DIV_SEL_2;
1786         case 8:
1787                 return BXT_CDCLK_CD2X_DIV_SEL_4;
1788         }
1789 }
1790
1791 static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
1792                                  int cdclk)
1793 {
1794         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1795         int i;
1796
1797         if (cdclk == dev_priv->display.cdclk.hw.bypass)
1798                 return 0;
1799
1800         for (i = 0; table[i].refclk; i++)
1801                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1802                     table[i].cdclk == cdclk)
1803                         return table[i].waveform;
1804
1805         drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1806                  cdclk, dev_priv->display.cdclk.hw.ref);
1807
1808         return 0xffff;
1809 }
1810
1811 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1812 {
1813         if (i915->display.cdclk.hw.vco != 0 &&
1814             i915->display.cdclk.hw.vco != vco)
1815                 icl_cdclk_pll_disable(i915);
1816
1817         if (i915->display.cdclk.hw.vco != vco)
1818                 icl_cdclk_pll_enable(i915, vco);
1819 }
1820
1821 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1822 {
1823         if (i915->display.cdclk.hw.vco != 0 &&
1824             i915->display.cdclk.hw.vco != vco)
1825                 bxt_de_pll_disable(i915);
1826
1827         if (i915->display.cdclk.hw.vco != vco)
1828                 bxt_de_pll_enable(i915, vco);
1829 }
1830
1831 static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
1832                                      u16 waveform)
1833 {
1834         u32 squash_ctl = 0;
1835
1836         if (waveform)
1837                 squash_ctl = CDCLK_SQUASH_ENABLE |
1838                              CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1839
1840         intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
1841 }
1842
1843 static bool cdclk_pll_is_unknown(unsigned int vco)
1844 {
1845         /*
1846          * Ensure driver does not take the crawl path for the
1847          * case when the vco is set to ~0 in the
1848          * sanitize path.
1849          */
1850         return vco == ~0;
1851 }
1852
1853 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
1854                                                     const struct intel_cdclk_config *old_cdclk_config,
1855                                                     const struct intel_cdclk_config *new_cdclk_config,
1856                                                     struct intel_cdclk_config *mid_cdclk_config)
1857 {
1858         u16 old_waveform, new_waveform, mid_waveform;
1859         int old_div, new_div, mid_div;
1860
1861         /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1862         if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1863                 return false;
1864
1865         /* Return if both Squash and Crawl are not present */
1866         if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
1867                 return false;
1868
1869         old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
1870         new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
1871
1872         /* Return if Squash only or Crawl only is the desired action */
1873         if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
1874             old_cdclk_config->vco == new_cdclk_config->vco ||
1875             old_waveform == new_waveform)
1876                 return false;
1877
1878         old_div = cdclk_divider(old_cdclk_config->cdclk,
1879                                 old_cdclk_config->vco, old_waveform);
1880         new_div = cdclk_divider(new_cdclk_config->cdclk,
1881                                 new_cdclk_config->vco, new_waveform);
1882
1883         /*
1884          * Should not happen currently. We might need more midpoint
1885          * transitions if we need to also change the cd2x divider.
1886          */
1887         if (drm_WARN_ON(&i915->drm, old_div != new_div))
1888                 return false;
1889
1890         *mid_cdclk_config = *new_cdclk_config;
1891
1892         /*
1893          * Populate the mid_cdclk_config accordingly.
1894          * - If moving to a higher cdclk, the desired action is squashing.
1895          * The mid cdclk config should have the new (squash) waveform.
1896          * - If moving to a lower cdclk, the desired action is crawling.
1897          * The mid cdclk config should have the new vco.
1898          */
1899
1900         if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
1901                 mid_cdclk_config->vco = old_cdclk_config->vco;
1902                 mid_div = old_div;
1903                 mid_waveform = new_waveform;
1904         } else {
1905                 mid_cdclk_config->vco = new_cdclk_config->vco;
1906                 mid_div = new_div;
1907                 mid_waveform = old_waveform;
1908         }
1909
1910         mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
1911                                                     mid_cdclk_config->vco,
1912                                                     cdclk_squash_len * mid_div);
1913
1914         /* make sure the mid clock came out sane */
1915
1916         drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
1917                     min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
1918         drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
1919                     i915->display.cdclk.max_cdclk_freq);
1920         drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
1921                     mid_waveform);
1922
1923         return true;
1924 }
1925
1926 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
1927 {
1928         return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
1929                 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
1930                 IS_DG2(dev_priv)) &&
1931                 dev_priv->display.cdclk.hw.vco > 0;
1932 }
1933
1934 static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
1935                          const struct intel_cdclk_config *cdclk_config,
1936                          enum pipe pipe)
1937 {
1938         int cdclk = cdclk_config->cdclk;
1939         int vco = cdclk_config->vco;
1940         u16 waveform;
1941         u32 val;
1942
1943         waveform = cdclk_squash_waveform(i915, cdclk);
1944
1945         val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) |
1946                 bxt_cdclk_cd2x_pipe(i915, pipe);
1947
1948         /*
1949          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1950          * enable otherwise.
1951          */
1952         if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) &&
1953             cdclk >= 500000)
1954                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1955
1956         if (DISPLAY_VER(i915) >= 20)
1957                 val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
1958         else
1959                 val |= skl_cdclk_decimal(cdclk);
1960
1961         return val;
1962 }
1963
1964 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
1965                            const struct intel_cdclk_config *cdclk_config,
1966                            enum pipe pipe)
1967 {
1968         int cdclk = cdclk_config->cdclk;
1969         int vco = cdclk_config->vco;
1970         u16 waveform;
1971
1972         if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
1973             !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
1974                 if (dev_priv->display.cdclk.hw.vco != vco)
1975                         adlp_cdclk_pll_crawl(dev_priv, vco);
1976         } else if (DISPLAY_VER(dev_priv) >= 11) {
1977                 /* wa_15010685871: dg2, mtl */
1978                 if (pll_enable_wa_needed(dev_priv))
1979                         dg2_cdclk_squash_program(dev_priv, 0);
1980
1981                 icl_cdclk_pll_update(dev_priv, vco);
1982         } else
1983                 bxt_cdclk_pll_update(dev_priv, vco);
1984
1985         waveform = cdclk_squash_waveform(dev_priv, cdclk);
1986
1987         if (HAS_CDCLK_SQUASH(dev_priv))
1988                 dg2_cdclk_squash_program(dev_priv, waveform);
1989
1990         intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe));
1991
1992         if (pipe != INVALID_PIPE)
1993                 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
1994 }
1995
1996 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1997                           const struct intel_cdclk_config *cdclk_config,
1998                           enum pipe pipe)
1999 {
2000         struct intel_cdclk_config mid_cdclk_config;
2001         int cdclk = cdclk_config->cdclk;
2002         int ret = 0;
2003
2004         /*
2005          * Inform power controller of upcoming frequency change.
2006          * Display versions 14 and beyond do not follow the PUnit
2007          * mailbox communication, skip
2008          * this step.
2009          */
2010         if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
2011                 /* NOOP */;
2012         else if (DISPLAY_VER(dev_priv) >= 11)
2013                 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2014                                         SKL_CDCLK_PREPARE_FOR_CHANGE,
2015                                         SKL_CDCLK_READY_FOR_CHANGE,
2016                                         SKL_CDCLK_READY_FOR_CHANGE, 3);
2017         else
2018                 /*
2019                  * BSpec requires us to wait up to 150usec, but that leads to
2020                  * timeouts; the 2ms used here is based on experiment.
2021                  */
2022                 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2023                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
2024                                               0x80000000, 150, 2);
2025
2026         if (ret) {
2027                 drm_err(&dev_priv->drm,
2028                         "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2029                         ret, cdclk);
2030                 return;
2031         }
2032
2033         if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
2034                                                     cdclk_config, &mid_cdclk_config)) {
2035                 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
2036                 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
2037         } else {
2038                 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
2039         }
2040
2041         if (DISPLAY_VER(dev_priv) >= 14)
2042                 /*
2043                  * NOOP - No Pcode communication needed for
2044                  * Display versions 14 and beyond
2045                  */;
2046         else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv))
2047                 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2048                                       cdclk_config->voltage_level);
2049         if (DISPLAY_VER(dev_priv) < 11) {
2050                 /*
2051                  * The timeout isn't specified, the 2ms used here is based on
2052                  * experiment.
2053                  * FIXME: Waiting for the request completion could be delayed
2054                  * until the next PCODE request based on BSpec.
2055                  */
2056                 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2057                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
2058                                               cdclk_config->voltage_level,
2059                                               150, 2);
2060         }
2061         if (ret) {
2062                 drm_err(&dev_priv->drm,
2063                         "PCode CDCLK freq set failed, (err %d, freq %d)\n",
2064                         ret, cdclk);
2065                 return;
2066         }
2067
2068         intel_update_cdclk(dev_priv);
2069
2070         if (DISPLAY_VER(dev_priv) >= 11)
2071                 /*
2072                  * Can't read out the voltage level :(
2073                  * Let's just assume everything is as expected.
2074                  */
2075                 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
2076 }
2077
2078 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
2079 {
2080         u32 cdctl, expected;
2081         int cdclk, vco;
2082
2083         intel_update_cdclk(dev_priv);
2084         intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
2085
2086         if (dev_priv->display.cdclk.hw.vco == 0 ||
2087             dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
2088                 goto sanitize;
2089
2090         /* Make sure this is a legal cdclk value for the platform */
2091         cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
2092         if (cdclk != dev_priv->display.cdclk.hw.cdclk)
2093                 goto sanitize;
2094
2095         /* Make sure the VCO is correct for the cdclk */
2096         vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2097         if (vco != dev_priv->display.cdclk.hw.vco)
2098                 goto sanitize;
2099
2100         /*
2101          * Some BIOS versions leave an incorrect decimal frequency value and
2102          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2103          * so sanitize this register.
2104          */
2105         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
2106         expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);
2107
2108         /*
2109          * Let's ignore the pipe field, since BIOS could have configured the
2110          * dividers both synching to an active pipe, or asynchronously
2111          * (PIPE_NONE).
2112          */
2113         cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2114         expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2115
2116         if (cdctl == expected)
2117                 /* All well; nothing to sanitize */
2118                 return;
2119
2120 sanitize:
2121         drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
2122
2123         /* force cdclk programming */
2124         dev_priv->display.cdclk.hw.cdclk = 0;
2125
2126         /* force full PLL disable + enable */
2127         dev_priv->display.cdclk.hw.vco = ~0;
2128 }
2129
2130 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
2131 {
2132         struct intel_cdclk_config cdclk_config;
2133
2134         bxt_sanitize_cdclk(dev_priv);
2135
2136         if (dev_priv->display.cdclk.hw.cdclk != 0 &&
2137             dev_priv->display.cdclk.hw.vco != 0)
2138                 return;
2139
2140         cdclk_config = dev_priv->display.cdclk.hw;
2141
2142         /*
2143          * FIXME:
2144          * - The initial CDCLK needs to be read from VBT.
2145          *   Need to make this change after VBT has changes for BXT.
2146          */
2147         cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
2148         cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
2149         cdclk_config.voltage_level =
2150                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2151
2152         bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2153 }
2154
2155 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
2156 {
2157         struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
2158
2159         cdclk_config.cdclk = cdclk_config.bypass;
2160         cdclk_config.vco = 0;
2161         cdclk_config.voltage_level =
2162                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2163
2164         bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2165 }
2166
2167 /**
2168  * intel_cdclk_init_hw - Initialize CDCLK hardware
2169  * @i915: i915 device
2170  *
2171  * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2172  * sanitizing the state of the hardware if needed. This is generally done only
2173  * during the display core initialization sequence, after which the DMC will
2174  * take care of turning CDCLK off/on as needed.
2175  */
2176 void intel_cdclk_init_hw(struct drm_i915_private *i915)
2177 {
2178         if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2179                 bxt_cdclk_init_hw(i915);
2180         else if (DISPLAY_VER(i915) == 9)
2181                 skl_cdclk_init_hw(i915);
2182 }
2183
2184 /**
2185  * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2186  * @i915: i915 device
2187  *
2188  * Uninitialize CDCLK. This is done only during the display core
2189  * uninitialization sequence.
2190  */
2191 void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
2192 {
2193         if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2194                 bxt_cdclk_uninit_hw(i915);
2195         else if (DISPLAY_VER(i915) == 9)
2196                 skl_cdclk_uninit_hw(i915);
2197 }
2198
2199 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
2200                                              const struct intel_cdclk_config *a,
2201                                              const struct intel_cdclk_config *b)
2202 {
2203         u16 old_waveform;
2204         u16 new_waveform;
2205
2206         drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco));
2207
2208         if (a->vco == 0 || b->vco == 0)
2209                 return false;
2210
2211         if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
2212                 return false;
2213
2214         old_waveform = cdclk_squash_waveform(i915, a->cdclk);
2215         new_waveform = cdclk_squash_waveform(i915, b->cdclk);
2216
2217         return a->vco != b->vco &&
2218                old_waveform != new_waveform;
2219 }
2220
2221 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
2222                                   const struct intel_cdclk_config *a,
2223                                   const struct intel_cdclk_config *b)
2224 {
2225         int a_div, b_div;
2226
2227         if (!HAS_CDCLK_CRAWL(dev_priv))
2228                 return false;
2229
2230         /*
2231          * The vco and cd2x divider will change independently
2232          * from each, so we disallow cd2x change when crawling.
2233          */
2234         a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2235         b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2236
2237         return a->vco != 0 && b->vco != 0 &&
2238                 a->vco != b->vco &&
2239                 a_div == b_div &&
2240                 a->ref == b->ref;
2241 }
2242
2243 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
2244                                    const struct intel_cdclk_config *a,
2245                                    const struct intel_cdclk_config *b)
2246 {
2247         /*
2248          * FIXME should store a bit more state in intel_cdclk_config
2249          * to differentiate squasher vs. cd2x divider properly. For
2250          * the moment all platforms with squasher use a fixed cd2x
2251          * divider.
2252          */
2253         if (!HAS_CDCLK_SQUASH(dev_priv))
2254                 return false;
2255
2256         return a->cdclk != b->cdclk &&
2257                 a->vco != 0 &&
2258                 a->vco == b->vco &&
2259                 a->ref == b->ref;
2260 }
2261
2262 /**
2263  * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2264  *                             configurations requires a modeset on all pipes
2265  * @a: first CDCLK configuration
2266  * @b: second CDCLK configuration
2267  *
2268  * Returns:
2269  * True if changing between the two CDCLK configurations
2270  * requires all pipes to be off, false if not.
2271  */
2272 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
2273                                const struct intel_cdclk_config *b)
2274 {
2275         return a->cdclk != b->cdclk ||
2276                 a->vco != b->vco ||
2277                 a->ref != b->ref;
2278 }
2279
2280 /**
2281  * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2282  *                               configurations requires only a cd2x divider update
2283  * @dev_priv: i915 device
2284  * @a: first CDCLK configuration
2285  * @b: second CDCLK configuration
2286  *
2287  * Returns:
2288  * True if changing between the two CDCLK configurations
2289  * can be done with just a cd2x divider update, false if not.
2290  */
2291 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
2292                                         const struct intel_cdclk_config *a,
2293                                         const struct intel_cdclk_config *b)
2294 {
2295         /* Older hw doesn't have the capability */
2296         if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
2297                 return false;
2298
2299         /*
2300          * FIXME should store a bit more state in intel_cdclk_config
2301          * to differentiate squasher vs. cd2x divider properly. For
2302          * the moment all platforms with squasher use a fixed cd2x
2303          * divider.
2304          */
2305         if (HAS_CDCLK_SQUASH(dev_priv))
2306                 return false;
2307
2308         return a->cdclk != b->cdclk &&
2309                 a->vco != 0 &&
2310                 a->vco == b->vco &&
2311                 a->ref == b->ref;
2312 }
2313
2314 /**
2315  * intel_cdclk_changed - Determine if two CDCLK configurations are different
2316  * @a: first CDCLK configuration
2317  * @b: second CDCLK configuration
2318  *
2319  * Returns:
2320  * True if the CDCLK configurations don't match, false if they do.
2321  */
2322 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2323                                 const struct intel_cdclk_config *b)
2324 {
2325         return intel_cdclk_needs_modeset(a, b) ||
2326                 a->voltage_level != b->voltage_level;
2327 }
2328
2329 void intel_cdclk_dump_config(struct drm_i915_private *i915,
2330                              const struct intel_cdclk_config *cdclk_config,
2331                              const char *context)
2332 {
2333         drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2334                     context, cdclk_config->cdclk, cdclk_config->vco,
2335                     cdclk_config->ref, cdclk_config->bypass,
2336                     cdclk_config->voltage_level);
2337 }
2338
2339 static void intel_pcode_notify(struct drm_i915_private *i915,
2340                                u8 voltage_level,
2341                                u8 active_pipe_count,
2342                                u16 cdclk,
2343                                bool cdclk_update_valid,
2344                                bool pipe_count_update_valid)
2345 {
2346         int ret;
2347         u32 update_mask = 0;
2348
2349         if (!IS_DG2(i915))
2350                 return;
2351
2352         update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2353
2354         if (cdclk_update_valid)
2355                 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2356
2357         if (pipe_count_update_valid)
2358                 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2359
2360         ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2361                                 SKL_CDCLK_PREPARE_FOR_CHANGE |
2362                                 update_mask,
2363                                 SKL_CDCLK_READY_FOR_CHANGE,
2364                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
2365         if (ret)
2366                 drm_err(&i915->drm,
2367                         "Failed to inform PCU about display config (err %d)\n",
2368                         ret);
2369 }
2370
2371 /**
2372  * intel_set_cdclk - Push the CDCLK configuration to the hardware
2373  * @dev_priv: i915 device
2374  * @cdclk_config: new CDCLK configuration
2375  * @pipe: pipe with which to synchronize the update
2376  *
2377  * Program the hardware based on the passed in CDCLK state,
2378  * if necessary.
2379  */
2380 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2381                             const struct intel_cdclk_config *cdclk_config,
2382                             enum pipe pipe)
2383 {
2384         struct intel_encoder *encoder;
2385
2386         if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
2387                 return;
2388
2389         if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
2390                 return;
2391
2392         intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
2393
2394         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2395                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2396
2397                 intel_psr_pause(intel_dp);
2398         }
2399
2400         intel_audio_cdclk_change_pre(dev_priv);
2401
2402         /*
2403          * Lock aux/gmbus while we change cdclk in case those
2404          * functions use cdclk. Not all platforms/ports do,
2405          * but we'll lock them all for simplicity.
2406          */
2407         mutex_lock(&dev_priv->display.gmbus.mutex);
2408         for_each_intel_dp(&dev_priv->drm, encoder) {
2409                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2410
2411                 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2412                                      &dev_priv->display.gmbus.mutex);
2413         }
2414
2415         intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
2416
2417         for_each_intel_dp(&dev_priv->drm, encoder) {
2418                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2419
2420                 mutex_unlock(&intel_dp->aux.hw_mutex);
2421         }
2422         mutex_unlock(&dev_priv->display.gmbus.mutex);
2423
2424         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2425                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2426
2427                 intel_psr_resume(intel_dp);
2428         }
2429
2430         intel_audio_cdclk_change_post(dev_priv);
2431
2432         if (drm_WARN(&dev_priv->drm,
2433                      intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
2434                      "cdclk state doesn't match!\n")) {
2435                 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
2436                 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
2437         }
2438 }
2439
2440 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2441 {
2442         struct drm_i915_private *i915 = to_i915(state->base.dev);
2443         const struct intel_cdclk_state *old_cdclk_state =
2444                 intel_atomic_get_old_cdclk_state(state);
2445         const struct intel_cdclk_state *new_cdclk_state =
2446                 intel_atomic_get_new_cdclk_state(state);
2447         unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2448         bool change_cdclk, update_pipe_count;
2449
2450         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2451                                  &new_cdclk_state->actual) &&
2452                                  new_cdclk_state->active_pipes ==
2453                                  old_cdclk_state->active_pipes)
2454                 return;
2455
2456         /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2457         voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2458
2459         change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2460         update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2461                             hweight8(old_cdclk_state->active_pipes);
2462
2463         /*
2464          * According to "Sequence Before Frequency Change",
2465          * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2466          * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2467          * which basically means we choose the maximum of old and new CDCLK, if we know both
2468          */
2469         if (change_cdclk)
2470                 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2471
2472         /*
2473          * According to "Sequence For Pipe Count Change",
2474          * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2475          * (power well is enabled)
2476          * no action if it is decreasing, before the change
2477          */
2478         if (update_pipe_count)
2479                 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2480
2481         intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2482                            change_cdclk, update_pipe_count);
2483 }
2484
2485 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2486 {
2487         struct drm_i915_private *i915 = to_i915(state->base.dev);
2488         const struct intel_cdclk_state *new_cdclk_state =
2489                 intel_atomic_get_new_cdclk_state(state);
2490         const struct intel_cdclk_state *old_cdclk_state =
2491                 intel_atomic_get_old_cdclk_state(state);
2492         unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2493         bool update_cdclk, update_pipe_count;
2494
2495         /* According to "Sequence After Frequency Change", set voltage to used level */
2496         voltage_level = new_cdclk_state->actual.voltage_level;
2497
2498         update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2499         update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2500                             hweight8(old_cdclk_state->active_pipes);
2501
2502         /*
2503          * According to "Sequence After Frequency Change",
2504          * set bits 25:16 to current CDCLK
2505          */
2506         if (update_cdclk)
2507                 cdclk = new_cdclk_state->actual.cdclk;
2508
2509         /*
2510          * According to "Sequence For Pipe Count Change",
2511          * if pipe count is decreasing, set bits 25:16 to current pipe count,
2512          * after the change(power well is disabled)
2513          * no action if it is increasing, after the change
2514          */
2515         if (update_pipe_count)
2516                 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2517
2518         intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2519                            update_cdclk, update_pipe_count);
2520 }
2521
2522 /**
2523  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2524  * @state: intel atomic state
2525  *
2526  * Program the hardware before updating the HW plane state based on the
2527  * new CDCLK state, if necessary.
2528  */
2529 void
2530 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2531 {
2532         struct drm_i915_private *i915 = to_i915(state->base.dev);
2533         const struct intel_cdclk_state *old_cdclk_state =
2534                 intel_atomic_get_old_cdclk_state(state);
2535         const struct intel_cdclk_state *new_cdclk_state =
2536                 intel_atomic_get_new_cdclk_state(state);
2537         struct intel_cdclk_config cdclk_config;
2538         enum pipe pipe;
2539
2540         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2541                                  &new_cdclk_state->actual))
2542                 return;
2543
2544         if (IS_DG2(i915))
2545                 intel_cdclk_pcode_pre_notify(state);
2546
2547         if (new_cdclk_state->disable_pipes) {
2548                 cdclk_config = new_cdclk_state->actual;
2549                 pipe = INVALID_PIPE;
2550         } else {
2551                 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2552                         cdclk_config = new_cdclk_state->actual;
2553                         pipe = new_cdclk_state->pipe;
2554                 } else {
2555                         cdclk_config = old_cdclk_state->actual;
2556                         pipe = INVALID_PIPE;
2557                 }
2558
2559                 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2560                                                  old_cdclk_state->actual.voltage_level);
2561         }
2562
2563         drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2564
2565         intel_set_cdclk(i915, &cdclk_config, pipe);
2566 }
2567
2568 /**
2569  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2570  * @state: intel atomic state
2571  *
2572  * Program the hardware after updating the HW plane state based on the
2573  * new CDCLK state, if necessary.
2574  */
2575 void
2576 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2577 {
2578         struct drm_i915_private *i915 = to_i915(state->base.dev);
2579         const struct intel_cdclk_state *old_cdclk_state =
2580                 intel_atomic_get_old_cdclk_state(state);
2581         const struct intel_cdclk_state *new_cdclk_state =
2582                 intel_atomic_get_new_cdclk_state(state);
2583         enum pipe pipe;
2584
2585         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2586                                  &new_cdclk_state->actual))
2587                 return;
2588
2589         if (IS_DG2(i915))
2590                 intel_cdclk_pcode_post_notify(state);
2591
2592         if (!new_cdclk_state->disable_pipes &&
2593             new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2594                 pipe = new_cdclk_state->pipe;
2595         else
2596                 pipe = INVALID_PIPE;
2597
2598         drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2599
2600         intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2601 }
2602
2603 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2604 {
2605         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2606         int pixel_rate = crtc_state->pixel_rate;
2607
2608         if (DISPLAY_VER(dev_priv) >= 10)
2609                 return DIV_ROUND_UP(pixel_rate, 2);
2610         else if (DISPLAY_VER(dev_priv) == 9 ||
2611                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2612                 return pixel_rate;
2613         else if (IS_CHERRYVIEW(dev_priv))
2614                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2615         else if (crtc_state->double_wide)
2616                 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2617         else
2618                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2619 }
2620
2621 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2622 {
2623         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2625         struct intel_plane *plane;
2626         int min_cdclk = 0;
2627
2628         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
2629                 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2630
2631         return min_cdclk;
2632 }
2633
2634 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
2635 {
2636         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2637         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2638         int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
2639         int min_cdclk = 0;
2640
2641         /*
2642          * When we decide to use only one VDSC engine, since
2643          * each VDSC operates with 1 ppc throughput, pixel clock
2644          * cannot be higher than the VDSC clock (cdclk)
2645          * If there 2 VDSC engines, then pixel clock can't be higher than
2646          * VDSC clock(cdclk) * 2 and so on.
2647          */
2648         min_cdclk = max_t(int, min_cdclk,
2649                           DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
2650
2651         if (crtc_state->bigjoiner_pipes) {
2652                 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
2653
2654                 /*
2655                  * According to Bigjoiner bw check:
2656                  * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
2657                  *
2658                  * We have already computed compressed_bpp, so now compute the min CDCLK that
2659                  * is required to support this compressed_bpp.
2660                  *
2661                  * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
2662                  *
2663                  * Since PPC = 2 with bigjoiner
2664                  * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
2665                  */
2666                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
2667                 int min_cdclk_bj =
2668                         (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
2669                          pixel_clock) / (2 * bigjoiner_interface_bits);
2670
2671                 min_cdclk = max(min_cdclk, min_cdclk_bj);
2672         }
2673
2674         return min_cdclk;
2675 }
2676
2677 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2678 {
2679         struct drm_i915_private *dev_priv =
2680                 to_i915(crtc_state->uapi.crtc->dev);
2681         int min_cdclk;
2682
2683         if (!crtc_state->hw.enable)
2684                 return 0;
2685
2686         min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2687
2688         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2689         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2690                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2691
2692         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2693          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2694          * there may be audio corruption or screen corruption." This cdclk
2695          * restriction for GLK is 316.8 MHz.
2696          */
2697         if (intel_crtc_has_dp_encoder(crtc_state) &&
2698             crtc_state->has_audio &&
2699             crtc_state->port_clock >= 540000 &&
2700             crtc_state->lane_count == 4) {
2701                 if (DISPLAY_VER(dev_priv) == 10) {
2702                         /* Display WA #1145: glk */
2703                         min_cdclk = max(316800, min_cdclk);
2704                 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
2705                         /* Display WA #1144: skl,bxt */
2706                         min_cdclk = max(432000, min_cdclk);
2707                 }
2708         }
2709
2710         /*
2711          * According to BSpec, "The CD clock frequency must be at least twice
2712          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2713          */
2714         if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
2715                 min_cdclk = max(2 * 96000, min_cdclk);
2716
2717         /*
2718          * "For DP audio configuration, cdclk frequency shall be set to
2719          *  meet the following requirements:
2720          *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
2721          *  270                    | 320 or higher
2722          *  162                    | 200 or higher"
2723          */
2724         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2725             intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2726                 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2727
2728         /*
2729          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2730          * than 320000KHz.
2731          */
2732         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2733             IS_VALLEYVIEW(dev_priv))
2734                 min_cdclk = max(320000, min_cdclk);
2735
2736         /*
2737          * On Geminilake once the CDCLK gets as low as 79200
2738          * picture gets unstable, despite that values are
2739          * correct for DSI PLL and DE PLL.
2740          */
2741         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2742             IS_GEMINILAKE(dev_priv))
2743                 min_cdclk = max(158400, min_cdclk);
2744
2745         /* Account for additional needs from the planes */
2746         min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2747
2748         if (crtc_state->dsc.compression_enable)
2749                 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2750
2751         /*
2752          * HACK. Currently for TGL/DG2 platforms we calculate
2753          * min_cdclk initially based on pixel_rate divided
2754          * by 2, accounting for also plane requirements,
2755          * however in some cases the lowest possible CDCLK
2756          * doesn't work and causing the underruns.
2757          * Explicitly stating here that this seems to be currently
2758          * rather a Hack, than final solution.
2759          */
2760         if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
2761                 /*
2762                  * Clamp to max_cdclk_freq in case pixel rate is higher,
2763                  * in order not to break an 8K, but still leave W/A at place.
2764                  */
2765                 min_cdclk = max_t(int, min_cdclk,
2766                                   min_t(int, crtc_state->pixel_rate,
2767                                         dev_priv->display.cdclk.max_cdclk_freq));
2768         }
2769
2770         return min_cdclk;
2771 }
2772
2773 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2774 {
2775         struct intel_atomic_state *state = cdclk_state->base.state;
2776         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2777         const struct intel_bw_state *bw_state;
2778         struct intel_crtc *crtc;
2779         struct intel_crtc_state *crtc_state;
2780         int min_cdclk, i;
2781         enum pipe pipe;
2782
2783         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2784                 int ret;
2785
2786                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2787                 if (min_cdclk < 0)
2788                         return min_cdclk;
2789
2790                 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2791                         continue;
2792
2793                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2794
2795                 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2796                 if (ret)
2797                         return ret;
2798         }
2799
2800         bw_state = intel_atomic_get_new_bw_state(state);
2801         if (bw_state) {
2802                 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
2803
2804                 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2805                         int ret;
2806
2807                         cdclk_state->bw_min_cdclk = min_cdclk;
2808
2809                         ret = intel_atomic_lock_global_state(&cdclk_state->base);
2810                         if (ret)
2811                                 return ret;
2812                 }
2813         }
2814
2815         min_cdclk = max(cdclk_state->force_min_cdclk,
2816                         cdclk_state->bw_min_cdclk);
2817         for_each_pipe(dev_priv, pipe)
2818                 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2819
2820         /*
2821          * Avoid glk_force_audio_cdclk() causing excessive screen
2822          * blinking when multiple pipes are active by making sure
2823          * CDCLK frequency is always high enough for audio. With a
2824          * single active pipe we can always change CDCLK frequency
2825          * by changing the cd2x divider (see glk_cdclk_table[]) and
2826          * thus a full modeset won't be needed then.
2827          */
2828         if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
2829             !is_power_of_2(cdclk_state->active_pipes))
2830                 min_cdclk = max(2 * 96000, min_cdclk);
2831
2832         if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
2833                 drm_dbg_kms(&dev_priv->drm,
2834                             "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2835                             min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
2836                 return -EINVAL;
2837         }
2838
2839         return min_cdclk;
2840 }
2841
2842 /*
2843  * Account for port clock min voltage level requirements.
2844  * This only really does something on DISPLA_VER >= 11 but can be
2845  * called on earlier platforms as well.
2846  *
2847  * Note that this functions assumes that 0 is
2848  * the lowest voltage value, and higher values
2849  * correspond to increasingly higher voltages.
2850  *
2851  * Should that relationship no longer hold on
2852  * future platforms this code will need to be
2853  * adjusted.
2854  */
2855 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2856 {
2857         struct intel_atomic_state *state = cdclk_state->base.state;
2858         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2859         struct intel_crtc *crtc;
2860         struct intel_crtc_state *crtc_state;
2861         u8 min_voltage_level;
2862         int i;
2863         enum pipe pipe;
2864
2865         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2866                 int ret;
2867
2868                 if (crtc_state->hw.enable)
2869                         min_voltage_level = crtc_state->min_voltage_level;
2870                 else
2871                         min_voltage_level = 0;
2872
2873                 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2874                         continue;
2875
2876                 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2877
2878                 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2879                 if (ret)
2880                         return ret;
2881         }
2882
2883         min_voltage_level = 0;
2884         for_each_pipe(dev_priv, pipe)
2885                 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2886                                         min_voltage_level);
2887
2888         return min_voltage_level;
2889 }
2890
2891 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2892 {
2893         struct intel_atomic_state *state = cdclk_state->base.state;
2894         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2895         int min_cdclk, cdclk;
2896
2897         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2898         if (min_cdclk < 0)
2899                 return min_cdclk;
2900
2901         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2902
2903         cdclk_state->logical.cdclk = cdclk;
2904         cdclk_state->logical.voltage_level =
2905                 vlv_calc_voltage_level(dev_priv, cdclk);
2906
2907         if (!cdclk_state->active_pipes) {
2908                 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2909
2910                 cdclk_state->actual.cdclk = cdclk;
2911                 cdclk_state->actual.voltage_level =
2912                         vlv_calc_voltage_level(dev_priv, cdclk);
2913         } else {
2914                 cdclk_state->actual = cdclk_state->logical;
2915         }
2916
2917         return 0;
2918 }
2919
2920 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2921 {
2922         int min_cdclk, cdclk;
2923
2924         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2925         if (min_cdclk < 0)
2926                 return min_cdclk;
2927
2928         cdclk = bdw_calc_cdclk(min_cdclk);
2929
2930         cdclk_state->logical.cdclk = cdclk;
2931         cdclk_state->logical.voltage_level =
2932                 bdw_calc_voltage_level(cdclk);
2933
2934         if (!cdclk_state->active_pipes) {
2935                 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2936
2937                 cdclk_state->actual.cdclk = cdclk;
2938                 cdclk_state->actual.voltage_level =
2939                         bdw_calc_voltage_level(cdclk);
2940         } else {
2941                 cdclk_state->actual = cdclk_state->logical;
2942         }
2943
2944         return 0;
2945 }
2946
2947 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2948 {
2949         struct intel_atomic_state *state = cdclk_state->base.state;
2950         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2951         struct intel_crtc *crtc;
2952         struct intel_crtc_state *crtc_state;
2953         int vco, i;
2954
2955         vco = cdclk_state->logical.vco;
2956         if (!vco)
2957                 vco = dev_priv->skl_preferred_vco_freq;
2958
2959         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2960                 if (!crtc_state->hw.enable)
2961                         continue;
2962
2963                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2964                         continue;
2965
2966                 /*
2967                  * DPLL0 VCO may need to be adjusted to get the correct
2968                  * clock for eDP. This will affect cdclk as well.
2969                  */
2970                 switch (crtc_state->port_clock / 2) {
2971                 case 108000:
2972                 case 216000:
2973                         vco = 8640000;
2974                         break;
2975                 default:
2976                         vco = 8100000;
2977                         break;
2978                 }
2979         }
2980
2981         return vco;
2982 }
2983
2984 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2985 {
2986         int min_cdclk, cdclk, vco;
2987
2988         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2989         if (min_cdclk < 0)
2990                 return min_cdclk;
2991
2992         vco = skl_dpll0_vco(cdclk_state);
2993
2994         cdclk = skl_calc_cdclk(min_cdclk, vco);
2995
2996         cdclk_state->logical.vco = vco;
2997         cdclk_state->logical.cdclk = cdclk;
2998         cdclk_state->logical.voltage_level =
2999                 skl_calc_voltage_level(cdclk);
3000
3001         if (!cdclk_state->active_pipes) {
3002                 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3003
3004                 cdclk_state->actual.vco = vco;
3005                 cdclk_state->actual.cdclk = cdclk;
3006                 cdclk_state->actual.voltage_level =
3007                         skl_calc_voltage_level(cdclk);
3008         } else {
3009                 cdclk_state->actual = cdclk_state->logical;
3010         }
3011
3012         return 0;
3013 }
3014
3015 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3016 {
3017         struct intel_atomic_state *state = cdclk_state->base.state;
3018         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3019         int min_cdclk, min_voltage_level, cdclk, vco;
3020
3021         min_cdclk = intel_compute_min_cdclk(cdclk_state);
3022         if (min_cdclk < 0)
3023                 return min_cdclk;
3024
3025         min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
3026         if (min_voltage_level < 0)
3027                 return min_voltage_level;
3028
3029         cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
3030         vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
3031
3032         cdclk_state->logical.vco = vco;
3033         cdclk_state->logical.cdclk = cdclk;
3034         cdclk_state->logical.voltage_level =
3035                 max_t(int, min_voltage_level,
3036                       intel_cdclk_calc_voltage_level(dev_priv, cdclk));
3037
3038         if (!cdclk_state->active_pipes) {
3039                 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
3040                 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
3041
3042                 cdclk_state->actual.vco = vco;
3043                 cdclk_state->actual.cdclk = cdclk;
3044                 cdclk_state->actual.voltage_level =
3045                         intel_cdclk_calc_voltage_level(dev_priv, cdclk);
3046         } else {
3047                 cdclk_state->actual = cdclk_state->logical;
3048         }
3049
3050         return 0;
3051 }
3052
3053 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3054 {
3055         int min_cdclk;
3056
3057         /*
3058          * We can't change the cdclk frequency, but we still want to
3059          * check that the required minimum frequency doesn't exceed
3060          * the actual cdclk frequency.
3061          */
3062         min_cdclk = intel_compute_min_cdclk(cdclk_state);
3063         if (min_cdclk < 0)
3064                 return min_cdclk;
3065
3066         return 0;
3067 }
3068
3069 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3070 {
3071         struct intel_cdclk_state *cdclk_state;
3072
3073         cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3074         if (!cdclk_state)
3075                 return NULL;
3076
3077         cdclk_state->pipe = INVALID_PIPE;
3078         cdclk_state->disable_pipes = false;
3079
3080         return &cdclk_state->base;
3081 }
3082
3083 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3084                                       struct intel_global_state *state)
3085 {
3086         kfree(state);
3087 }
3088
3089 static const struct intel_global_state_funcs intel_cdclk_funcs = {
3090         .atomic_duplicate_state = intel_cdclk_duplicate_state,
3091         .atomic_destroy_state = intel_cdclk_destroy_state,
3092 };
3093
3094 struct intel_cdclk_state *
3095 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3096 {
3097         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3098         struct intel_global_state *cdclk_state;
3099
3100         cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
3101         if (IS_ERR(cdclk_state))
3102                 return ERR_CAST(cdclk_state);
3103
3104         return to_intel_cdclk_state(cdclk_state);
3105 }
3106
3107 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
3108                              bool *need_cdclk_calc)
3109 {
3110         const struct intel_cdclk_state *old_cdclk_state;
3111         const struct intel_cdclk_state *new_cdclk_state;
3112         struct intel_plane_state __maybe_unused *plane_state;
3113         struct intel_plane *plane;
3114         int ret;
3115         int i;
3116
3117         /*
3118          * active_planes bitmask has been updated, and potentially affected
3119          * planes are part of the state. We can now compute the minimum cdclk
3120          * for each plane.
3121          */
3122         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3123                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
3124                 if (ret)
3125                         return ret;
3126         }
3127
3128         ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
3129         if (ret)
3130                 return ret;
3131
3132         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3133         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3134
3135         if (new_cdclk_state &&
3136             old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3137                 *need_cdclk_calc = true;
3138
3139         return 0;
3140 }
3141
3142 int intel_cdclk_init(struct drm_i915_private *dev_priv)
3143 {
3144         struct intel_cdclk_state *cdclk_state;
3145
3146         cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3147         if (!cdclk_state)
3148                 return -ENOMEM;
3149
3150         intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
3151                                      &cdclk_state->base, &intel_cdclk_funcs);
3152
3153         return 0;
3154 }
3155
3156 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
3157                                        const struct intel_cdclk_state *old_cdclk_state,
3158                                        const struct intel_cdclk_state *new_cdclk_state)
3159 {
3160         bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3161                                       hweight8(new_cdclk_state->active_pipes);
3162         bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3163                                                  &new_cdclk_state->actual);
3164         /*
3165          * We need to poke hw for gen >= 12, because we notify PCode if
3166          * pipe power well count changes.
3167          */
3168         return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed);
3169 }
3170
3171 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3172 {
3173         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3174         const struct intel_cdclk_state *old_cdclk_state;
3175         struct intel_cdclk_state *new_cdclk_state;
3176         enum pipe pipe = INVALID_PIPE;
3177         int ret;
3178
3179         new_cdclk_state = intel_atomic_get_cdclk_state(state);
3180         if (IS_ERR(new_cdclk_state))
3181                 return PTR_ERR(new_cdclk_state);
3182
3183         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3184
3185         new_cdclk_state->active_pipes =
3186                 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3187
3188         ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);
3189         if (ret)
3190                 return ret;
3191
3192         if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) {
3193                 /*
3194                  * Also serialize commits across all crtcs
3195                  * if the actual hw needs to be poked.
3196                  */
3197                 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3198                 if (ret)
3199                         return ret;
3200         } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3201                    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3202                    intel_cdclk_changed(&old_cdclk_state->logical,
3203                                        &new_cdclk_state->logical)) {
3204                 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3205                 if (ret)
3206                         return ret;
3207         } else {
3208                 return 0;
3209         }
3210
3211         if (is_power_of_2(new_cdclk_state->active_pipes) &&
3212             intel_cdclk_can_cd2x_update(dev_priv,
3213                                         &old_cdclk_state->actual,
3214                                         &new_cdclk_state->actual)) {
3215                 struct intel_crtc *crtc;
3216                 struct intel_crtc_state *crtc_state;
3217
3218                 pipe = ilog2(new_cdclk_state->active_pipes);
3219                 crtc = intel_crtc_for_pipe(dev_priv, pipe);
3220
3221                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3222                 if (IS_ERR(crtc_state))
3223                         return PTR_ERR(crtc_state);
3224
3225                 if (intel_crtc_needs_modeset(crtc_state))
3226                         pipe = INVALID_PIPE;
3227         }
3228
3229         if (intel_cdclk_can_crawl_and_squash(dev_priv,
3230                                              &old_cdclk_state->actual,
3231                                              &new_cdclk_state->actual)) {
3232                 drm_dbg_kms(&dev_priv->drm,
3233                             "Can change cdclk via crawling and squashing\n");
3234         } else if (intel_cdclk_can_squash(dev_priv,
3235                                         &old_cdclk_state->actual,
3236                                         &new_cdclk_state->actual)) {
3237                 drm_dbg_kms(&dev_priv->drm,
3238                             "Can change cdclk via squashing\n");
3239         } else if (intel_cdclk_can_crawl(dev_priv,
3240                                          &old_cdclk_state->actual,
3241                                          &new_cdclk_state->actual)) {
3242                 drm_dbg_kms(&dev_priv->drm,
3243                             "Can change cdclk via crawling\n");
3244         } else if (pipe != INVALID_PIPE) {
3245                 new_cdclk_state->pipe = pipe;
3246
3247                 drm_dbg_kms(&dev_priv->drm,
3248                             "Can change cdclk cd2x divider with pipe %c active\n",
3249                             pipe_name(pipe));
3250         } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
3251                                              &new_cdclk_state->actual)) {
3252                 /* All pipes must be switched off while we change the cdclk. */
3253                 ret = intel_modeset_all_pipes_late(state, "CDCLK change");
3254                 if (ret)
3255                         return ret;
3256
3257                 new_cdclk_state->disable_pipes = true;
3258
3259                 drm_dbg_kms(&dev_priv->drm,
3260                             "Modeset required for cdclk change\n");
3261         }
3262
3263         drm_dbg_kms(&dev_priv->drm,
3264                     "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3265                     new_cdclk_state->logical.cdclk,
3266                     new_cdclk_state->actual.cdclk);
3267         drm_dbg_kms(&dev_priv->drm,
3268                     "New voltage level calculated to be logical %u, actual %u\n",
3269                     new_cdclk_state->logical.voltage_level,
3270                     new_cdclk_state->actual.voltage_level);
3271
3272         return 0;
3273 }
3274
3275 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
3276 {
3277         int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
3278
3279         if (DISPLAY_VER(dev_priv) >= 10)
3280                 return 2 * max_cdclk_freq;
3281         else if (DISPLAY_VER(dev_priv) == 9 ||
3282                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3283                 return max_cdclk_freq;
3284         else if (IS_CHERRYVIEW(dev_priv))
3285                 return max_cdclk_freq*95/100;
3286         else if (DISPLAY_VER(dev_priv) < 4)
3287                 return 2*max_cdclk_freq*90/100;
3288         else
3289                 return max_cdclk_freq*90/100;
3290 }
3291
3292 /**
3293  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3294  * @dev_priv: i915 device
3295  *
3296  * Determine the maximum CDCLK frequency the platform supports, and also
3297  * derive the maximum dot clock frequency the maximum CDCLK frequency
3298  * allows.
3299  */
3300 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
3301 {
3302         if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3303                 if (dev_priv->display.cdclk.hw.ref == 24000)
3304                         dev_priv->display.cdclk.max_cdclk_freq = 552000;
3305                 else
3306                         dev_priv->display.cdclk.max_cdclk_freq = 556800;
3307         } else if (DISPLAY_VER(dev_priv) >= 11) {
3308                 if (dev_priv->display.cdclk.hw.ref == 24000)
3309                         dev_priv->display.cdclk.max_cdclk_freq = 648000;
3310                 else
3311                         dev_priv->display.cdclk.max_cdclk_freq = 652800;
3312         } else if (IS_GEMINILAKE(dev_priv)) {
3313                 dev_priv->display.cdclk.max_cdclk_freq = 316800;
3314         } else if (IS_BROXTON(dev_priv)) {
3315                 dev_priv->display.cdclk.max_cdclk_freq = 624000;
3316         } else if (DISPLAY_VER(dev_priv) == 9) {
3317                 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3318                 int max_cdclk, vco;
3319
3320                 vco = dev_priv->skl_preferred_vco_freq;
3321                 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
3322
3323                 /*
3324                  * Use the lower (vco 8640) cdclk values as a
3325                  * first guess. skl_calc_cdclk() will correct it
3326                  * if the preferred vco is 8100 instead.
3327                  */
3328                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3329                         max_cdclk = 617143;
3330                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3331                         max_cdclk = 540000;
3332                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3333                         max_cdclk = 432000;
3334                 else
3335                         max_cdclk = 308571;
3336
3337                 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3338         } else if (IS_BROADWELL(dev_priv))  {
3339                 /*
3340                  * FIXME with extra cooling we can allow
3341                  * 540 MHz for ULX and 675 Mhz for ULT.
3342                  * How can we know if extra cooling is
3343                  * available? PCI ID, VTB, something else?
3344                  */
3345                 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3346                         dev_priv->display.cdclk.max_cdclk_freq = 450000;
3347                 else if (IS_BROADWELL_ULX(dev_priv))
3348                         dev_priv->display.cdclk.max_cdclk_freq = 450000;
3349                 else if (IS_BROADWELL_ULT(dev_priv))
3350                         dev_priv->display.cdclk.max_cdclk_freq = 540000;
3351                 else
3352                         dev_priv->display.cdclk.max_cdclk_freq = 675000;
3353         } else if (IS_CHERRYVIEW(dev_priv)) {
3354                 dev_priv->display.cdclk.max_cdclk_freq = 320000;
3355         } else if (IS_VALLEYVIEW(dev_priv)) {
3356                 dev_priv->display.cdclk.max_cdclk_freq = 400000;
3357         } else {
3358                 /* otherwise assume cdclk is fixed */
3359                 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
3360         }
3361
3362         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
3363
3364         drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
3365                 dev_priv->display.cdclk.max_cdclk_freq);
3366
3367         drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
3368                 dev_priv->max_dotclk_freq);
3369 }
3370
3371 /**
3372  * intel_update_cdclk - Determine the current CDCLK frequency
3373  * @dev_priv: i915 device
3374  *
3375  * Determine the current CDCLK frequency.
3376  */
3377 void intel_update_cdclk(struct drm_i915_private *dev_priv)
3378 {
3379         intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
3380
3381         /*
3382          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3383          * Programmng [sic] note: bit[9:2] should be programmed to the number
3384          * of cdclk that generates 4MHz reference clock freq which is used to
3385          * generate GMBus clock. This will vary with the cdclk freq.
3386          */
3387         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3388                 intel_de_write(dev_priv, GMBUSFREQ_VLV,
3389                                DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
3390 }
3391
3392 static int dg1_rawclk(struct drm_i915_private *dev_priv)
3393 {
3394         /*
3395          * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
3396          * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3397          */
3398         intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
3399                        CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3400
3401         return 38400;
3402 }
3403
3404 static int cnp_rawclk(struct drm_i915_private *dev_priv)
3405 {
3406         u32 rawclk;
3407         int divider, fraction;
3408
3409         if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3410                 /* 24 MHz */
3411                 divider = 24000;
3412                 fraction = 0;
3413         } else {
3414                 /* 19.2 MHz */
3415                 divider = 19000;
3416                 fraction = 200;
3417         }
3418
3419         rawclk = CNP_RAWCLK_DIV(divider / 1000);
3420         if (fraction) {
3421                 int numerator = 1;
3422
3423                 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3424                                                            fraction) - 1);
3425                 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3426                         rawclk |= ICP_RAWCLK_NUM(numerator);
3427         }
3428
3429         intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
3430         return divider + fraction;
3431 }
3432
3433 static int pch_rawclk(struct drm_i915_private *dev_priv)
3434 {
3435         return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3436 }
3437
3438 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
3439 {
3440         /* RAWCLK_FREQ_VLV register updated from power well code */
3441         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
3442                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
3443 }
3444
3445 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
3446 {
3447         u32 clkcfg;
3448
3449         /*
3450          * hrawclock is 1/4 the FSB frequency
3451          *
3452          * Note that this only reads the state of the FSB
3453          * straps, not the actual FSB frequency. Some BIOSen
3454          * let you configure each independently. Ideally we'd
3455          * read out the actual FSB frequency but sadly we
3456          * don't know which registers have that information,
3457          * and all the relevant docs have gone to bit heaven :(
3458          */
3459         clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
3460
3461         if (IS_MOBILE(dev_priv)) {
3462                 switch (clkcfg) {
3463                 case CLKCFG_FSB_400:
3464                         return 100000;
3465                 case CLKCFG_FSB_533:
3466                         return 133333;
3467                 case CLKCFG_FSB_667:
3468                         return 166667;
3469                 case CLKCFG_FSB_800:
3470                         return 200000;
3471                 case CLKCFG_FSB_1067:
3472                         return 266667;
3473                 case CLKCFG_FSB_1333:
3474                         return 333333;
3475                 default:
3476                         MISSING_CASE(clkcfg);
3477                         return 133333;
3478                 }
3479         } else {
3480                 switch (clkcfg) {
3481                 case CLKCFG_FSB_400_ALT:
3482                         return 100000;
3483                 case CLKCFG_FSB_533:
3484                         return 133333;
3485                 case CLKCFG_FSB_667:
3486                         return 166667;
3487                 case CLKCFG_FSB_800:
3488                         return 200000;
3489                 case CLKCFG_FSB_1067_ALT:
3490                         return 266667;
3491                 case CLKCFG_FSB_1333_ALT:
3492                         return 333333;
3493                 case CLKCFG_FSB_1600_ALT:
3494                         return 400000;
3495                 default:
3496                         return 133333;
3497                 }
3498         }
3499 }
3500
3501 /**
3502  * intel_read_rawclk - Determine the current RAWCLK frequency
3503  * @dev_priv: i915 device
3504  *
3505  * Determine the current RAWCLK frequency. RAWCLK is a fixed
3506  * frequency clock so this needs to done only once.
3507  */
3508 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
3509 {
3510         u32 freq;
3511
3512         if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
3513                 /*
3514                  * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
3515                  * "RAWCLK_FREQ defaults to the values for 38.4 and does
3516                  * not need to be programmed."
3517                  */
3518                 freq = 38400;
3519         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3520                 freq = dg1_rawclk(dev_priv);
3521         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3522                 freq = cnp_rawclk(dev_priv);
3523         else if (HAS_PCH_SPLIT(dev_priv))
3524                 freq = pch_rawclk(dev_priv);
3525         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3526                 freq = vlv_hrawclk(dev_priv);
3527         else if (DISPLAY_VER(dev_priv) >= 3)
3528                 freq = i9xx_hrawclk(dev_priv);
3529         else
3530                 /* no rawclk on other platforms, or no need to know it */
3531                 return 0;
3532
3533         return freq;
3534 }
3535
3536 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3537 {
3538         struct drm_i915_private *i915 = m->private;
3539
3540         seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
3541         seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
3542         seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
3543
3544         return 0;
3545 }
3546
3547 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3548
3549 void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
3550 {
3551         struct drm_minor *minor = i915->drm.primary;
3552
3553         debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3554                             i915, &i915_cdclk_info_fops);
3555 }
3556
3557 static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
3558         .get_cdclk = bxt_get_cdclk,
3559         .set_cdclk = bxt_set_cdclk,
3560         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3561         .calc_voltage_level = rplu_calc_voltage_level,
3562 };
3563
3564 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3565         .get_cdclk = bxt_get_cdclk,
3566         .set_cdclk = bxt_set_cdclk,
3567         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3568         .calc_voltage_level = rplu_calc_voltage_level,
3569 };
3570
3571 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3572         .get_cdclk = bxt_get_cdclk,
3573         .set_cdclk = bxt_set_cdclk,
3574         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3575         .calc_voltage_level = tgl_calc_voltage_level,
3576 };
3577
3578 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3579         .get_cdclk = bxt_get_cdclk,
3580         .set_cdclk = bxt_set_cdclk,
3581         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3582         .calc_voltage_level = ehl_calc_voltage_level,
3583 };
3584
3585 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3586         .get_cdclk = bxt_get_cdclk,
3587         .set_cdclk = bxt_set_cdclk,
3588         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3589         .calc_voltage_level = icl_calc_voltage_level,
3590 };
3591
3592 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3593         .get_cdclk = bxt_get_cdclk,
3594         .set_cdclk = bxt_set_cdclk,
3595         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3596         .calc_voltage_level = bxt_calc_voltage_level,
3597 };
3598
3599 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3600         .get_cdclk = skl_get_cdclk,
3601         .set_cdclk = skl_set_cdclk,
3602         .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3603 };
3604
3605 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3606         .get_cdclk = bdw_get_cdclk,
3607         .set_cdclk = bdw_set_cdclk,
3608         .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3609 };
3610
3611 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3612         .get_cdclk = vlv_get_cdclk,
3613         .set_cdclk = chv_set_cdclk,
3614         .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3615 };
3616
3617 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3618         .get_cdclk = vlv_get_cdclk,
3619         .set_cdclk = vlv_set_cdclk,
3620         .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3621 };
3622
3623 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3624         .get_cdclk = hsw_get_cdclk,
3625         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3626 };
3627
3628 /* SNB, IVB, 965G, 945G */
3629 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3630         .get_cdclk = fixed_400mhz_get_cdclk,
3631         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3632 };
3633
3634 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3635         .get_cdclk = fixed_450mhz_get_cdclk,
3636         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3637 };
3638
3639 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3640         .get_cdclk = gm45_get_cdclk,
3641         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3642 };
3643
3644 /* G45 uses G33 */
3645
3646 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3647         .get_cdclk = i965gm_get_cdclk,
3648         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3649 };
3650
3651 /* i965G uses fixed 400 */
3652
3653 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3654         .get_cdclk = pnv_get_cdclk,
3655         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3656 };
3657
3658 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3659         .get_cdclk = g33_get_cdclk,
3660         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3661 };
3662
3663 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3664         .get_cdclk = i945gm_get_cdclk,
3665         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3666 };
3667
3668 /* i945G uses fixed 400 */
3669
3670 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3671         .get_cdclk = i915gm_get_cdclk,
3672         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3673 };
3674
3675 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3676         .get_cdclk = fixed_333mhz_get_cdclk,
3677         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3678 };
3679
3680 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3681         .get_cdclk = fixed_266mhz_get_cdclk,
3682         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3683 };
3684
3685 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3686         .get_cdclk = i85x_get_cdclk,
3687         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3688 };
3689
3690 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3691         .get_cdclk = fixed_200mhz_get_cdclk,
3692         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3693 };
3694
3695 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3696         .get_cdclk = fixed_133mhz_get_cdclk,
3697         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3698 };
3699
3700 /**
3701  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3702  * @dev_priv: i915 device
3703  */
3704 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
3705 {
3706         if (DISPLAY_VER(dev_priv) >= 20) {
3707                 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3708                 dev_priv->display.cdclk.table = lnl_cdclk_table;
3709         } else if (DISPLAY_VER(dev_priv) >= 14) {
3710                 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3711                 dev_priv->display.cdclk.table = mtl_cdclk_table;
3712         } else if (IS_DG2(dev_priv)) {
3713                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3714                 dev_priv->display.cdclk.table = dg2_cdclk_table;
3715         } else if (IS_ALDERLAKE_P(dev_priv)) {
3716                 /* Wa_22011320316:adl-p[a0] */
3717                 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
3718                         dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
3719                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3720                 } else if (IS_RAPTORLAKE_U(dev_priv)) {
3721                         dev_priv->display.cdclk.table = rplu_cdclk_table;
3722                         dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
3723                 } else {
3724                         dev_priv->display.cdclk.table = adlp_cdclk_table;
3725                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3726                 }
3727         } else if (IS_ROCKETLAKE(dev_priv)) {
3728                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3729                 dev_priv->display.cdclk.table = rkl_cdclk_table;
3730         } else if (DISPLAY_VER(dev_priv) >= 12) {
3731                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3732                 dev_priv->display.cdclk.table = icl_cdclk_table;
3733         } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3734                 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
3735                 dev_priv->display.cdclk.table = icl_cdclk_table;
3736         } else if (DISPLAY_VER(dev_priv) >= 11) {
3737                 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
3738                 dev_priv->display.cdclk.table = icl_cdclk_table;
3739         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
3740                 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
3741                 if (IS_GEMINILAKE(dev_priv))
3742                         dev_priv->display.cdclk.table = glk_cdclk_table;
3743                 else
3744                         dev_priv->display.cdclk.table = bxt_cdclk_table;
3745         } else if (DISPLAY_VER(dev_priv) == 9) {
3746                 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
3747         } else if (IS_BROADWELL(dev_priv)) {
3748                 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
3749         } else if (IS_HASWELL(dev_priv)) {
3750                 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
3751         } else if (IS_CHERRYVIEW(dev_priv)) {
3752                 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
3753         } else if (IS_VALLEYVIEW(dev_priv)) {
3754                 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
3755         } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
3756                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3757         } else if (IS_IRONLAKE(dev_priv)) {
3758                 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
3759         } else if (IS_GM45(dev_priv)) {
3760                 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
3761         } else if (IS_G45(dev_priv)) {
3762                 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3763         } else if (IS_I965GM(dev_priv)) {
3764                 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
3765         } else if (IS_I965G(dev_priv)) {
3766                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3767         } else if (IS_PINEVIEW(dev_priv)) {
3768                 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
3769         } else if (IS_G33(dev_priv)) {
3770                 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3771         } else if (IS_I945GM(dev_priv)) {
3772                 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
3773         } else if (IS_I945G(dev_priv)) {
3774                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3775         } else if (IS_I915GM(dev_priv)) {
3776                 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
3777         } else if (IS_I915G(dev_priv)) {
3778                 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
3779         } else if (IS_I865G(dev_priv)) {
3780                 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
3781         } else if (IS_I85X(dev_priv)) {
3782                 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
3783         } else if (IS_I845G(dev_priv)) {
3784                 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
3785         } else if (IS_I830(dev_priv)) {
3786                 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3787         }
3788
3789         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
3790                      "Unknown platform. Assuming i830\n"))
3791                 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3792 }