2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/time.h>
28 #include "intel_atomic.h"
29 #include "intel_atomic_plane.h"
30 #include "intel_audio.h"
32 #include "intel_cdclk.h"
33 #include "intel_crtc.h"
36 #include "intel_display_types.h"
37 #include "intel_mchbar_regs.h"
38 #include "intel_pci_config.h"
39 #include "intel_pcode.h"
40 #include "intel_psr.h"
41 #include "intel_vdsc.h"
42 #include "vlv_sideband.h"
47 * The display engine uses several different clocks to do its work. There
48 * are two main clocks involved that aren't directly related to the actual
49 * pixel clock or any symbol/bit clock of the actual output port. These
50 * are the core display clock (CDCLK) and RAWCLK.
52 * CDCLK clocks most of the display pipe logic, and thus its frequency
53 * must be high enough to support the rate at which pixels are flowing
54 * through the pipes. Downscaling must also be accounted as that increases
55 * the effective pixel rate.
57 * On several platforms the CDCLK frequency can be changed dynamically
58 * to minimize power consumption for a given display configuration.
59 * Typically changes to the CDCLK frequency require all the display pipes
60 * to be shut down while the frequency is being changed.
62 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
63 * DMC will not change the active CDCLK frequency however, so that part
64 * will still be performed by the driver directly.
66 * Several methods exist to change the CDCLK frequency, which ones are
67 * supported depends on the platform:
69 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
70 * - CD2X divider update. Single pipe can be active as the divider update
71 * can be synchronized with the pipe's start of vblank.
72 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
73 * - Squash waveform update. Pipes can be active.
74 * - Crawl and squash can also be done back to back. Pipes can be active.
76 * RAWCLK is a fixed frequency clock, often used by various auxiliary
77 * blocks such as AUX CH or backlight PWM. Hence the only thing we
78 * really need to know about RAWCLK is its frequency so that various
79 * dividers can be programmed correctly.
82 struct intel_cdclk_funcs {
83 void (*get_cdclk)(struct drm_i915_private *i915,
84 struct intel_cdclk_config *cdclk_config);
85 void (*set_cdclk)(struct drm_i915_private *i915,
86 const struct intel_cdclk_config *cdclk_config,
88 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
89 u8 (*calc_voltage_level)(int cdclk);
92 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
93 struct intel_cdclk_config *cdclk_config)
95 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
98 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
99 const struct intel_cdclk_config *cdclk_config,
102 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
105 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
106 struct intel_cdclk_state *cdclk_config)
108 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
111 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
114 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
117 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
118 struct intel_cdclk_config *cdclk_config)
120 cdclk_config->cdclk = 133333;
123 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
124 struct intel_cdclk_config *cdclk_config)
126 cdclk_config->cdclk = 200000;
129 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
130 struct intel_cdclk_config *cdclk_config)
132 cdclk_config->cdclk = 266667;
135 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
136 struct intel_cdclk_config *cdclk_config)
138 cdclk_config->cdclk = 333333;
141 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
142 struct intel_cdclk_config *cdclk_config)
144 cdclk_config->cdclk = 400000;
147 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
148 struct intel_cdclk_config *cdclk_config)
150 cdclk_config->cdclk = 450000;
153 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
154 struct intel_cdclk_config *cdclk_config)
156 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
160 * 852GM/852GMV only supports 133 MHz and the HPLLCC
161 * encoding is different :(
162 * FIXME is this the right way to detect 852GM/852GMV?
164 if (pdev->revision == 0x1) {
165 cdclk_config->cdclk = 133333;
169 pci_bus_read_config_word(pdev->bus,
170 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
172 /* Assume that the hardware is in the high speed state. This
173 * should be the default.
175 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
176 case GC_CLOCK_133_200:
177 case GC_CLOCK_133_200_2:
178 case GC_CLOCK_100_200:
179 cdclk_config->cdclk = 200000;
181 case GC_CLOCK_166_250:
182 cdclk_config->cdclk = 250000;
184 case GC_CLOCK_100_133:
185 cdclk_config->cdclk = 133333;
187 case GC_CLOCK_133_266:
188 case GC_CLOCK_133_266_2:
189 case GC_CLOCK_166_266:
190 cdclk_config->cdclk = 266667;
195 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
196 struct intel_cdclk_config *cdclk_config)
198 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
201 pci_read_config_word(pdev, GCFGC, &gcfgc);
203 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
204 cdclk_config->cdclk = 133333;
208 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
209 case GC_DISPLAY_CLOCK_333_320_MHZ:
210 cdclk_config->cdclk = 333333;
213 case GC_DISPLAY_CLOCK_190_200_MHZ:
214 cdclk_config->cdclk = 190000;
219 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
220 struct intel_cdclk_config *cdclk_config)
222 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
225 pci_read_config_word(pdev, GCFGC, &gcfgc);
227 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
228 cdclk_config->cdclk = 133333;
232 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
233 case GC_DISPLAY_CLOCK_333_320_MHZ:
234 cdclk_config->cdclk = 320000;
237 case GC_DISPLAY_CLOCK_190_200_MHZ:
238 cdclk_config->cdclk = 200000;
243 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
245 static const unsigned int blb_vco[8] = {
252 static const unsigned int pnv_vco[8] = {
259 static const unsigned int cl_vco[8] = {
268 static const unsigned int elk_vco[8] = {
274 static const unsigned int ctg_vco[8] = {
282 const unsigned int *vco_table;
286 /* FIXME other chipsets? */
287 if (IS_GM45(dev_priv))
289 else if (IS_G45(dev_priv))
291 else if (IS_I965GM(dev_priv))
293 else if (IS_PINEVIEW(dev_priv))
295 else if (IS_G33(dev_priv))
300 tmp = intel_de_read(dev_priv,
301 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
303 vco = vco_table[tmp & 0x7];
305 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
308 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
313 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
314 struct intel_cdclk_config *cdclk_config)
316 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
317 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
318 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
319 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
320 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
322 unsigned int cdclk_sel;
325 cdclk_config->vco = intel_hpll_vco(dev_priv);
327 pci_read_config_word(pdev, GCFGC, &tmp);
329 cdclk_sel = (tmp >> 4) & 0x7;
331 if (cdclk_sel >= ARRAY_SIZE(div_3200))
334 switch (cdclk_config->vco) {
336 div_table = div_3200;
339 div_table = div_4000;
342 div_table = div_4800;
345 div_table = div_5333;
351 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
352 div_table[cdclk_sel]);
356 drm_err(&dev_priv->drm,
357 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
358 cdclk_config->vco, tmp);
359 cdclk_config->cdclk = 190476;
362 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
363 struct intel_cdclk_config *cdclk_config)
365 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
368 pci_read_config_word(pdev, GCFGC, &gcfgc);
370 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
371 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
372 cdclk_config->cdclk = 266667;
374 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
375 cdclk_config->cdclk = 333333;
377 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
378 cdclk_config->cdclk = 444444;
380 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
381 cdclk_config->cdclk = 200000;
384 drm_err(&dev_priv->drm,
385 "Unknown pnv display core clock 0x%04x\n", gcfgc);
387 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
388 cdclk_config->cdclk = 133333;
390 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
391 cdclk_config->cdclk = 166667;
396 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
397 struct intel_cdclk_config *cdclk_config)
399 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
400 static const u8 div_3200[] = { 16, 10, 8 };
401 static const u8 div_4000[] = { 20, 12, 10 };
402 static const u8 div_5333[] = { 24, 16, 14 };
404 unsigned int cdclk_sel;
407 cdclk_config->vco = intel_hpll_vco(dev_priv);
409 pci_read_config_word(pdev, GCFGC, &tmp);
411 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
413 if (cdclk_sel >= ARRAY_SIZE(div_3200))
416 switch (cdclk_config->vco) {
418 div_table = div_3200;
421 div_table = div_4000;
424 div_table = div_5333;
430 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
431 div_table[cdclk_sel]);
435 drm_err(&dev_priv->drm,
436 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
437 cdclk_config->vco, tmp);
438 cdclk_config->cdclk = 200000;
441 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
442 struct intel_cdclk_config *cdclk_config)
444 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
445 unsigned int cdclk_sel;
448 cdclk_config->vco = intel_hpll_vco(dev_priv);
450 pci_read_config_word(pdev, GCFGC, &tmp);
452 cdclk_sel = (tmp >> 12) & 0x1;
454 switch (cdclk_config->vco) {
458 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
461 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
464 drm_err(&dev_priv->drm,
465 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
466 cdclk_config->vco, tmp);
467 cdclk_config->cdclk = 222222;
472 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
473 struct intel_cdclk_config *cdclk_config)
475 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
476 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
478 if (lcpll & LCPLL_CD_SOURCE_FCLK)
479 cdclk_config->cdclk = 800000;
480 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
481 cdclk_config->cdclk = 450000;
482 else if (freq == LCPLL_CLK_FREQ_450)
483 cdclk_config->cdclk = 450000;
484 else if (IS_HASWELL_ULT(dev_priv))
485 cdclk_config->cdclk = 337500;
487 cdclk_config->cdclk = 540000;
490 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
492 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
496 * We seem to get an unstable or solid color picture at 200MHz.
497 * Not sure what's wrong. For now use 200MHz only when all pipes
500 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
502 else if (min_cdclk > 266667)
504 else if (min_cdclk > 0)
510 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
512 if (IS_VALLEYVIEW(dev_priv)) {
513 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
515 else if (cdclk >= 266667)
521 * Specs are full of misinformation, but testing on actual
522 * hardware has shown that we just need to write the desired
523 * CCK divider into the Punit register.
525 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
529 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
530 struct intel_cdclk_config *cdclk_config)
534 vlv_iosf_sb_get(dev_priv,
535 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
537 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
538 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
539 CCK_DISPLAY_CLOCK_CONTROL,
542 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
544 vlv_iosf_sb_put(dev_priv,
545 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
547 if (IS_VALLEYVIEW(dev_priv))
548 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
551 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
552 DSPFREQGUAR_SHIFT_CHV;
555 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
557 unsigned int credits, default_credits;
559 if (IS_CHERRYVIEW(dev_priv))
560 default_credits = PFI_CREDIT(12);
562 default_credits = PFI_CREDIT(8);
564 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
565 /* CHV suggested value is 31 or 63 */
566 if (IS_CHERRYVIEW(dev_priv))
567 credits = PFI_CREDIT_63;
569 credits = PFI_CREDIT(15);
571 credits = default_credits;
575 * WA - write default credits before re-programming
576 * FIXME: should we also set the resend bit here?
578 intel_de_write(dev_priv, GCI_CONTROL,
579 VGA_FAST_MODE_DISABLE | default_credits);
581 intel_de_write(dev_priv, GCI_CONTROL,
582 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
585 * FIXME is this guaranteed to clear
586 * immediately or should we poll for it?
588 drm_WARN_ON(&dev_priv->drm,
589 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
592 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
593 const struct intel_cdclk_config *cdclk_config,
596 int cdclk = cdclk_config->cdclk;
597 u32 val, cmd = cdclk_config->voltage_level;
598 intel_wakeref_t wakeref;
612 /* There are cases where we can end up here with power domains
613 * off and a CDCLK frequency other than the minimum, like when
614 * issuing a modeset without actually changing any display after
615 * a system suspend. So grab the display core domain, which covers
616 * the HW blocks needed for the following programming.
618 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
620 vlv_iosf_sb_get(dev_priv,
621 BIT(VLV_IOSF_SB_CCK) |
622 BIT(VLV_IOSF_SB_BUNIT) |
623 BIT(VLV_IOSF_SB_PUNIT));
625 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
626 val &= ~DSPFREQGUAR_MASK;
627 val |= (cmd << DSPFREQGUAR_SHIFT);
628 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
629 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
630 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
632 drm_err(&dev_priv->drm,
633 "timed out waiting for CDclk change\n");
636 if (cdclk == 400000) {
639 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
642 /* adjust cdclk divider */
643 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
644 val &= ~CCK_FREQUENCY_VALUES;
646 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
648 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
649 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
651 drm_err(&dev_priv->drm,
652 "timed out waiting for CDclk change\n");
655 /* adjust self-refresh exit latency value */
656 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
660 * For high bandwidth configs, we set a higher latency in the bunit
661 * so that the core display fetch happens in time to avoid underruns.
664 val |= 4500 / 250; /* 4.5 usec */
666 val |= 3000 / 250; /* 3.0 usec */
667 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
669 vlv_iosf_sb_put(dev_priv,
670 BIT(VLV_IOSF_SB_CCK) |
671 BIT(VLV_IOSF_SB_BUNIT) |
672 BIT(VLV_IOSF_SB_PUNIT));
674 intel_update_cdclk(dev_priv);
676 vlv_program_pfi_credits(dev_priv);
678 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
681 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
682 const struct intel_cdclk_config *cdclk_config,
685 int cdclk = cdclk_config->cdclk;
686 u32 val, cmd = cdclk_config->voltage_level;
687 intel_wakeref_t wakeref;
700 /* There are cases where we can end up here with power domains
701 * off and a CDCLK frequency other than the minimum, like when
702 * issuing a modeset without actually changing any display after
703 * a system suspend. So grab the display core domain, which covers
704 * the HW blocks needed for the following programming.
706 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
708 vlv_punit_get(dev_priv);
709 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
710 val &= ~DSPFREQGUAR_MASK_CHV;
711 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
712 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
713 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
714 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
716 drm_err(&dev_priv->drm,
717 "timed out waiting for CDclk change\n");
720 vlv_punit_put(dev_priv);
722 intel_update_cdclk(dev_priv);
724 vlv_program_pfi_credits(dev_priv);
726 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
729 static int bdw_calc_cdclk(int min_cdclk)
731 if (min_cdclk > 540000)
733 else if (min_cdclk > 450000)
735 else if (min_cdclk > 337500)
741 static u8 bdw_calc_voltage_level(int cdclk)
756 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
757 struct intel_cdclk_config *cdclk_config)
759 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
760 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
762 if (lcpll & LCPLL_CD_SOURCE_FCLK)
763 cdclk_config->cdclk = 800000;
764 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
765 cdclk_config->cdclk = 450000;
766 else if (freq == LCPLL_CLK_FREQ_450)
767 cdclk_config->cdclk = 450000;
768 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
769 cdclk_config->cdclk = 540000;
770 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
771 cdclk_config->cdclk = 337500;
773 cdclk_config->cdclk = 675000;
776 * Can't read this out :( Let's assume it's
777 * at least what the CDCLK frequency requires.
779 cdclk_config->voltage_level =
780 bdw_calc_voltage_level(cdclk_config->cdclk);
783 static u32 bdw_cdclk_freq_sel(int cdclk)
790 return LCPLL_CLK_FREQ_337_5_BDW;
792 return LCPLL_CLK_FREQ_450;
794 return LCPLL_CLK_FREQ_54O_BDW;
796 return LCPLL_CLK_FREQ_675_BDW;
800 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
801 const struct intel_cdclk_config *cdclk_config,
804 int cdclk = cdclk_config->cdclk;
807 if (drm_WARN(&dev_priv->drm,
808 (intel_de_read(dev_priv, LCPLL_CTL) &
809 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
810 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
811 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
812 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
813 "trying to change cdclk frequency with cdclk not enabled\n"))
816 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
818 drm_err(&dev_priv->drm,
819 "failed to inform pcode about cdclk change\n");
823 intel_de_rmw(dev_priv, LCPLL_CTL,
824 0, LCPLL_CD_SOURCE_FCLK);
827 * According to the spec, it should be enough to poll for this 1 us.
828 * However, extensive testing shows that this can take longer.
830 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
831 LCPLL_CD_SOURCE_FCLK_DONE, 100))
832 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
834 intel_de_rmw(dev_priv, LCPLL_CTL,
835 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
837 intel_de_rmw(dev_priv, LCPLL_CTL,
838 LCPLL_CD_SOURCE_FCLK, 0);
840 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
841 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
842 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
844 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
845 cdclk_config->voltage_level);
847 intel_de_write(dev_priv, CDCLK_FREQ,
848 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
850 intel_update_cdclk(dev_priv);
853 static int skl_calc_cdclk(int min_cdclk, int vco)
855 if (vco == 8640000) {
856 if (min_cdclk > 540000)
858 else if (min_cdclk > 432000)
860 else if (min_cdclk > 308571)
865 if (min_cdclk > 540000)
867 else if (min_cdclk > 450000)
869 else if (min_cdclk > 337500)
876 static u8 skl_calc_voltage_level(int cdclk)
880 else if (cdclk > 450000)
882 else if (cdclk > 337500)
888 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
889 struct intel_cdclk_config *cdclk_config)
893 cdclk_config->ref = 24000;
894 cdclk_config->vco = 0;
896 val = intel_de_read(dev_priv, LCPLL1_CTL);
897 if ((val & LCPLL_PLL_ENABLE) == 0)
900 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
903 val = intel_de_read(dev_priv, DPLL_CTRL1);
905 if (drm_WARN_ON(&dev_priv->drm,
906 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
907 DPLL_CTRL1_SSC(SKL_DPLL0) |
908 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
909 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
912 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
913 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
914 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
915 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
916 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
917 cdclk_config->vco = 8100000;
919 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
920 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
921 cdclk_config->vco = 8640000;
924 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
929 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
930 struct intel_cdclk_config *cdclk_config)
934 skl_dpll0_update(dev_priv, cdclk_config);
936 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
938 if (cdclk_config->vco == 0)
941 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
943 if (cdclk_config->vco == 8640000) {
944 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
945 case CDCLK_FREQ_450_432:
946 cdclk_config->cdclk = 432000;
948 case CDCLK_FREQ_337_308:
949 cdclk_config->cdclk = 308571;
952 cdclk_config->cdclk = 540000;
954 case CDCLK_FREQ_675_617:
955 cdclk_config->cdclk = 617143;
958 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
962 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
963 case CDCLK_FREQ_450_432:
964 cdclk_config->cdclk = 450000;
966 case CDCLK_FREQ_337_308:
967 cdclk_config->cdclk = 337500;
970 cdclk_config->cdclk = 540000;
972 case CDCLK_FREQ_675_617:
973 cdclk_config->cdclk = 675000;
976 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
983 * Can't read this out :( Let's assume it's
984 * at least what the CDCLK frequency requires.
986 cdclk_config->voltage_level =
987 skl_calc_voltage_level(cdclk_config->cdclk);
990 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
991 static int skl_cdclk_decimal(int cdclk)
993 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
996 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
999 bool changed = dev_priv->skl_preferred_vco_freq != vco;
1001 dev_priv->skl_preferred_vco_freq = vco;
1004 intel_update_max_cdclk(dev_priv);
1007 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
1009 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
1012 * We always enable DPLL0 with the lowest link rate possible, but still
1013 * taking into account the VCO required to operate the eDP panel at the
1014 * desired frequency. The usual DP link rates operate with a VCO of
1015 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1016 * The modeset code is responsible for the selection of the exact link
1017 * rate later on, with the constraint of choosing a frequency that
1021 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1023 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1026 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
1028 intel_de_rmw(dev_priv, DPLL_CTRL1,
1029 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1030 DPLL_CTRL1_SSC(SKL_DPLL0) |
1031 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1032 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1033 skl_dpll0_link_rate(dev_priv, vco));
1034 intel_de_posting_read(dev_priv, DPLL_CTRL1);
1036 intel_de_rmw(dev_priv, LCPLL1_CTL,
1037 0, LCPLL_PLL_ENABLE);
1039 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1040 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
1042 dev_priv->display.cdclk.hw.vco = vco;
1044 /* We'll want to keep using the current vco from now on. */
1045 skl_set_preferred_cdclk_vco(dev_priv, vco);
1048 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
1050 intel_de_rmw(dev_priv, LCPLL1_CTL,
1051 LCPLL_PLL_ENABLE, 0);
1053 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1054 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1056 dev_priv->display.cdclk.hw.vco = 0;
1059 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
1064 drm_WARN_ON(&dev_priv->drm,
1065 cdclk != dev_priv->display.cdclk.hw.bypass);
1066 drm_WARN_ON(&dev_priv->drm, vco != 0);
1070 return CDCLK_FREQ_337_308;
1073 return CDCLK_FREQ_450_432;
1075 return CDCLK_FREQ_540;
1078 return CDCLK_FREQ_675_617;
1082 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1083 const struct intel_cdclk_config *cdclk_config,
1086 int cdclk = cdclk_config->cdclk;
1087 int vco = cdclk_config->vco;
1088 u32 freq_select, cdclk_ctl;
1092 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1093 * unsupported on SKL. In theory this should never happen since only
1094 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1095 * supported on SKL either, see the above WA. WARN whenever trying to
1096 * use the corresponding VCO freq as that always leads to using the
1097 * minimum 308MHz CDCLK.
1099 drm_WARN_ON_ONCE(&dev_priv->drm,
1100 IS_SKYLAKE(dev_priv) && vco == 8640000);
1102 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1103 SKL_CDCLK_PREPARE_FOR_CHANGE,
1104 SKL_CDCLK_READY_FOR_CHANGE,
1105 SKL_CDCLK_READY_FOR_CHANGE, 3);
1107 drm_err(&dev_priv->drm,
1108 "Failed to inform PCU about cdclk change (%d)\n", ret);
1112 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1114 if (dev_priv->display.cdclk.hw.vco != 0 &&
1115 dev_priv->display.cdclk.hw.vco != vco)
1116 skl_dpll0_disable(dev_priv);
1118 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1120 if (dev_priv->display.cdclk.hw.vco != vco) {
1121 /* Wa Display #1183: skl,kbl,cfl */
1122 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1123 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1124 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1127 /* Wa Display #1183: skl,kbl,cfl */
1128 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1129 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1130 intel_de_posting_read(dev_priv, CDCLK_CTL);
1132 if (dev_priv->display.cdclk.hw.vco != vco)
1133 skl_dpll0_enable(dev_priv, vco);
1135 /* Wa Display #1183: skl,kbl,cfl */
1136 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1137 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1139 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1140 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1142 /* Wa Display #1183: skl,kbl,cfl */
1143 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1144 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1145 intel_de_posting_read(dev_priv, CDCLK_CTL);
1147 /* inform PCU of the change */
1148 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1149 cdclk_config->voltage_level);
1151 intel_update_cdclk(dev_priv);
1154 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1156 u32 cdctl, expected;
1159 * check if the pre-os initialized the display
1160 * There is SWF18 scratchpad register defined which is set by the
1161 * pre-os which can be used by the OS drivers to check the status
1163 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1166 intel_update_cdclk(dev_priv);
1167 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1169 /* Is PLL enabled and locked ? */
1170 if (dev_priv->display.cdclk.hw.vco == 0 ||
1171 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
1174 /* DPLL okay; verify the cdclock
1176 * Noticed in some instances that the freq selection is correct but
1177 * decimal part is programmed wrong from BIOS where pre-os does not
1178 * enable display. Verify the same as well.
1180 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1181 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1182 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
1183 if (cdctl == expected)
1184 /* All well; nothing to sanitize */
1188 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1190 /* force cdclk programming */
1191 dev_priv->display.cdclk.hw.cdclk = 0;
1192 /* force full PLL disable + enable */
1193 dev_priv->display.cdclk.hw.vco = ~0;
1196 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1198 struct intel_cdclk_config cdclk_config;
1200 skl_sanitize_cdclk(dev_priv);
1202 if (dev_priv->display.cdclk.hw.cdclk != 0 &&
1203 dev_priv->display.cdclk.hw.vco != 0) {
1205 * Use the current vco as our initial
1206 * guess as to what the preferred vco is.
1208 if (dev_priv->skl_preferred_vco_freq == 0)
1209 skl_set_preferred_cdclk_vco(dev_priv,
1210 dev_priv->display.cdclk.hw.vco);
1214 cdclk_config = dev_priv->display.cdclk.hw;
1216 cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1217 if (cdclk_config.vco == 0)
1218 cdclk_config.vco = 8100000;
1219 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1220 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1222 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1225 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1227 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
1229 cdclk_config.cdclk = cdclk_config.bypass;
1230 cdclk_config.vco = 0;
1231 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1233 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1236 struct intel_cdclk_vals {
1243 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1244 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1245 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1246 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1247 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1248 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1252 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1253 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1254 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1255 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1259 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1260 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1261 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1262 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1263 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1264 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1265 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1267 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1268 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1269 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1270 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1271 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1272 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1274 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1275 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1276 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1277 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1278 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1279 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1283 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1284 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1285 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1286 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1287 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1288 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1289 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1291 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1292 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1293 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1294 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1295 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1296 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1298 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1299 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1300 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1301 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1302 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1303 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1307 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1308 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1309 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1310 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1312 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1313 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1314 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1316 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1317 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1318 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1322 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1323 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1324 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1325 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1326 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1327 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1329 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1330 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1331 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1332 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1333 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1335 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1336 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1337 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1338 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1339 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1343 static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1344 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1345 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1346 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1347 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1348 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1349 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1351 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1352 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1353 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1354 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1355 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1356 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1358 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1359 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1360 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1361 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1362 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1363 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1367 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1368 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1369 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1370 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1371 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1372 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1373 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1374 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1375 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1376 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1377 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1378 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1379 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1380 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1384 static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1385 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1386 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1387 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1388 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1389 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1390 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1394 static const struct intel_cdclk_vals lnl_cdclk_table[] = {
1395 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1396 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1397 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1398 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1399 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1400 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1401 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1402 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1403 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1404 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1405 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1406 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1407 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1408 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1409 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1410 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1411 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1412 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1413 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1414 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1415 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1419 static const int cdclk_squash_len = 16;
1421 static int cdclk_squash_divider(u16 waveform)
1423 return hweight16(waveform ?: 0xffff);
1426 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1428 /* 2 * cd2x divider */
1429 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1430 cdclk * cdclk_squash_len);
1433 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1435 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1438 for (i = 0; table[i].refclk; i++)
1439 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1440 table[i].cdclk >= min_cdclk)
1441 return table[i].cdclk;
1443 drm_WARN(&dev_priv->drm, 1,
1444 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1445 min_cdclk, dev_priv->display.cdclk.hw.ref);
1449 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1451 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1454 if (cdclk == dev_priv->display.cdclk.hw.bypass)
1457 for (i = 0; table[i].refclk; i++)
1458 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1459 table[i].cdclk == cdclk)
1460 return dev_priv->display.cdclk.hw.ref * table[i].ratio;
1462 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1463 cdclk, dev_priv->display.cdclk.hw.ref);
1467 static u8 bxt_calc_voltage_level(int cdclk)
1469 return DIV_ROUND_UP(cdclk, 25000);
1472 static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1473 const int voltage_level_max_cdclk[])
1477 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1478 if (cdclk <= voltage_level_max_cdclk[voltage_level])
1479 return voltage_level;
1482 MISSING_CASE(cdclk);
1483 return num_voltage_levels - 1;
1486 static u8 icl_calc_voltage_level(int cdclk)
1488 static const int icl_voltage_level_max_cdclk[] = {
1494 return calc_voltage_level(cdclk,
1495 ARRAY_SIZE(icl_voltage_level_max_cdclk),
1496 icl_voltage_level_max_cdclk);
1499 static u8 ehl_calc_voltage_level(int cdclk)
1501 static const int ehl_voltage_level_max_cdclk[] = {
1506 * Bspec lists the limit as 556.8 MHz, but some JSL
1507 * development boards (at least) boot with 652.8 MHz
1512 return calc_voltage_level(cdclk,
1513 ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1514 ehl_voltage_level_max_cdclk);
1517 static u8 tgl_calc_voltage_level(int cdclk)
1519 static const int tgl_voltage_level_max_cdclk[] = {
1526 return calc_voltage_level(cdclk,
1527 ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1528 tgl_voltage_level_max_cdclk);
1531 static u8 rplu_calc_voltage_level(int cdclk)
1533 static const int rplu_voltage_level_max_cdclk[] = {
1540 return calc_voltage_level(cdclk,
1541 ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1542 rplu_voltage_level_max_cdclk);
1545 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1546 struct intel_cdclk_config *cdclk_config)
1548 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1554 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1555 cdclk_config->ref = 24000;
1557 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1558 cdclk_config->ref = 19200;
1560 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1561 cdclk_config->ref = 38400;
1566 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1567 struct intel_cdclk_config *cdclk_config)
1571 if (IS_DG2(dev_priv))
1572 cdclk_config->ref = 38400;
1573 else if (DISPLAY_VER(dev_priv) >= 11)
1574 icl_readout_refclk(dev_priv, cdclk_config);
1576 cdclk_config->ref = 19200;
1578 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1579 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1580 (val & BXT_DE_PLL_LOCK) == 0) {
1582 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1583 * setting it to zero is a way to signal that.
1585 cdclk_config->vco = 0;
1590 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1591 * gen9lp had it in a separate PLL control register.
1593 if (DISPLAY_VER(dev_priv) >= 11)
1594 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1596 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1598 cdclk_config->vco = ratio * cdclk_config->ref;
1601 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1602 struct intel_cdclk_config *cdclk_config)
1608 bxt_de_pll_readout(dev_priv, cdclk_config);
1610 if (DISPLAY_VER(dev_priv) >= 12)
1611 cdclk_config->bypass = cdclk_config->ref / 2;
1612 else if (DISPLAY_VER(dev_priv) >= 11)
1613 cdclk_config->bypass = 50000;
1615 cdclk_config->bypass = cdclk_config->ref;
1617 if (cdclk_config->vco == 0) {
1618 cdclk_config->cdclk = cdclk_config->bypass;
1622 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1625 case BXT_CDCLK_CD2X_DIV_SEL_1:
1628 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1631 case BXT_CDCLK_CD2X_DIV_SEL_2:
1634 case BXT_CDCLK_CD2X_DIV_SEL_4:
1638 MISSING_CASE(divider);
1642 if (HAS_CDCLK_SQUASH(dev_priv))
1643 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
1645 if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1649 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1650 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1652 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1653 cdclk_config->vco, size * div);
1655 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1660 * Can't read this out :( Let's assume it's
1661 * at least what the CDCLK frequency requires.
1663 cdclk_config->voltage_level =
1664 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
1667 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1669 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1672 if (intel_de_wait_for_clear(dev_priv,
1673 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1674 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1676 dev_priv->display.cdclk.hw.vco = 0;
1679 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1681 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1683 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
1684 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1686 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1689 if (intel_de_wait_for_set(dev_priv,
1690 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1691 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1693 dev_priv->display.cdclk.hw.vco = vco;
1696 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1698 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
1699 BXT_DE_PLL_PLL_ENABLE, 0);
1702 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1703 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
1705 dev_priv->display.cdclk.hw.vco = 0;
1708 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1710 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1713 val = ICL_CDCLK_PLL_RATIO(ratio);
1714 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1716 val |= BXT_DE_PLL_PLL_ENABLE;
1717 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1720 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1721 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
1723 dev_priv->display.cdclk.hw.vco = vco;
1726 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
1728 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1731 /* Write PLL ratio without disabling */
1732 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1733 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1735 /* Submit freq change request */
1736 val |= BXT_DE_PLL_FREQ_REQ;
1737 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1740 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
1741 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1742 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
1744 val &= ~BXT_DE_PLL_FREQ_REQ;
1745 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1747 dev_priv->display.cdclk.hw.vco = vco;
1750 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1752 if (DISPLAY_VER(dev_priv) >= 12) {
1753 if (pipe == INVALID_PIPE)
1754 return TGL_CDCLK_CD2X_PIPE_NONE;
1756 return TGL_CDCLK_CD2X_PIPE(pipe);
1757 } else if (DISPLAY_VER(dev_priv) >= 11) {
1758 if (pipe == INVALID_PIPE)
1759 return ICL_CDCLK_CD2X_PIPE_NONE;
1761 return ICL_CDCLK_CD2X_PIPE(pipe);
1763 if (pipe == INVALID_PIPE)
1764 return BXT_CDCLK_CD2X_PIPE_NONE;
1766 return BXT_CDCLK_CD2X_PIPE(pipe);
1770 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
1771 int cdclk, int vco, u16 waveform)
1773 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1774 switch (cdclk_divider(cdclk, vco, waveform)) {
1776 drm_WARN_ON(&dev_priv->drm,
1777 cdclk != dev_priv->display.cdclk.hw.bypass);
1778 drm_WARN_ON(&dev_priv->drm, vco != 0);
1781 return BXT_CDCLK_CD2X_DIV_SEL_1;
1783 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1785 return BXT_CDCLK_CD2X_DIV_SEL_2;
1787 return BXT_CDCLK_CD2X_DIV_SEL_4;
1791 static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
1794 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1797 if (cdclk == dev_priv->display.cdclk.hw.bypass)
1800 for (i = 0; table[i].refclk; i++)
1801 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1802 table[i].cdclk == cdclk)
1803 return table[i].waveform;
1805 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1806 cdclk, dev_priv->display.cdclk.hw.ref);
1811 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1813 if (i915->display.cdclk.hw.vco != 0 &&
1814 i915->display.cdclk.hw.vco != vco)
1815 icl_cdclk_pll_disable(i915);
1817 if (i915->display.cdclk.hw.vco != vco)
1818 icl_cdclk_pll_enable(i915, vco);
1821 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1823 if (i915->display.cdclk.hw.vco != 0 &&
1824 i915->display.cdclk.hw.vco != vco)
1825 bxt_de_pll_disable(i915);
1827 if (i915->display.cdclk.hw.vco != vco)
1828 bxt_de_pll_enable(i915, vco);
1831 static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
1837 squash_ctl = CDCLK_SQUASH_ENABLE |
1838 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1840 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
1843 static bool cdclk_pll_is_unknown(unsigned int vco)
1846 * Ensure driver does not take the crawl path for the
1847 * case when the vco is set to ~0 in the
1853 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
1854 const struct intel_cdclk_config *old_cdclk_config,
1855 const struct intel_cdclk_config *new_cdclk_config,
1856 struct intel_cdclk_config *mid_cdclk_config)
1858 u16 old_waveform, new_waveform, mid_waveform;
1859 int old_div, new_div, mid_div;
1861 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1862 if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1865 /* Return if both Squash and Crawl are not present */
1866 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
1869 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
1870 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
1872 /* Return if Squash only or Crawl only is the desired action */
1873 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
1874 old_cdclk_config->vco == new_cdclk_config->vco ||
1875 old_waveform == new_waveform)
1878 old_div = cdclk_divider(old_cdclk_config->cdclk,
1879 old_cdclk_config->vco, old_waveform);
1880 new_div = cdclk_divider(new_cdclk_config->cdclk,
1881 new_cdclk_config->vco, new_waveform);
1884 * Should not happen currently. We might need more midpoint
1885 * transitions if we need to also change the cd2x divider.
1887 if (drm_WARN_ON(&i915->drm, old_div != new_div))
1890 *mid_cdclk_config = *new_cdclk_config;
1893 * Populate the mid_cdclk_config accordingly.
1894 * - If moving to a higher cdclk, the desired action is squashing.
1895 * The mid cdclk config should have the new (squash) waveform.
1896 * - If moving to a lower cdclk, the desired action is crawling.
1897 * The mid cdclk config should have the new vco.
1900 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
1901 mid_cdclk_config->vco = old_cdclk_config->vco;
1903 mid_waveform = new_waveform;
1905 mid_cdclk_config->vco = new_cdclk_config->vco;
1907 mid_waveform = old_waveform;
1910 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
1911 mid_cdclk_config->vco,
1912 cdclk_squash_len * mid_div);
1914 /* make sure the mid clock came out sane */
1916 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
1917 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
1918 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
1919 i915->display.cdclk.max_cdclk_freq);
1920 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
1926 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
1928 return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
1929 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
1930 IS_DG2(dev_priv)) &&
1931 dev_priv->display.cdclk.hw.vco > 0;
1934 static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
1935 const struct intel_cdclk_config *cdclk_config,
1938 int cdclk = cdclk_config->cdclk;
1939 int vco = cdclk_config->vco;
1943 waveform = cdclk_squash_waveform(i915, cdclk);
1945 val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) |
1946 bxt_cdclk_cd2x_pipe(i915, pipe);
1949 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1952 if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) &&
1954 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1956 if (DISPLAY_VER(i915) >= 20)
1957 val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
1959 val |= skl_cdclk_decimal(cdclk);
1964 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
1965 const struct intel_cdclk_config *cdclk_config,
1968 int cdclk = cdclk_config->cdclk;
1969 int vco = cdclk_config->vco;
1972 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
1973 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
1974 if (dev_priv->display.cdclk.hw.vco != vco)
1975 adlp_cdclk_pll_crawl(dev_priv, vco);
1976 } else if (DISPLAY_VER(dev_priv) >= 11) {
1977 /* wa_15010685871: dg2, mtl */
1978 if (pll_enable_wa_needed(dev_priv))
1979 dg2_cdclk_squash_program(dev_priv, 0);
1981 icl_cdclk_pll_update(dev_priv, vco);
1983 bxt_cdclk_pll_update(dev_priv, vco);
1985 waveform = cdclk_squash_waveform(dev_priv, cdclk);
1987 if (HAS_CDCLK_SQUASH(dev_priv))
1988 dg2_cdclk_squash_program(dev_priv, waveform);
1990 intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe));
1992 if (pipe != INVALID_PIPE)
1993 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
1996 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1997 const struct intel_cdclk_config *cdclk_config,
2000 struct intel_cdclk_config mid_cdclk_config;
2001 int cdclk = cdclk_config->cdclk;
2005 * Inform power controller of upcoming frequency change.
2006 * Display versions 14 and beyond do not follow the PUnit
2007 * mailbox communication, skip
2010 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
2012 else if (DISPLAY_VER(dev_priv) >= 11)
2013 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2014 SKL_CDCLK_PREPARE_FOR_CHANGE,
2015 SKL_CDCLK_READY_FOR_CHANGE,
2016 SKL_CDCLK_READY_FOR_CHANGE, 3);
2019 * BSpec requires us to wait up to 150usec, but that leads to
2020 * timeouts; the 2ms used here is based on experiment.
2022 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2023 HSW_PCODE_DE_WRITE_FREQ_REQ,
2024 0x80000000, 150, 2);
2027 drm_err(&dev_priv->drm,
2028 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2033 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
2034 cdclk_config, &mid_cdclk_config)) {
2035 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
2036 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
2038 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
2041 if (DISPLAY_VER(dev_priv) >= 14)
2043 * NOOP - No Pcode communication needed for
2044 * Display versions 14 and beyond
2046 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv))
2047 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2048 cdclk_config->voltage_level);
2049 if (DISPLAY_VER(dev_priv) < 11) {
2051 * The timeout isn't specified, the 2ms used here is based on
2053 * FIXME: Waiting for the request completion could be delayed
2054 * until the next PCODE request based on BSpec.
2056 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2057 HSW_PCODE_DE_WRITE_FREQ_REQ,
2058 cdclk_config->voltage_level,
2062 drm_err(&dev_priv->drm,
2063 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
2068 intel_update_cdclk(dev_priv);
2070 if (DISPLAY_VER(dev_priv) >= 11)
2072 * Can't read out the voltage level :(
2073 * Let's just assume everything is as expected.
2075 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
2078 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
2080 u32 cdctl, expected;
2083 intel_update_cdclk(dev_priv);
2084 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
2086 if (dev_priv->display.cdclk.hw.vco == 0 ||
2087 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
2090 /* Make sure this is a legal cdclk value for the platform */
2091 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
2092 if (cdclk != dev_priv->display.cdclk.hw.cdclk)
2095 /* Make sure the VCO is correct for the cdclk */
2096 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2097 if (vco != dev_priv->display.cdclk.hw.vco)
2101 * Some BIOS versions leave an incorrect decimal frequency value and
2102 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2103 * so sanitize this register.
2105 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
2106 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);
2109 * Let's ignore the pipe field, since BIOS could have configured the
2110 * dividers both synching to an active pipe, or asynchronously
2113 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2114 expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2116 if (cdctl == expected)
2117 /* All well; nothing to sanitize */
2121 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
2123 /* force cdclk programming */
2124 dev_priv->display.cdclk.hw.cdclk = 0;
2126 /* force full PLL disable + enable */
2127 dev_priv->display.cdclk.hw.vco = ~0;
2130 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
2132 struct intel_cdclk_config cdclk_config;
2134 bxt_sanitize_cdclk(dev_priv);
2136 if (dev_priv->display.cdclk.hw.cdclk != 0 &&
2137 dev_priv->display.cdclk.hw.vco != 0)
2140 cdclk_config = dev_priv->display.cdclk.hw;
2144 * - The initial CDCLK needs to be read from VBT.
2145 * Need to make this change after VBT has changes for BXT.
2147 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
2148 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
2149 cdclk_config.voltage_level =
2150 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2152 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2155 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
2157 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
2159 cdclk_config.cdclk = cdclk_config.bypass;
2160 cdclk_config.vco = 0;
2161 cdclk_config.voltage_level =
2162 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2164 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2168 * intel_cdclk_init_hw - Initialize CDCLK hardware
2169 * @i915: i915 device
2171 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2172 * sanitizing the state of the hardware if needed. This is generally done only
2173 * during the display core initialization sequence, after which the DMC will
2174 * take care of turning CDCLK off/on as needed.
2176 void intel_cdclk_init_hw(struct drm_i915_private *i915)
2178 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2179 bxt_cdclk_init_hw(i915);
2180 else if (DISPLAY_VER(i915) == 9)
2181 skl_cdclk_init_hw(i915);
2185 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2186 * @i915: i915 device
2188 * Uninitialize CDCLK. This is done only during the display core
2189 * uninitialization sequence.
2191 void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
2193 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2194 bxt_cdclk_uninit_hw(i915);
2195 else if (DISPLAY_VER(i915) == 9)
2196 skl_cdclk_uninit_hw(i915);
2199 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
2200 const struct intel_cdclk_config *a,
2201 const struct intel_cdclk_config *b)
2206 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco));
2208 if (a->vco == 0 || b->vco == 0)
2211 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
2214 old_waveform = cdclk_squash_waveform(i915, a->cdclk);
2215 new_waveform = cdclk_squash_waveform(i915, b->cdclk);
2217 return a->vco != b->vco &&
2218 old_waveform != new_waveform;
2221 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
2222 const struct intel_cdclk_config *a,
2223 const struct intel_cdclk_config *b)
2227 if (!HAS_CDCLK_CRAWL(dev_priv))
2231 * The vco and cd2x divider will change independently
2232 * from each, so we disallow cd2x change when crawling.
2234 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2235 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2237 return a->vco != 0 && b->vco != 0 &&
2243 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
2244 const struct intel_cdclk_config *a,
2245 const struct intel_cdclk_config *b)
2248 * FIXME should store a bit more state in intel_cdclk_config
2249 * to differentiate squasher vs. cd2x divider properly. For
2250 * the moment all platforms with squasher use a fixed cd2x
2253 if (!HAS_CDCLK_SQUASH(dev_priv))
2256 return a->cdclk != b->cdclk &&
2263 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2264 * configurations requires a modeset on all pipes
2265 * @a: first CDCLK configuration
2266 * @b: second CDCLK configuration
2269 * True if changing between the two CDCLK configurations
2270 * requires all pipes to be off, false if not.
2272 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
2273 const struct intel_cdclk_config *b)
2275 return a->cdclk != b->cdclk ||
2281 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2282 * configurations requires only a cd2x divider update
2283 * @dev_priv: i915 device
2284 * @a: first CDCLK configuration
2285 * @b: second CDCLK configuration
2288 * True if changing between the two CDCLK configurations
2289 * can be done with just a cd2x divider update, false if not.
2291 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
2292 const struct intel_cdclk_config *a,
2293 const struct intel_cdclk_config *b)
2295 /* Older hw doesn't have the capability */
2296 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
2300 * FIXME should store a bit more state in intel_cdclk_config
2301 * to differentiate squasher vs. cd2x divider properly. For
2302 * the moment all platforms with squasher use a fixed cd2x
2305 if (HAS_CDCLK_SQUASH(dev_priv))
2308 return a->cdclk != b->cdclk &&
2315 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2316 * @a: first CDCLK configuration
2317 * @b: second CDCLK configuration
2320 * True if the CDCLK configurations don't match, false if they do.
2322 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2323 const struct intel_cdclk_config *b)
2325 return intel_cdclk_needs_modeset(a, b) ||
2326 a->voltage_level != b->voltage_level;
2329 void intel_cdclk_dump_config(struct drm_i915_private *i915,
2330 const struct intel_cdclk_config *cdclk_config,
2331 const char *context)
2333 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2334 context, cdclk_config->cdclk, cdclk_config->vco,
2335 cdclk_config->ref, cdclk_config->bypass,
2336 cdclk_config->voltage_level);
2339 static void intel_pcode_notify(struct drm_i915_private *i915,
2341 u8 active_pipe_count,
2343 bool cdclk_update_valid,
2344 bool pipe_count_update_valid)
2347 u32 update_mask = 0;
2352 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2354 if (cdclk_update_valid)
2355 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2357 if (pipe_count_update_valid)
2358 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2360 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2361 SKL_CDCLK_PREPARE_FOR_CHANGE |
2363 SKL_CDCLK_READY_FOR_CHANGE,
2364 SKL_CDCLK_READY_FOR_CHANGE, 3);
2367 "Failed to inform PCU about display config (err %d)\n",
2372 * intel_set_cdclk - Push the CDCLK configuration to the hardware
2373 * @dev_priv: i915 device
2374 * @cdclk_config: new CDCLK configuration
2375 * @pipe: pipe with which to synchronize the update
2377 * Program the hardware based on the passed in CDCLK state,
2380 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2381 const struct intel_cdclk_config *cdclk_config,
2384 struct intel_encoder *encoder;
2386 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
2389 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
2392 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
2394 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2395 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2397 intel_psr_pause(intel_dp);
2400 intel_audio_cdclk_change_pre(dev_priv);
2403 * Lock aux/gmbus while we change cdclk in case those
2404 * functions use cdclk. Not all platforms/ports do,
2405 * but we'll lock them all for simplicity.
2407 mutex_lock(&dev_priv->display.gmbus.mutex);
2408 for_each_intel_dp(&dev_priv->drm, encoder) {
2409 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2411 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2412 &dev_priv->display.gmbus.mutex);
2415 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
2417 for_each_intel_dp(&dev_priv->drm, encoder) {
2418 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2420 mutex_unlock(&intel_dp->aux.hw_mutex);
2422 mutex_unlock(&dev_priv->display.gmbus.mutex);
2424 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2425 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2427 intel_psr_resume(intel_dp);
2430 intel_audio_cdclk_change_post(dev_priv);
2432 if (drm_WARN(&dev_priv->drm,
2433 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
2434 "cdclk state doesn't match!\n")) {
2435 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
2436 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
2440 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2442 struct drm_i915_private *i915 = to_i915(state->base.dev);
2443 const struct intel_cdclk_state *old_cdclk_state =
2444 intel_atomic_get_old_cdclk_state(state);
2445 const struct intel_cdclk_state *new_cdclk_state =
2446 intel_atomic_get_new_cdclk_state(state);
2447 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2448 bool change_cdclk, update_pipe_count;
2450 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2451 &new_cdclk_state->actual) &&
2452 new_cdclk_state->active_pipes ==
2453 old_cdclk_state->active_pipes)
2456 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2457 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2459 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2460 update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2461 hweight8(old_cdclk_state->active_pipes);
2464 * According to "Sequence Before Frequency Change",
2465 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2466 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2467 * which basically means we choose the maximum of old and new CDCLK, if we know both
2470 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2473 * According to "Sequence For Pipe Count Change",
2474 * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2475 * (power well is enabled)
2476 * no action if it is decreasing, before the change
2478 if (update_pipe_count)
2479 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2481 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2482 change_cdclk, update_pipe_count);
2485 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2487 struct drm_i915_private *i915 = to_i915(state->base.dev);
2488 const struct intel_cdclk_state *new_cdclk_state =
2489 intel_atomic_get_new_cdclk_state(state);
2490 const struct intel_cdclk_state *old_cdclk_state =
2491 intel_atomic_get_old_cdclk_state(state);
2492 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2493 bool update_cdclk, update_pipe_count;
2495 /* According to "Sequence After Frequency Change", set voltage to used level */
2496 voltage_level = new_cdclk_state->actual.voltage_level;
2498 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2499 update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2500 hweight8(old_cdclk_state->active_pipes);
2503 * According to "Sequence After Frequency Change",
2504 * set bits 25:16 to current CDCLK
2507 cdclk = new_cdclk_state->actual.cdclk;
2510 * According to "Sequence For Pipe Count Change",
2511 * if pipe count is decreasing, set bits 25:16 to current pipe count,
2512 * after the change(power well is disabled)
2513 * no action if it is increasing, after the change
2515 if (update_pipe_count)
2516 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2518 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2519 update_cdclk, update_pipe_count);
2523 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2524 * @state: intel atomic state
2526 * Program the hardware before updating the HW plane state based on the
2527 * new CDCLK state, if necessary.
2530 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2532 struct drm_i915_private *i915 = to_i915(state->base.dev);
2533 const struct intel_cdclk_state *old_cdclk_state =
2534 intel_atomic_get_old_cdclk_state(state);
2535 const struct intel_cdclk_state *new_cdclk_state =
2536 intel_atomic_get_new_cdclk_state(state);
2537 enum pipe pipe = new_cdclk_state->pipe;
2539 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2540 &new_cdclk_state->actual))
2544 intel_cdclk_pcode_pre_notify(state);
2546 if (pipe == INVALID_PIPE ||
2547 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
2548 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2550 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2555 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2556 * @state: intel atomic state
2558 * Program the hardware after updating the HW plane state based on the
2559 * new CDCLK state, if necessary.
2562 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2564 struct drm_i915_private *i915 = to_i915(state->base.dev);
2565 const struct intel_cdclk_state *old_cdclk_state =
2566 intel_atomic_get_old_cdclk_state(state);
2567 const struct intel_cdclk_state *new_cdclk_state =
2568 intel_atomic_get_new_cdclk_state(state);
2569 enum pipe pipe = new_cdclk_state->pipe;
2571 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2572 &new_cdclk_state->actual))
2576 intel_cdclk_pcode_post_notify(state);
2578 if (pipe != INVALID_PIPE &&
2579 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
2580 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2582 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2586 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2588 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2589 int pixel_rate = crtc_state->pixel_rate;
2591 if (DISPLAY_VER(dev_priv) >= 10)
2592 return DIV_ROUND_UP(pixel_rate, 2);
2593 else if (DISPLAY_VER(dev_priv) == 9 ||
2594 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2596 else if (IS_CHERRYVIEW(dev_priv))
2597 return DIV_ROUND_UP(pixel_rate * 100, 95);
2598 else if (crtc_state->double_wide)
2599 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2601 return DIV_ROUND_UP(pixel_rate * 100, 90);
2604 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2606 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2608 struct intel_plane *plane;
2611 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
2612 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2617 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
2619 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2620 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2621 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
2625 * When we decide to use only one VDSC engine, since
2626 * each VDSC operates with 1 ppc throughput, pixel clock
2627 * cannot be higher than the VDSC clock (cdclk)
2628 * If there 2 VDSC engines, then pixel clock can't be higher than
2629 * VDSC clock(cdclk) * 2 and so on.
2631 min_cdclk = max_t(int, min_cdclk,
2632 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
2634 if (crtc_state->bigjoiner_pipes) {
2635 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
2638 * According to Bigjoiner bw check:
2639 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
2641 * We have already computed compressed_bpp, so now compute the min CDCLK that
2642 * is required to support this compressed_bpp.
2644 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
2646 * Since PPC = 2 with bigjoiner
2647 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
2649 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
2651 (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
2652 pixel_clock) / (2 * bigjoiner_interface_bits);
2654 min_cdclk = max(min_cdclk, min_cdclk_bj);
2660 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2662 struct drm_i915_private *dev_priv =
2663 to_i915(crtc_state->uapi.crtc->dev);
2666 if (!crtc_state->hw.enable)
2669 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2671 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2672 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2673 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2675 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2676 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2677 * there may be audio corruption or screen corruption." This cdclk
2678 * restriction for GLK is 316.8 MHz.
2680 if (intel_crtc_has_dp_encoder(crtc_state) &&
2681 crtc_state->has_audio &&
2682 crtc_state->port_clock >= 540000 &&
2683 crtc_state->lane_count == 4) {
2684 if (DISPLAY_VER(dev_priv) == 10) {
2685 /* Display WA #1145: glk */
2686 min_cdclk = max(316800, min_cdclk);
2687 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
2688 /* Display WA #1144: skl,bxt */
2689 min_cdclk = max(432000, min_cdclk);
2694 * According to BSpec, "The CD clock frequency must be at least twice
2695 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2697 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
2698 min_cdclk = max(2 * 96000, min_cdclk);
2701 * "For DP audio configuration, cdclk frequency shall be set to
2702 * meet the following requirements:
2703 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
2704 * 270 | 320 or higher
2705 * 162 | 200 or higher"
2707 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2708 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2709 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2712 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2715 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2716 IS_VALLEYVIEW(dev_priv))
2717 min_cdclk = max(320000, min_cdclk);
2720 * On Geminilake once the CDCLK gets as low as 79200
2721 * picture gets unstable, despite that values are
2722 * correct for DSI PLL and DE PLL.
2724 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2725 IS_GEMINILAKE(dev_priv))
2726 min_cdclk = max(158400, min_cdclk);
2728 /* Account for additional needs from the planes */
2729 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2731 if (crtc_state->dsc.compression_enable)
2732 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2735 * HACK. Currently for TGL/DG2 platforms we calculate
2736 * min_cdclk initially based on pixel_rate divided
2737 * by 2, accounting for also plane requirements,
2738 * however in some cases the lowest possible CDCLK
2739 * doesn't work and causing the underruns.
2740 * Explicitly stating here that this seems to be currently
2741 * rather a Hack, than final solution.
2743 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
2745 * Clamp to max_cdclk_freq in case pixel rate is higher,
2746 * in order not to break an 8K, but still leave W/A at place.
2748 min_cdclk = max_t(int, min_cdclk,
2749 min_t(int, crtc_state->pixel_rate,
2750 dev_priv->display.cdclk.max_cdclk_freq));
2756 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2758 struct intel_atomic_state *state = cdclk_state->base.state;
2759 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2760 const struct intel_bw_state *bw_state;
2761 struct intel_crtc *crtc;
2762 struct intel_crtc_state *crtc_state;
2766 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2769 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2773 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2776 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2778 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2783 bw_state = intel_atomic_get_new_bw_state(state);
2785 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
2787 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2790 cdclk_state->bw_min_cdclk = min_cdclk;
2792 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2798 min_cdclk = max(cdclk_state->force_min_cdclk,
2799 cdclk_state->bw_min_cdclk);
2800 for_each_pipe(dev_priv, pipe)
2801 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2804 * Avoid glk_force_audio_cdclk() causing excessive screen
2805 * blinking when multiple pipes are active by making sure
2806 * CDCLK frequency is always high enough for audio. With a
2807 * single active pipe we can always change CDCLK frequency
2808 * by changing the cd2x divider (see glk_cdclk_table[]) and
2809 * thus a full modeset won't be needed then.
2811 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
2812 !is_power_of_2(cdclk_state->active_pipes))
2813 min_cdclk = max(2 * 96000, min_cdclk);
2815 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
2816 drm_dbg_kms(&dev_priv->drm,
2817 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2818 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
2826 * Account for port clock min voltage level requirements.
2827 * This only really does something on DISPLA_VER >= 11 but can be
2828 * called on earlier platforms as well.
2830 * Note that this functions assumes that 0 is
2831 * the lowest voltage value, and higher values
2832 * correspond to increasingly higher voltages.
2834 * Should that relationship no longer hold on
2835 * future platforms this code will need to be
2838 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2840 struct intel_atomic_state *state = cdclk_state->base.state;
2841 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2842 struct intel_crtc *crtc;
2843 struct intel_crtc_state *crtc_state;
2844 u8 min_voltage_level;
2848 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2851 if (crtc_state->hw.enable)
2852 min_voltage_level = crtc_state->min_voltage_level;
2854 min_voltage_level = 0;
2856 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2859 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2861 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2866 min_voltage_level = 0;
2867 for_each_pipe(dev_priv, pipe)
2868 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2871 return min_voltage_level;
2874 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2876 struct intel_atomic_state *state = cdclk_state->base.state;
2877 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2878 int min_cdclk, cdclk;
2880 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2884 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2886 cdclk_state->logical.cdclk = cdclk;
2887 cdclk_state->logical.voltage_level =
2888 vlv_calc_voltage_level(dev_priv, cdclk);
2890 if (!cdclk_state->active_pipes) {
2891 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2893 cdclk_state->actual.cdclk = cdclk;
2894 cdclk_state->actual.voltage_level =
2895 vlv_calc_voltage_level(dev_priv, cdclk);
2897 cdclk_state->actual = cdclk_state->logical;
2903 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2905 int min_cdclk, cdclk;
2907 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2911 cdclk = bdw_calc_cdclk(min_cdclk);
2913 cdclk_state->logical.cdclk = cdclk;
2914 cdclk_state->logical.voltage_level =
2915 bdw_calc_voltage_level(cdclk);
2917 if (!cdclk_state->active_pipes) {
2918 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2920 cdclk_state->actual.cdclk = cdclk;
2921 cdclk_state->actual.voltage_level =
2922 bdw_calc_voltage_level(cdclk);
2924 cdclk_state->actual = cdclk_state->logical;
2930 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2932 struct intel_atomic_state *state = cdclk_state->base.state;
2933 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2934 struct intel_crtc *crtc;
2935 struct intel_crtc_state *crtc_state;
2938 vco = cdclk_state->logical.vco;
2940 vco = dev_priv->skl_preferred_vco_freq;
2942 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2943 if (!crtc_state->hw.enable)
2946 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2950 * DPLL0 VCO may need to be adjusted to get the correct
2951 * clock for eDP. This will affect cdclk as well.
2953 switch (crtc_state->port_clock / 2) {
2967 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2969 int min_cdclk, cdclk, vco;
2971 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2975 vco = skl_dpll0_vco(cdclk_state);
2977 cdclk = skl_calc_cdclk(min_cdclk, vco);
2979 cdclk_state->logical.vco = vco;
2980 cdclk_state->logical.cdclk = cdclk;
2981 cdclk_state->logical.voltage_level =
2982 skl_calc_voltage_level(cdclk);
2984 if (!cdclk_state->active_pipes) {
2985 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2987 cdclk_state->actual.vco = vco;
2988 cdclk_state->actual.cdclk = cdclk;
2989 cdclk_state->actual.voltage_level =
2990 skl_calc_voltage_level(cdclk);
2992 cdclk_state->actual = cdclk_state->logical;
2998 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3000 struct intel_atomic_state *state = cdclk_state->base.state;
3001 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3002 int min_cdclk, min_voltage_level, cdclk, vco;
3004 min_cdclk = intel_compute_min_cdclk(cdclk_state);
3008 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
3009 if (min_voltage_level < 0)
3010 return min_voltage_level;
3012 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
3013 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
3015 cdclk_state->logical.vco = vco;
3016 cdclk_state->logical.cdclk = cdclk;
3017 cdclk_state->logical.voltage_level =
3018 max_t(int, min_voltage_level,
3019 intel_cdclk_calc_voltage_level(dev_priv, cdclk));
3021 if (!cdclk_state->active_pipes) {
3022 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
3023 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
3025 cdclk_state->actual.vco = vco;
3026 cdclk_state->actual.cdclk = cdclk;
3027 cdclk_state->actual.voltage_level =
3028 intel_cdclk_calc_voltage_level(dev_priv, cdclk);
3030 cdclk_state->actual = cdclk_state->logical;
3036 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3041 * We can't change the cdclk frequency, but we still want to
3042 * check that the required minimum frequency doesn't exceed
3043 * the actual cdclk frequency.
3045 min_cdclk = intel_compute_min_cdclk(cdclk_state);
3052 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3054 struct intel_cdclk_state *cdclk_state;
3056 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3060 cdclk_state->pipe = INVALID_PIPE;
3062 return &cdclk_state->base;
3065 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3066 struct intel_global_state *state)
3071 static const struct intel_global_state_funcs intel_cdclk_funcs = {
3072 .atomic_duplicate_state = intel_cdclk_duplicate_state,
3073 .atomic_destroy_state = intel_cdclk_destroy_state,
3076 struct intel_cdclk_state *
3077 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3079 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3080 struct intel_global_state *cdclk_state;
3082 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
3083 if (IS_ERR(cdclk_state))
3084 return ERR_CAST(cdclk_state);
3086 return to_intel_cdclk_state(cdclk_state);
3089 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
3090 bool *need_cdclk_calc)
3092 const struct intel_cdclk_state *old_cdclk_state;
3093 const struct intel_cdclk_state *new_cdclk_state;
3094 struct intel_plane_state __maybe_unused *plane_state;
3095 struct intel_plane *plane;
3100 * active_planes bitmask has been updated, and potentially affected
3101 * planes are part of the state. We can now compute the minimum cdclk
3104 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3105 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
3110 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
3114 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3115 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3117 if (new_cdclk_state &&
3118 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3119 *need_cdclk_calc = true;
3124 int intel_cdclk_init(struct drm_i915_private *dev_priv)
3126 struct intel_cdclk_state *cdclk_state;
3128 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3132 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
3133 &cdclk_state->base, &intel_cdclk_funcs);
3138 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
3139 const struct intel_cdclk_state *old_cdclk_state,
3140 const struct intel_cdclk_state *new_cdclk_state)
3142 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3143 hweight8(new_cdclk_state->active_pipes);
3144 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3145 &new_cdclk_state->actual);
3147 * We need to poke hw for gen >= 12, because we notify PCode if
3148 * pipe power well count changes.
3150 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed);
3153 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3155 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3156 const struct intel_cdclk_state *old_cdclk_state;
3157 struct intel_cdclk_state *new_cdclk_state;
3158 enum pipe pipe = INVALID_PIPE;
3161 new_cdclk_state = intel_atomic_get_cdclk_state(state);
3162 if (IS_ERR(new_cdclk_state))
3163 return PTR_ERR(new_cdclk_state);
3165 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3167 new_cdclk_state->active_pipes =
3168 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3170 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);
3174 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) {
3176 * Also serialize commits across all crtcs
3177 * if the actual hw needs to be poked.
3179 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3182 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3183 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3184 intel_cdclk_changed(&old_cdclk_state->logical,
3185 &new_cdclk_state->logical)) {
3186 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3193 if (is_power_of_2(new_cdclk_state->active_pipes) &&
3194 intel_cdclk_can_cd2x_update(dev_priv,
3195 &old_cdclk_state->actual,
3196 &new_cdclk_state->actual)) {
3197 struct intel_crtc *crtc;
3198 struct intel_crtc_state *crtc_state;
3200 pipe = ilog2(new_cdclk_state->active_pipes);
3201 crtc = intel_crtc_for_pipe(dev_priv, pipe);
3203 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3204 if (IS_ERR(crtc_state))
3205 return PTR_ERR(crtc_state);
3207 if (intel_crtc_needs_modeset(crtc_state))
3208 pipe = INVALID_PIPE;
3211 if (intel_cdclk_can_crawl_and_squash(dev_priv,
3212 &old_cdclk_state->actual,
3213 &new_cdclk_state->actual)) {
3214 drm_dbg_kms(&dev_priv->drm,
3215 "Can change cdclk via crawling and squashing\n");
3216 } else if (intel_cdclk_can_squash(dev_priv,
3217 &old_cdclk_state->actual,
3218 &new_cdclk_state->actual)) {
3219 drm_dbg_kms(&dev_priv->drm,
3220 "Can change cdclk via squashing\n");
3221 } else if (intel_cdclk_can_crawl(dev_priv,
3222 &old_cdclk_state->actual,
3223 &new_cdclk_state->actual)) {
3224 drm_dbg_kms(&dev_priv->drm,
3225 "Can change cdclk via crawling\n");
3226 } else if (pipe != INVALID_PIPE) {
3227 new_cdclk_state->pipe = pipe;
3229 drm_dbg_kms(&dev_priv->drm,
3230 "Can change cdclk cd2x divider with pipe %c active\n",
3232 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
3233 &new_cdclk_state->actual)) {
3234 /* All pipes must be switched off while we change the cdclk. */
3235 ret = intel_modeset_all_pipes_late(state, "CDCLK change");
3239 drm_dbg_kms(&dev_priv->drm,
3240 "Modeset required for cdclk change\n");
3243 drm_dbg_kms(&dev_priv->drm,
3244 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3245 new_cdclk_state->logical.cdclk,
3246 new_cdclk_state->actual.cdclk);
3247 drm_dbg_kms(&dev_priv->drm,
3248 "New voltage level calculated to be logical %u, actual %u\n",
3249 new_cdclk_state->logical.voltage_level,
3250 new_cdclk_state->actual.voltage_level);
3255 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
3257 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
3259 if (DISPLAY_VER(dev_priv) >= 10)
3260 return 2 * max_cdclk_freq;
3261 else if (DISPLAY_VER(dev_priv) == 9 ||
3262 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3263 return max_cdclk_freq;
3264 else if (IS_CHERRYVIEW(dev_priv))
3265 return max_cdclk_freq*95/100;
3266 else if (DISPLAY_VER(dev_priv) < 4)
3267 return 2*max_cdclk_freq*90/100;
3269 return max_cdclk_freq*90/100;
3273 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3274 * @dev_priv: i915 device
3276 * Determine the maximum CDCLK frequency the platform supports, and also
3277 * derive the maximum dot clock frequency the maximum CDCLK frequency
3280 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
3282 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3283 if (dev_priv->display.cdclk.hw.ref == 24000)
3284 dev_priv->display.cdclk.max_cdclk_freq = 552000;
3286 dev_priv->display.cdclk.max_cdclk_freq = 556800;
3287 } else if (DISPLAY_VER(dev_priv) >= 11) {
3288 if (dev_priv->display.cdclk.hw.ref == 24000)
3289 dev_priv->display.cdclk.max_cdclk_freq = 648000;
3291 dev_priv->display.cdclk.max_cdclk_freq = 652800;
3292 } else if (IS_GEMINILAKE(dev_priv)) {
3293 dev_priv->display.cdclk.max_cdclk_freq = 316800;
3294 } else if (IS_BROXTON(dev_priv)) {
3295 dev_priv->display.cdclk.max_cdclk_freq = 624000;
3296 } else if (DISPLAY_VER(dev_priv) == 9) {
3297 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3300 vco = dev_priv->skl_preferred_vco_freq;
3301 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
3304 * Use the lower (vco 8640) cdclk values as a
3305 * first guess. skl_calc_cdclk() will correct it
3306 * if the preferred vco is 8100 instead.
3308 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3310 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3312 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3317 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3318 } else if (IS_BROADWELL(dev_priv)) {
3320 * FIXME with extra cooling we can allow
3321 * 540 MHz for ULX and 675 Mhz for ULT.
3322 * How can we know if extra cooling is
3323 * available? PCI ID, VTB, something else?
3325 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3326 dev_priv->display.cdclk.max_cdclk_freq = 450000;
3327 else if (IS_BROADWELL_ULX(dev_priv))
3328 dev_priv->display.cdclk.max_cdclk_freq = 450000;
3329 else if (IS_BROADWELL_ULT(dev_priv))
3330 dev_priv->display.cdclk.max_cdclk_freq = 540000;
3332 dev_priv->display.cdclk.max_cdclk_freq = 675000;
3333 } else if (IS_CHERRYVIEW(dev_priv)) {
3334 dev_priv->display.cdclk.max_cdclk_freq = 320000;
3335 } else if (IS_VALLEYVIEW(dev_priv)) {
3336 dev_priv->display.cdclk.max_cdclk_freq = 400000;
3338 /* otherwise assume cdclk is fixed */
3339 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
3342 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
3344 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
3345 dev_priv->display.cdclk.max_cdclk_freq);
3347 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
3348 dev_priv->max_dotclk_freq);
3352 * intel_update_cdclk - Determine the current CDCLK frequency
3353 * @dev_priv: i915 device
3355 * Determine the current CDCLK frequency.
3357 void intel_update_cdclk(struct drm_i915_private *dev_priv)
3359 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
3362 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3363 * Programmng [sic] note: bit[9:2] should be programmed to the number
3364 * of cdclk that generates 4MHz reference clock freq which is used to
3365 * generate GMBus clock. This will vary with the cdclk freq.
3367 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3368 intel_de_write(dev_priv, GMBUSFREQ_VLV,
3369 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
3372 static int dg1_rawclk(struct drm_i915_private *dev_priv)
3375 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
3376 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3378 intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
3379 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3384 static int cnp_rawclk(struct drm_i915_private *dev_priv)
3387 int divider, fraction;
3389 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3399 rawclk = CNP_RAWCLK_DIV(divider / 1000);
3403 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3405 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3406 rawclk |= ICP_RAWCLK_NUM(numerator);
3409 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
3410 return divider + fraction;
3413 static int pch_rawclk(struct drm_i915_private *dev_priv)
3415 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3418 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
3420 /* RAWCLK_FREQ_VLV register updated from power well code */
3421 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
3422 CCK_DISPLAY_REF_CLOCK_CONTROL);
3425 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
3430 * hrawclock is 1/4 the FSB frequency
3432 * Note that this only reads the state of the FSB
3433 * straps, not the actual FSB frequency. Some BIOSen
3434 * let you configure each independently. Ideally we'd
3435 * read out the actual FSB frequency but sadly we
3436 * don't know which registers have that information,
3437 * and all the relevant docs have gone to bit heaven :(
3439 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
3441 if (IS_MOBILE(dev_priv)) {
3443 case CLKCFG_FSB_400:
3445 case CLKCFG_FSB_533:
3447 case CLKCFG_FSB_667:
3449 case CLKCFG_FSB_800:
3451 case CLKCFG_FSB_1067:
3453 case CLKCFG_FSB_1333:
3456 MISSING_CASE(clkcfg);
3461 case CLKCFG_FSB_400_ALT:
3463 case CLKCFG_FSB_533:
3465 case CLKCFG_FSB_667:
3467 case CLKCFG_FSB_800:
3469 case CLKCFG_FSB_1067_ALT:
3471 case CLKCFG_FSB_1333_ALT:
3473 case CLKCFG_FSB_1600_ALT:
3482 * intel_read_rawclk - Determine the current RAWCLK frequency
3483 * @dev_priv: i915 device
3485 * Determine the current RAWCLK frequency. RAWCLK is a fixed
3486 * frequency clock so this needs to done only once.
3488 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
3492 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
3494 * MTL always uses a 38.4 MHz rawclk. The bspec tells us
3495 * "RAWCLK_FREQ defaults to the values for 38.4 and does
3496 * not need to be programmed."
3499 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3500 freq = dg1_rawclk(dev_priv);
3501 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3502 freq = cnp_rawclk(dev_priv);
3503 else if (HAS_PCH_SPLIT(dev_priv))
3504 freq = pch_rawclk(dev_priv);
3505 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3506 freq = vlv_hrawclk(dev_priv);
3507 else if (DISPLAY_VER(dev_priv) >= 3)
3508 freq = i9xx_hrawclk(dev_priv);
3510 /* no rawclk on other platforms, or no need to know it */
3516 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3518 struct drm_i915_private *i915 = m->private;
3520 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
3521 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
3522 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
3527 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3529 void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
3531 struct drm_minor *minor = i915->drm.primary;
3533 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3534 i915, &i915_cdclk_info_fops);
3537 static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
3538 .get_cdclk = bxt_get_cdclk,
3539 .set_cdclk = bxt_set_cdclk,
3540 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3541 .calc_voltage_level = rplu_calc_voltage_level,
3544 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3545 .get_cdclk = bxt_get_cdclk,
3546 .set_cdclk = bxt_set_cdclk,
3547 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3548 .calc_voltage_level = rplu_calc_voltage_level,
3551 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3552 .get_cdclk = bxt_get_cdclk,
3553 .set_cdclk = bxt_set_cdclk,
3554 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3555 .calc_voltage_level = tgl_calc_voltage_level,
3558 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3559 .get_cdclk = bxt_get_cdclk,
3560 .set_cdclk = bxt_set_cdclk,
3561 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3562 .calc_voltage_level = ehl_calc_voltage_level,
3565 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3566 .get_cdclk = bxt_get_cdclk,
3567 .set_cdclk = bxt_set_cdclk,
3568 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3569 .calc_voltage_level = icl_calc_voltage_level,
3572 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3573 .get_cdclk = bxt_get_cdclk,
3574 .set_cdclk = bxt_set_cdclk,
3575 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3576 .calc_voltage_level = bxt_calc_voltage_level,
3579 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3580 .get_cdclk = skl_get_cdclk,
3581 .set_cdclk = skl_set_cdclk,
3582 .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3585 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3586 .get_cdclk = bdw_get_cdclk,
3587 .set_cdclk = bdw_set_cdclk,
3588 .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3591 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3592 .get_cdclk = vlv_get_cdclk,
3593 .set_cdclk = chv_set_cdclk,
3594 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3597 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3598 .get_cdclk = vlv_get_cdclk,
3599 .set_cdclk = vlv_set_cdclk,
3600 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3603 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3604 .get_cdclk = hsw_get_cdclk,
3605 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3608 /* SNB, IVB, 965G, 945G */
3609 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3610 .get_cdclk = fixed_400mhz_get_cdclk,
3611 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3614 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3615 .get_cdclk = fixed_450mhz_get_cdclk,
3616 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3619 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3620 .get_cdclk = gm45_get_cdclk,
3621 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3626 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3627 .get_cdclk = i965gm_get_cdclk,
3628 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3631 /* i965G uses fixed 400 */
3633 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3634 .get_cdclk = pnv_get_cdclk,
3635 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3638 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3639 .get_cdclk = g33_get_cdclk,
3640 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3643 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3644 .get_cdclk = i945gm_get_cdclk,
3645 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3648 /* i945G uses fixed 400 */
3650 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3651 .get_cdclk = i915gm_get_cdclk,
3652 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3655 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3656 .get_cdclk = fixed_333mhz_get_cdclk,
3657 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3660 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3661 .get_cdclk = fixed_266mhz_get_cdclk,
3662 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3665 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3666 .get_cdclk = i85x_get_cdclk,
3667 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3670 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3671 .get_cdclk = fixed_200mhz_get_cdclk,
3672 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3675 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3676 .get_cdclk = fixed_133mhz_get_cdclk,
3677 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3681 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3682 * @dev_priv: i915 device
3684 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
3686 if (DISPLAY_VER(dev_priv) >= 20) {
3687 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3688 dev_priv->display.cdclk.table = lnl_cdclk_table;
3689 } else if (DISPLAY_VER(dev_priv) >= 14) {
3690 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3691 dev_priv->display.cdclk.table = mtl_cdclk_table;
3692 } else if (IS_DG2(dev_priv)) {
3693 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3694 dev_priv->display.cdclk.table = dg2_cdclk_table;
3695 } else if (IS_ALDERLAKE_P(dev_priv)) {
3696 /* Wa_22011320316:adl-p[a0] */
3697 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
3698 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
3699 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3700 } else if (IS_RAPTORLAKE_U(dev_priv)) {
3701 dev_priv->display.cdclk.table = rplu_cdclk_table;
3702 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
3704 dev_priv->display.cdclk.table = adlp_cdclk_table;
3705 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3707 } else if (IS_ROCKETLAKE(dev_priv)) {
3708 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3709 dev_priv->display.cdclk.table = rkl_cdclk_table;
3710 } else if (DISPLAY_VER(dev_priv) >= 12) {
3711 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3712 dev_priv->display.cdclk.table = icl_cdclk_table;
3713 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3714 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
3715 dev_priv->display.cdclk.table = icl_cdclk_table;
3716 } else if (DISPLAY_VER(dev_priv) >= 11) {
3717 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
3718 dev_priv->display.cdclk.table = icl_cdclk_table;
3719 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
3720 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
3721 if (IS_GEMINILAKE(dev_priv))
3722 dev_priv->display.cdclk.table = glk_cdclk_table;
3724 dev_priv->display.cdclk.table = bxt_cdclk_table;
3725 } else if (DISPLAY_VER(dev_priv) == 9) {
3726 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
3727 } else if (IS_BROADWELL(dev_priv)) {
3728 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
3729 } else if (IS_HASWELL(dev_priv)) {
3730 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
3731 } else if (IS_CHERRYVIEW(dev_priv)) {
3732 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
3733 } else if (IS_VALLEYVIEW(dev_priv)) {
3734 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
3735 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
3736 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3737 } else if (IS_IRONLAKE(dev_priv)) {
3738 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
3739 } else if (IS_GM45(dev_priv)) {
3740 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
3741 } else if (IS_G45(dev_priv)) {
3742 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3743 } else if (IS_I965GM(dev_priv)) {
3744 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
3745 } else if (IS_I965G(dev_priv)) {
3746 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3747 } else if (IS_PINEVIEW(dev_priv)) {
3748 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
3749 } else if (IS_G33(dev_priv)) {
3750 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3751 } else if (IS_I945GM(dev_priv)) {
3752 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
3753 } else if (IS_I945G(dev_priv)) {
3754 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3755 } else if (IS_I915GM(dev_priv)) {
3756 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
3757 } else if (IS_I915G(dev_priv)) {
3758 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
3759 } else if (IS_I865G(dev_priv)) {
3760 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
3761 } else if (IS_I85X(dev_priv)) {
3762 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
3763 } else if (IS_I845G(dev_priv)) {
3764 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
3765 } else if (IS_I830(dev_priv)) {
3766 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3769 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
3770 "Unknown platform. Assuming i830\n"))
3771 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;