drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "smu_types.h"
  25 #define SWSMU_CODE_LAYER_L2
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_v14_0.h"
  30 #include "smu14_driver_if_v14_0_0.h"
  31 #include "smu_v14_0_0_ppt.h"
  32 #include "smu_v14_0_0_ppsmc.h"
  33 #include "smu_v14_0_0_pmfw.h"
  34 #include "smu_cmn.h"
  35
  36 /*
  37  * DO NOT use these for err/warn/info/debug messages.
  38  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  39  * They are more MGPU friendly.
  40  */
  41 #undef pr_err
  42 #undef pr_warn
  43 #undef pr_info
  44 #undef pr_debug
  45
  46 #define mmMP1_SMN_C2PMSG_66                     0x0282
  47 #define mmMP1_SMN_C2PMSG_66_BASE_IDX            0
  48
  49 #define mmMP1_SMN_C2PMSG_82                     0x0292
  50 #define mmMP1_SMN_C2PMSG_82_BASE_IDX            0
  51
  52 #define mmMP1_SMN_C2PMSG_90                     0x029a
  53 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                0
  54
  55 #define FEATURE_MASK(feature) (1ULL << feature)
  56 #define SMC_DPM_FEATURE ( \
  57         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
  58         FEATURE_MASK(FEATURE_VCN_DPM_BIT)        | \
  59         FEATURE_MASK(FEATURE_FCLK_DPM_BIT)       | \
  60         FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)     | \
  61         FEATURE_MASK(FEATURE_LCLK_DPM_BIT)       | \
  62         FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)    | \
  63         FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
  64         FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
  65         FEATURE_MASK(FEATURE_IPU_DPM_BIT)       | \
  66         FEATURE_MASK(FEATURE_GFX_DPM_BIT)       | \
  67         FEATURE_MASK(FEATURE_VPE_DPM_BIT))
  68
  69 static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] = {
  70         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                          1),
  71         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetPmfwVersion,                       1),
  72         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  73         MSG_MAP(PowerDownVcn0,                  PPSMC_MSG_PowerDownVcn0,                        1),
  74         MSG_MAP(PowerUpVcn0,                    PPSMC_MSG_PowerUpVcn0,                          1),
  75         MSG_MAP(SetHardMinVcn0,                 PPSMC_MSG_SetHardMinVcn0,                       1),
  76         MSG_MAP(PowerDownVcn1,                  PPSMC_MSG_PowerDownVcn1,                        1),
  77         MSG_MAP(PowerUpVcn1,                    PPSMC_MSG_PowerUpVcn1,                          1),
  78         MSG_MAP(SetHardMinVcn1,                 PPSMC_MSG_SetHardMinVcn1,                       1),
  79         MSG_MAP(SetSoftMinGfxclk,               PPSMC_MSG_SetSoftMinGfxclk,                     1),
  80         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
  81         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
  82         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
  83         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
  84         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        1),
  85         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         1),
  86         MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,        1),
  87         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       1),
  88         MSG_MAP(SetSoftMinFclk,                 PPSMC_MSG_SetSoftMinFclk,                       1),
  89         MSG_MAP(SetSoftMinVcn0,                 PPSMC_MSG_SetSoftMinVcn0,                       1),
  90         MSG_MAP(SetSoftMinVcn1,                 PPSMC_MSG_SetSoftMinVcn1,                       1),
  91         MSG_MAP(EnableGfxImu,                   PPSMC_MSG_EnableGfxImu,                         1),
  92         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                          1),
  93         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,                       1),
  94         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,                     1),
  95         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,                     1),
  96         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       1),
  97         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         1),
  98         MSG_MAP(SetSoftMaxVcn0,                 PPSMC_MSG_SetSoftMaxVcn0,                       1),
  99         MSG_MAP(SetSoftMaxVcn1,                 PPSMC_MSG_SetSoftMaxVcn1,                       1),
 100         MSG_MAP(PowerDownJpeg0,                 PPSMC_MSG_PowerDownJpeg0,                       1),
 101         MSG_MAP(PowerUpJpeg0,                   PPSMC_MSG_PowerUpJpeg0,                         1),
 102         MSG_MAP(PowerDownJpeg1,                 PPSMC_MSG_PowerDownJpeg1,                       1),
 103         MSG_MAP(PowerUpJpeg1,                   PPSMC_MSG_PowerUpJpeg1,                         1),
 104         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         1),
 105         MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,       1),
 106         MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,           1),
 107         MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,                     1),
 108         MSG_MAP(SetHardMinIspiclkByFreq,        PPSMC_MSG_SetHardMinIspiclkByFreq,      1),
 109         MSG_MAP(SetHardMinIspxclkByFreq,        PPSMC_MSG_SetHardMinIspxclkByFreq,      1),
 110         MSG_MAP(PowerUpVpe,                     PPSMC_MSG_PowerUpVpe,                           1),
 111         MSG_MAP(PowerDownVpe,                   PPSMC_MSG_PowerDownVpe,                         1),
 112         MSG_MAP(PowerUpUmsch,                   PPSMC_MSG_PowerUpUmsch,                         1),
 113         MSG_MAP(PowerDownUmsch,                 PPSMC_MSG_PowerDownUmsch,                       1),
 114         MSG_MAP(SetSoftMaxVpe,                  PPSMC_MSG_SetSoftMaxVpe,                        1),
 115         MSG_MAP(SetSoftMinVpe,                  PPSMC_MSG_SetSoftMinVpe,                        1),
 116 };
 117
 118 static struct cmn2asic_mapping smu_v14_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
 119         FEA_MAP(CCLK_DPM),
 120         FEA_MAP(FAN_CONTROLLER),
 121         FEA_MAP(PPT),
 122         FEA_MAP(TDC),
 123         FEA_MAP(THERMAL),
 124         FEA_MAP(VCN_DPM),
 125         FEA_MAP_REVERSE(FCLK),
 126         FEA_MAP_REVERSE(SOCCLK),
 127         FEA_MAP(LCLK_DPM),
 128         FEA_MAP(SHUBCLK_DPM),
 129         FEA_MAP(DCFCLK_DPM),
 130         FEA_MAP_HALF_REVERSE(GFX),
 131         FEA_MAP(DS_GFXCLK),
 132         FEA_MAP(DS_SOCCLK),
 133         FEA_MAP(DS_LCLK),
 134         FEA_MAP(LOW_POWER_DCNCLKS),
 135         FEA_MAP(DS_FCLK),
 136         FEA_MAP(DS_MP1CLK),
 137         FEA_MAP(PSI),
 138         FEA_MAP(PROCHOT),
 139         FEA_MAP(CPUOFF),
 140         FEA_MAP(STAPM),
 141         FEA_MAP(S0I3),
 142         FEA_MAP(PERF_LIMIT),
 143         FEA_MAP(CORE_DLDO),
 144         FEA_MAP(DS_VCN),
 145         FEA_MAP(CPPC),
 146         FEA_MAP(DF_CSTATES),
 147         FEA_MAP(ATHUB_PG),
 148 };
 149
 150 static struct cmn2asic_mapping smu_v14_0_0_table_map[SMU_TABLE_COUNT] = {
 151         TAB_MAP_VALID(WATERMARKS),
 152         TAB_MAP_VALID(SMU_METRICS),
 153         TAB_MAP_VALID(CUSTOM_DPM),
 154         TAB_MAP_VALID(DPMCLOCKS),
 155 };
 156
 157 static int smu_v14_0_0_init_smc_tables(struct smu_context *smu)
 158 {
 159         struct smu_table_context *smu_table = &smu->smu_table;
 160         struct smu_table *tables = smu_table->tables;
 161
 162         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 163                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 164         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, max(sizeof(DpmClocks_t), sizeof(DpmClocks_t_v14_0_1)),
 165                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 166         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 167                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 168
 169         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 170         if (!smu_table->metrics_table)
 171                 goto err0_out;
 172         smu_table->metrics_time = 0;
 173
 174         smu_table->clocks_table = kzalloc(max(sizeof(DpmClocks_t), sizeof(DpmClocks_t_v14_0_1)), GFP_KERNEL);
 175         if (!smu_table->clocks_table)
 176                 goto err1_out;
 177
 178         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 179         if (!smu_table->watermarks_table)
 180                 goto err2_out;
 181
 182         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v3_0);
 183         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 184         if (!smu_table->gpu_metrics_table)
 185                 goto err3_out;
 186
 187         return 0;
 188
 189 err3_out:
 190         kfree(smu_table->watermarks_table);
 191 err2_out:
 192         kfree(smu_table->clocks_table);
 193 err1_out:
 194         kfree(smu_table->metrics_table);
 195 err0_out:
 196         return -ENOMEM;
 197 }
 198
 199 static int smu_v14_0_0_fini_smc_tables(struct smu_context *smu)
 200 {
 201         struct smu_table_context *smu_table = &smu->smu_table;
 202
 203         kfree(smu_table->clocks_table);
 204         smu_table->clocks_table = NULL;
 205
 206         kfree(smu_table->metrics_table);
 207         smu_table->metrics_table = NULL;
 208
 209         kfree(smu_table->watermarks_table);
 210         smu_table->watermarks_table = NULL;
 211
 212         kfree(smu_table->gpu_metrics_table);
 213         smu_table->gpu_metrics_table = NULL;
 214
 215         return 0;
 216 }
 217
 218 static int smu_v14_0_0_system_features_control(struct smu_context *smu, bool en)
 219 {
 220         struct amdgpu_device *adev = smu->adev;
 221         int ret = 0;
 222
 223         if (!en && !adev->in_s0ix)
 224                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
 225
 226         return ret;
 227 }
 228
 229 static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
 230                                             MetricsMember_t member,
 231                                             uint32_t *value)
 232 {
 233         struct smu_table_context *smu_table = &smu->smu_table;
 234
 235         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 236         int ret = 0;
 237
 238         ret = smu_cmn_get_metrics_table(smu, NULL, false);
 239         if (ret)
 240                 return ret;
 241
 242         switch (member) {
 243         case METRICS_AVERAGE_GFXCLK:
 244                 *value = metrics->GfxclkFrequency;
 245                 break;
 246         case METRICS_AVERAGE_SOCCLK:
 247                 *value = metrics->SocclkFrequency;
 248                 break;
 249         case METRICS_AVERAGE_VCLK:
 250                 *value = metrics->VclkFrequency;
 251                 break;
 252         case METRICS_AVERAGE_DCLK:
 253                 *value = 0;
 254                 break;
 255         case METRICS_AVERAGE_UCLK:
 256                 *value = metrics->MemclkFrequency;
 257                 break;
 258         case METRICS_AVERAGE_FCLK:
 259                 *value = metrics->FclkFrequency;
 260                 break;
 261         case METRICS_AVERAGE_VPECLK:
 262                 *value = metrics->VpeclkFrequency;
 263                 break;
 264         case METRICS_AVERAGE_IPUCLK:
 265                 *value = metrics->IpuclkFrequency;
 266                 break;
 267         case METRICS_AVERAGE_MPIPUCLK:
 268                 *value = metrics->MpipuclkFrequency;
 269                 break;
 270         case METRICS_AVERAGE_GFXACTIVITY:
 271                 if ((smu->smc_fw_version > 0x5d4600))
 272                         *value = metrics->GfxActivity;
 273                 else
 274                         *value = metrics->GfxActivity / 100;
 275                 break;
 276         case METRICS_AVERAGE_VCNACTIVITY:
 277                 *value = metrics->VcnActivity / 100;
 278                 break;
 279         case METRICS_AVERAGE_SOCKETPOWER:
 280         case METRICS_CURR_SOCKETPOWER:
 281                 *value = (metrics->SocketPower / 1000 << 8) +
 282                 (metrics->SocketPower % 1000 / 10);
 283                 break;
 284         case METRICS_TEMPERATURE_EDGE:
 285                 *value = metrics->GfxTemperature / 100 *
 286                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 287                 break;
 288         case METRICS_TEMPERATURE_HOTSPOT:
 289                 *value = metrics->SocTemperature / 100 *
 290                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 291                 break;
 292         case METRICS_THROTTLER_RESIDENCY_PROCHOT:
 293                 *value = metrics->ThrottleResidency_PROCHOT;
 294                 break;
 295         case METRICS_THROTTLER_RESIDENCY_SPL:
 296                 *value = metrics->ThrottleResidency_SPL;
 297                 break;
 298         case METRICS_THROTTLER_RESIDENCY_FPPT:
 299                 *value = metrics->ThrottleResidency_FPPT;
 300                 break;
 301         case METRICS_THROTTLER_RESIDENCY_SPPT:
 302                 *value = metrics->ThrottleResidency_SPPT;
 303                 break;
 304         case METRICS_THROTTLER_RESIDENCY_THM_CORE:
 305                 *value = metrics->ThrottleResidency_THM_CORE;
 306                 break;
 307         case METRICS_THROTTLER_RESIDENCY_THM_GFX:
 308                 *value = metrics->ThrottleResidency_THM_GFX;
 309                 break;
 310         case METRICS_THROTTLER_RESIDENCY_THM_SOC:
 311                 *value = metrics->ThrottleResidency_THM_SOC;
 312                 break;
 313         case METRICS_VOLTAGE_VDDGFX:
 314                 *value = 0;
 315                 break;
 316         case METRICS_VOLTAGE_VDDSOC:
 317                 *value = 0;
 318                 break;
 319         case METRICS_SS_APU_SHARE:
 320                 /* return the percentage of APU power with respect to APU's power limit.
 321                  * percentage is reported, this isn't boost value. Smartshift power
 322                  * boost/shift is only when the percentage is more than 100.
 323                  */
 324                 if (metrics->StapmOpnLimit > 0)
 325                         *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
 326                 else
 327                         *value = 0;
 328                 break;
 329         case METRICS_SS_DGPU_SHARE:
 330                 /* return the percentage of dGPU power with respect to dGPU's power limit.
 331                  * percentage is reported, this isn't boost value. Smartshift power
 332                  * boost/shift is only when the percentage is more than 100.
 333                  */
 334                 if ((metrics->dGpuPower > 0) &&
 335                     (metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
 336                         *value = (metrics->dGpuPower * 100) /
 337                                  (metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
 338                 else
 339                         *value = 0;
 340                 break;
 341         default:
 342                 *value = UINT_MAX;
 343                 break;
 344         }
 345
 346         return ret;
 347 }
 348
 349 static int smu_v14_0_0_read_sensor(struct smu_context *smu,
 350                                    enum amd_pp_sensors sensor,
 351                                    void *data, uint32_t *size)
 352 {
 353         int ret = 0;
 354
 355         if (!data || !size)
 356                 return -EINVAL;
 357
 358         switch (sensor) {
 359         case AMDGPU_PP_SENSOR_GPU_LOAD:
 360                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 361                                                        METRICS_AVERAGE_GFXACTIVITY,
 362                                                        (uint32_t *)data);
 363                 *size = 4;
 364                 break;
 365         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
 366                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 367                                                        METRICS_AVERAGE_SOCKETPOWER,
 368                                                        (uint32_t *)data);
 369                 *size = 4;
 370                 break;
 371         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
 372                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 373                                                        METRICS_CURR_SOCKETPOWER,
 374                                                        (uint32_t *)data);
 375                 *size = 4;
 376                 break;
 377         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 378                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 379                                                        METRICS_TEMPERATURE_EDGE,
 380                                                        (uint32_t *)data);
 381                 *size = 4;
 382                 break;
 383         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 384                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 385                                                        METRICS_TEMPERATURE_HOTSPOT,
 386                                                        (uint32_t *)data);
 387                 *size = 4;
 388                 break;
 389         case AMDGPU_PP_SENSOR_GFX_MCLK:
 390                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 391                                                        METRICS_AVERAGE_UCLK,
 392                                                        (uint32_t *)data);
 393                 *(uint32_t *)data *= 100;
 394                 *size = 4;
 395                 break;
 396         case AMDGPU_PP_SENSOR_GFX_SCLK:
 397                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 398                                                        METRICS_AVERAGE_GFXCLK,
 399                                                        (uint32_t *)data);
 400                 *(uint32_t *)data *= 100;
 401                 *size = 4;
 402                 break;
 403         case AMDGPU_PP_SENSOR_VDDGFX:
 404                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 405                                                        METRICS_VOLTAGE_VDDGFX,
 406                                                        (uint32_t *)data);
 407                 *size = 4;
 408                 break;
 409         case AMDGPU_PP_SENSOR_VDDNB:
 410                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 411                                                        METRICS_VOLTAGE_VDDSOC,
 412                                                        (uint32_t *)data);
 413                 *size = 4;
 414                 break;
 415         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
 416                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 417                                                        METRICS_SS_APU_SHARE,
 418                                                        (uint32_t *)data);
 419                 *size = 4;
 420                 break;
 421         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
 422                 ret = smu_v14_0_0_get_smu_metrics_data(smu,
 423                                                        METRICS_SS_DGPU_SHARE,
 424                                                        (uint32_t *)data);
 425                 *size = 4;
 426                 break;
 427         default:
 428                 ret = -EOPNOTSUPP;
 429                 break;
 430         }
 431
 432         return ret;
 433 }
 434
 435 static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
 436 {
 437         int ret = 0;
 438         uint64_t feature_enabled;
 439
 440         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 441
 442         if (ret)
 443                 return false;
 444
 445         return !!(feature_enabled & SMC_DPM_FEATURE);
 446 }
 447
 448 static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,
 449                                             struct pp_smu_wm_range_sets *clock_ranges)
 450 {
 451         int i;
 452         int ret = 0;
 453         Watermarks_t *table = smu->smu_table.watermarks_table;
 454
 455         if (!table || !clock_ranges)
 456                 return -EINVAL;
 457
 458         if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
 459                 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
 460                 return -EINVAL;
 461
 462         for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
 463                 table->WatermarkRow[WM_DCFCLK][i].MinClock =
 464                         clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
 465                 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
 466                         clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
 467                 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
 468                         clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
 469                 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
 470                         clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
 471
 472                 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
 473                         clock_ranges->reader_wm_sets[i].wm_inst;
 474         }
 475
 476         for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
 477                 table->WatermarkRow[WM_SOCCLK][i].MinClock =
 478                         clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
 479                 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
 480                         clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
 481                 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
 482                         clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
 483                 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
 484                         clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
 485
 486                 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
 487                         clock_ranges->writer_wm_sets[i].wm_inst;
 488         }
 489
 490         smu->watermarks_bitmap |= WATERMARKS_EXIST;
 491
 492         /* pass data to smu controller */
 493         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 494              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 495                 ret = smu_cmn_write_watermarks_table(smu);
 496                 if (ret) {
 497                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
 498                         return ret;
 499                 }
 500                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
 507                                                 void **table)
 508 {
 509         struct smu_table_context *smu_table = &smu->smu_table;
 510         struct gpu_metrics_v3_0 *gpu_metrics =
 511                 (struct gpu_metrics_v3_0 *)smu_table->gpu_metrics_table;
 512         SmuMetrics_t metrics;
 513         int ret = 0;
 514
 515         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
 516         if (ret)
 517                 return ret;
 518
 519         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 3, 0);
 520
 521         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 522         gpu_metrics->temperature_soc = metrics.SocTemperature;
 523         memcpy(&gpu_metrics->temperature_core[0],
 524                 &metrics.CoreTemperature[0],
 525                 sizeof(uint16_t) * 16);
 526         gpu_metrics->temperature_skin = metrics.SkinTemp;
 527
 528         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
 529         gpu_metrics->average_vcn_activity = metrics.VcnActivity;
 530         memcpy(&gpu_metrics->average_ipu_activity[0],
 531                 &metrics.IpuBusy[0],
 532                 sizeof(uint16_t) * 8);
 533         memcpy(&gpu_metrics->average_core_c0_activity[0],
 534                 &metrics.CoreC0Residency[0],
 535                 sizeof(uint16_t) * 16);
 536         gpu_metrics->average_dram_reads = metrics.DRAMReads;
 537         gpu_metrics->average_dram_writes = metrics.DRAMWrites;
 538         gpu_metrics->average_ipu_reads = metrics.IpuReads;
 539         gpu_metrics->average_ipu_writes = metrics.IpuWrites;
 540
 541         gpu_metrics->average_socket_power = metrics.SocketPower;
 542         gpu_metrics->average_ipu_power = metrics.IpuPower;
 543         gpu_metrics->average_apu_power = metrics.ApuPower;
 544         gpu_metrics->average_gfx_power = metrics.GfxPower;
 545         gpu_metrics->average_dgpu_power = metrics.dGpuPower;
 546         gpu_metrics->average_all_core_power = metrics.AllCorePower;
 547         gpu_metrics->average_sys_power = metrics.Psys;
 548         memcpy(&gpu_metrics->average_core_power[0],
 549                 &metrics.CorePower[0],
 550                 sizeof(uint16_t) * 16);
 551
 552         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
 553         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
 554         gpu_metrics->average_vpeclk_frequency = metrics.VpeclkFrequency;
 555         gpu_metrics->average_fclk_frequency = metrics.FclkFrequency;
 556         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
 557         gpu_metrics->average_ipuclk_frequency = metrics.IpuclkFrequency;
 558         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
 559         gpu_metrics->average_mpipu_frequency = metrics.MpipuclkFrequency;
 560
 561         memcpy(&gpu_metrics->current_coreclk[0],
 562                 &metrics.CoreFrequency[0],
 563                 sizeof(uint16_t) * 16);
 564         gpu_metrics->current_core_maxfreq = metrics.InfrastructureCpuMaxFreq;
 565         gpu_metrics->current_gfx_maxfreq = metrics.InfrastructureGfxMaxFreq;
 566
 567         gpu_metrics->throttle_residency_prochot = metrics.ThrottleResidency_PROCHOT;
 568         gpu_metrics->throttle_residency_spl = metrics.ThrottleResidency_SPL;
 569         gpu_metrics->throttle_residency_fppt = metrics.ThrottleResidency_FPPT;
 570         gpu_metrics->throttle_residency_sppt = metrics.ThrottleResidency_SPPT;
 571         gpu_metrics->throttle_residency_thm_core = metrics.ThrottleResidency_THM_CORE;
 572         gpu_metrics->throttle_residency_thm_gfx = metrics.ThrottleResidency_THM_GFX;
 573         gpu_metrics->throttle_residency_thm_soc = metrics.ThrottleResidency_THM_SOC;
 574
 575         gpu_metrics->time_filter_alphavalue = metrics.FilterAlphaValue;
 576         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 577
 578         *table = (void *)gpu_metrics;
 579
 580         return sizeof(struct gpu_metrics_v3_0);
 581 }
 582
 583 static int smu_v14_0_0_mode2_reset(struct smu_context *smu)
 584 {
 585         int ret;
 586
 587         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
 588                                                SMU_RESET_MODE_2, NULL);
 589
 590         if (ret)
 591                 dev_err(smu->adev->dev, "Failed to mode2 reset!\n");
 592
 593         return ret;
 594 }
 595
 596 static int smu_v14_0_1_get_dpm_freq_by_index(struct smu_context *smu,
 597                                                 enum smu_clk_type clk_type,
 598                                                 uint32_t dpm_level,
 599                                                 uint32_t *freq)
 600 {
 601         DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
 602
 603         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 604                 return -EINVAL;
 605
 606         switch (clk_type) {
 607         case SMU_SOCCLK:
 608                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 609                         return -EINVAL;
 610                 *freq = clk_table->SocClocks[dpm_level];
 611                 break;
 612         case SMU_VCLK:
 613                 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled)
 614                         return -EINVAL;
 615                 *freq = clk_table->VClocks0[dpm_level];
 616                 break;
 617         case SMU_DCLK:
 618                 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled)
 619                         return -EINVAL;
 620                 *freq = clk_table->DClocks0[dpm_level];
 621                 break;
 622         case SMU_VCLK1:
 623                 if (dpm_level >= clk_table->Vcn1ClkLevelsEnabled)
 624                         return -EINVAL;
 625                 *freq = clk_table->VClocks1[dpm_level];
 626                 break;
 627         case SMU_DCLK1:
 628                 if (dpm_level >= clk_table->Vcn1ClkLevelsEnabled)
 629                         return -EINVAL;
 630                 *freq = clk_table->DClocks1[dpm_level];
 631                 break;
 632         case SMU_UCLK:
 633         case SMU_MCLK:
 634                 if (dpm_level >= clk_table->NumMemPstatesEnabled)
 635                         return -EINVAL;
 636                 *freq = clk_table->MemPstateTable[dpm_level].MemClk;
 637                 break;
 638         case SMU_FCLK:
 639                 if (dpm_level >= clk_table->NumFclkLevelsEnabled)
 640                         return -EINVAL;
 641                 *freq = clk_table->FclkClocks_Freq[dpm_level];
 642                 break;
 643         default:
 644                 return -EINVAL;
 645         }
 646
 647         return 0;
 648 }
 649
 650 static int smu_v14_0_0_get_dpm_freq_by_index(struct smu_context *smu,
 651                                                 enum smu_clk_type clk_type,
 652                                                 uint32_t dpm_level,
 653                                                 uint32_t *freq)
 654 {
 655         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 656
 657         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 658                 return -EINVAL;
 659
 660         switch (clk_type) {
 661         case SMU_SOCCLK:
 662                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 663                         return -EINVAL;
 664                 *freq = clk_table->SocClocks[dpm_level];
 665                 break;
 666         case SMU_VCLK:
 667                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 668                         return -EINVAL;
 669                 *freq = clk_table->VClocks[dpm_level];
 670                 break;
 671         case SMU_DCLK:
 672                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 673                         return -EINVAL;
 674                 *freq = clk_table->DClocks[dpm_level];
 675                 break;
 676         case SMU_UCLK:
 677         case SMU_MCLK:
 678                 if (dpm_level >= clk_table->NumMemPstatesEnabled)
 679                         return -EINVAL;
 680                 *freq = clk_table->MemPstateTable[dpm_level].MemClk;
 681                 break;
 682         case SMU_FCLK:
 683                 if (dpm_level >= clk_table->NumFclkLevelsEnabled)
 684                         return -EINVAL;
 685                 *freq = clk_table->FclkClocks_Freq[dpm_level];
 686                 break;
 687         default:
 688                 return -EINVAL;
 689         }
 690
 691         return 0;
 692 }
 693
 694 static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu,
 695                                                 enum smu_clk_type clk_type,
 696                                                 uint32_t dpm_level,
 697                                                 uint32_t *freq)
 698 {
 699         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
 700                 smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
 701         else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
 702                 smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
 703
 704         return 0;
 705 }
 706
 707 static bool smu_v14_0_0_clk_dpm_is_enabled(struct smu_context *smu,
 708                                                 enum smu_clk_type clk_type)
 709 {
 710         enum smu_feature_mask feature_id = 0;
 711
 712         switch (clk_type) {
 713         case SMU_MCLK:
 714         case SMU_UCLK:
 715         case SMU_FCLK:
 716                 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 717                 break;
 718         case SMU_GFXCLK:
 719         case SMU_SCLK:
 720                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 721                 break;
 722         case SMU_SOCCLK:
 723                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 724                 break;
 725         case SMU_VCLK:
 726         case SMU_DCLK:
 727         case SMU_VCLK1:
 728         case SMU_DCLK1:
 729                 feature_id = SMU_FEATURE_VCN_DPM_BIT;
 730                 break;
 731         default:
 732                 return true;
 733         }
 734
 735         return smu_cmn_feature_is_enabled(smu, feature_id);
 736 }
 737
 738 static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
 739                                                         enum smu_clk_type clk_type,
 740                                                         uint32_t *min,
 741                                                         uint32_t *max)
 742 {
 743         DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
 744         uint32_t clock_limit;
 745         uint32_t max_dpm_level, min_dpm_level;
 746         int ret = 0;
 747
 748         if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {
 749                 switch (clk_type) {
 750                 case SMU_MCLK:
 751                 case SMU_UCLK:
 752                         clock_limit = smu->smu_table.boot_values.uclk;
 753                         break;
 754                 case SMU_FCLK:
 755                         clock_limit = smu->smu_table.boot_values.fclk;
 756                         break;
 757                 case SMU_GFXCLK:
 758                 case SMU_SCLK:
 759                         clock_limit = smu->smu_table.boot_values.gfxclk;
 760                         break;
 761                 case SMU_SOCCLK:
 762                         clock_limit = smu->smu_table.boot_values.socclk;
 763                         break;
 764                 case SMU_VCLK:
 765                 case SMU_VCLK1:
 766                         clock_limit = smu->smu_table.boot_values.vclk;
 767                         break;
 768                 case SMU_DCLK:
 769                 case SMU_DCLK1:
 770                         clock_limit = smu->smu_table.boot_values.dclk;
 771                         break;
 772                 default:
 773                         clock_limit = 0;
 774                         break;
 775                 }
 776
 777                 /* clock in Mhz unit */
 778                 if (min)
 779                         *min = clock_limit / 100;
 780                 if (max)
 781                         *max = clock_limit / 100;
 782
 783                 return 0;
 784         }
 785
 786         if (max) {
 787                 switch (clk_type) {
 788                 case SMU_GFXCLK:
 789                 case SMU_SCLK:
 790                         *max = clk_table->MaxGfxClk;
 791                         break;
 792                 case SMU_MCLK:
 793                 case SMU_UCLK:
 794                 case SMU_FCLK:
 795                         max_dpm_level = 0;
 796                         break;
 797                 case SMU_SOCCLK:
 798                         max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
 799                         break;
 800                 case SMU_VCLK:
 801                 case SMU_DCLK:
 802                         max_dpm_level = clk_table->Vcn0ClkLevelsEnabled - 1;
 803                         break;
 804                 case SMU_VCLK1:
 805                 case SMU_DCLK1:
 806                         max_dpm_level = clk_table->Vcn1ClkLevelsEnabled - 1;
 807                         break;
 808                 default:
 809                         ret = -EINVAL;
 810                         goto failed;
 811                 }
 812
 813                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 814                         ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
 815                         if (ret)
 816                                 goto failed;
 817                 }
 818         }
 819
 820         if (min) {
 821                 switch (clk_type) {
 822                 case SMU_GFXCLK:
 823                 case SMU_SCLK:
 824                         *min = clk_table->MinGfxClk;
 825                         break;
 826                 case SMU_MCLK:
 827                 case SMU_UCLK:
 828                         min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
 829                         break;
 830                 case SMU_FCLK:
 831                         min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
 832                         break;
 833                 case SMU_SOCCLK:
 834                         min_dpm_level = 0;
 835                         break;
 836                 case SMU_VCLK:
 837                 case SMU_DCLK:
 838                 case SMU_VCLK1:
 839                 case SMU_DCLK1:
 840                         min_dpm_level = 0;
 841                         break;
 842                 default:
 843                         ret = -EINVAL;
 844                         goto failed;
 845                 }
 846
 847                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 848                         ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
 849                         if (ret)
 850                                 goto failed;
 851                 }
 852         }
 853
 854 failed:
 855         return ret;
 856 }
 857
 858 static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
 859                                                         enum smu_clk_type clk_type,
 860                                                         uint32_t *min,
 861                                                         uint32_t *max)
 862 {
 863         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 864         uint32_t clock_limit;
 865         uint32_t max_dpm_level, min_dpm_level;
 866         int ret = 0;
 867
 868         if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {
 869                 switch (clk_type) {
 870                 case SMU_MCLK:
 871                 case SMU_UCLK:
 872                         clock_limit = smu->smu_table.boot_values.uclk;
 873                         break;
 874                 case SMU_FCLK:
 875                         clock_limit = smu->smu_table.boot_values.fclk;
 876                         break;
 877                 case SMU_GFXCLK:
 878                 case SMU_SCLK:
 879                         clock_limit = smu->smu_table.boot_values.gfxclk;
 880                         break;
 881                 case SMU_SOCCLK:
 882                         clock_limit = smu->smu_table.boot_values.socclk;
 883                         break;
 884                 case SMU_VCLK:
 885                         clock_limit = smu->smu_table.boot_values.vclk;
 886                         break;
 887                 case SMU_DCLK:
 888                         clock_limit = smu->smu_table.boot_values.dclk;
 889                         break;
 890                 default:
 891                         clock_limit = 0;
 892                         break;
 893                 }
 894
 895                 /* clock in Mhz unit */
 896                 if (min)
 897                         *min = clock_limit / 100;
 898                 if (max)
 899                         *max = clock_limit / 100;
 900
 901                 return 0;
 902         }
 903
 904         if (max) {
 905                 switch (clk_type) {
 906                 case SMU_GFXCLK:
 907                 case SMU_SCLK:
 908                         *max = clk_table->MaxGfxClk;
 909                         break;
 910                 case SMU_MCLK:
 911                 case SMU_UCLK:
 912                 case SMU_FCLK:
 913                         max_dpm_level = 0;
 914                         break;
 915                 case SMU_SOCCLK:
 916                         max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
 917                         break;
 918                 case SMU_VCLK:
 919                 case SMU_DCLK:
 920                         max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
 921                         break;
 922                 default:
 923                         ret = -EINVAL;
 924                         goto failed;
 925                 }
 926
 927                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 928                         ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
 929                         if (ret)
 930                                 goto failed;
 931                 }
 932         }
 933
 934         if (min) {
 935                 switch (clk_type) {
 936                 case SMU_GFXCLK:
 937                 case SMU_SCLK:
 938                         *min = clk_table->MinGfxClk;
 939                         break;
 940                 case SMU_MCLK:
 941                 case SMU_UCLK:
 942                         min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
 943                         break;
 944                 case SMU_FCLK:
 945                         min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
 946                         break;
 947                 case SMU_SOCCLK:
 948                         min_dpm_level = 0;
 949                         break;
 950                 case SMU_VCLK:
 951                 case SMU_DCLK:
 952                         min_dpm_level = 0;
 953                         break;
 954                 default:
 955                         ret = -EINVAL;
 956                         goto failed;
 957                 }
 958
 959                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 960                         ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
 961                         if (ret)
 962                                 goto failed;
 963                 }
 964         }
 965
 966 failed:
 967         return ret;
 968 }
 969
 970 static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
 971                                                         enum smu_clk_type clk_type,
 972                                                         uint32_t *min,
 973                                                         uint32_t *max)
 974 {
 975         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
 976                 smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
 977         else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
 978                 smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
 979
 980         return 0;
 981 }
 982
 983 static int smu_v14_0_0_get_current_clk_freq(struct smu_context *smu,
 984                                             enum smu_clk_type clk_type,
 985                                             uint32_t *value)
 986 {
 987         MetricsMember_t member_type;
 988
 989         switch (clk_type) {
 990         case SMU_SOCCLK:
 991                 member_type = METRICS_AVERAGE_SOCCLK;
 992                 break;
 993         case SMU_VCLK:
 994                 member_type = METRICS_AVERAGE_VCLK;
 995                 break;
 996         case SMU_DCLK:
 997                 member_type = METRICS_AVERAGE_DCLK;
 998                 break;
 999         case SMU_MCLK:
1000                 member_type = METRICS_AVERAGE_UCLK;
1001                 break;
1002         case SMU_FCLK:
1003                 member_type = METRICS_AVERAGE_FCLK;
1004                 break;
1005         case SMU_GFXCLK:
1006         case SMU_SCLK:
1007                 member_type = METRICS_AVERAGE_GFXCLK;
1008                 break;
1009         default:
1010                 return -EINVAL;
1011         }
1012
1013         return smu_v14_0_0_get_smu_metrics_data(smu, member_type, value);
1014 }
1015
1016 static int smu_v14_0_1_get_dpm_level_count(struct smu_context *smu,
1017                                            enum smu_clk_type clk_type,
1018                                            uint32_t *count)
1019 {
1020         DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
1021
1022         switch (clk_type) {
1023         case SMU_SOCCLK:
1024                 *count = clk_table->NumSocClkLevelsEnabled;
1025                 break;
1026         case SMU_VCLK:
1027         case SMU_DCLK:
1028                 *count = clk_table->Vcn0ClkLevelsEnabled;
1029                 break;
1030         case SMU_VCLK1:
1031         case SMU_DCLK1:
1032                 *count = clk_table->Vcn1ClkLevelsEnabled;
1033                 break;
1034         case SMU_MCLK:
1035                 *count = clk_table->NumMemPstatesEnabled;
1036                 break;
1037         case SMU_FCLK:
1038                 *count = clk_table->NumFclkLevelsEnabled;
1039                 break;
1040         default:
1041                 break;
1042         }
1043
1044         return 0;
1045 }
1046
1047 static int smu_v14_0_0_get_dpm_level_count(struct smu_context *smu,
1048                                            enum smu_clk_type clk_type,
1049                                            uint32_t *count)
1050 {
1051         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1052
1053         switch (clk_type) {
1054         case SMU_SOCCLK:
1055                 *count = clk_table->NumSocClkLevelsEnabled;
1056                 break;
1057         case SMU_VCLK:
1058                 *count = clk_table->VcnClkLevelsEnabled;
1059                 break;
1060         case SMU_DCLK:
1061                 *count = clk_table->VcnClkLevelsEnabled;
1062                 break;
1063         case SMU_MCLK:
1064                 *count = clk_table->NumMemPstatesEnabled;
1065                 break;
1066         case SMU_FCLK:
1067                 *count = clk_table->NumFclkLevelsEnabled;
1068                 break;
1069         default:
1070                 break;
1071         }
1072
1073         return 0;
1074 }
1075
1076 static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu,
1077                                            enum smu_clk_type clk_type,
1078                                            uint32_t *count)
1079 {
1080         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1081                 smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
1082         else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1083                 smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);
1084
1085         return 0;
1086 }
1087
1088 static int smu_v14_0_0_print_clk_levels(struct smu_context *smu,
1089                                         enum smu_clk_type clk_type, char *buf)
1090 {
1091         int i, size = 0, ret = 0;
1092         uint32_t cur_value = 0, value = 0, count = 0;
1093         uint32_t min, max;
1094
1095         smu_cmn_get_sysfs_buf(&buf, &size);
1096
1097         switch (clk_type) {
1098         case SMU_OD_SCLK:
1099                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1100                 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
1101                 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1102                 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
1103                 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1104                 break;
1105         case SMU_OD_RANGE:
1106                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1107                 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1108                                       smu->gfx_default_hard_min_freq,
1109                                       smu->gfx_default_soft_max_freq);
1110                 break;
1111         case SMU_SOCCLK:
1112         case SMU_VCLK:
1113         case SMU_DCLK:
1114         case SMU_VCLK1:
1115         case SMU_DCLK1:
1116         case SMU_MCLK:
1117         case SMU_FCLK:
1118                 ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
1119                 if (ret)
1120                         break;
1121
1122                 ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count);
1123                 if (ret)
1124                         break;
1125
1126                 for (i = 0; i < count; i++) {
1127                         ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, i, &value);
1128                         if (ret)
1129                                 break;
1130
1131                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1132                                               cur_value == value ? "*" : "");
1133                 }
1134                 break;
1135         case SMU_GFXCLK:
1136         case SMU_SCLK:
1137                 ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
1138                 if (ret)
1139                         break;
1140                 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1141                 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1142                 if (cur_value  == max)
1143                         i = 2;
1144                 else if (cur_value == min)
1145                         i = 0;
1146                 else
1147                         i = 1;
1148                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
1149                                       i == 0 ? "*" : "");
1150                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1151                                       i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */
1152                                       i == 1 ? "*" : "");
1153                 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
1154                                       i == 2 ? "*" : "");
1155                 break;
1156         default:
1157                 break;
1158         }
1159
1160         return size;
1161 }
1162
1163 static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu,
1164                                                    enum smu_clk_type clk_type,
1165                                                    uint32_t min,
1166                                                    uint32_t max)
1167 {
1168         enum smu_message_type msg_set_min, msg_set_max;
1169         int ret = 0;
1170
1171         if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type))
1172                 return -EINVAL;
1173
1174         switch (clk_type) {
1175         case SMU_GFXCLK:
1176         case SMU_SCLK:
1177                 msg_set_min = SMU_MSG_SetHardMinGfxClk;
1178                 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
1179                 break;
1180         case SMU_FCLK:
1181                 msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
1182                 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
1183                 break;
1184         case SMU_SOCCLK:
1185                 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
1186                 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
1187                 break;
1188         case SMU_VCLK:
1189         case SMU_DCLK:
1190                 msg_set_min = SMU_MSG_SetHardMinVcn0;
1191                 msg_set_max = SMU_MSG_SetSoftMaxVcn0;
1192                 break;
1193         case SMU_VCLK1:
1194         case SMU_DCLK1:
1195                 msg_set_min = SMU_MSG_SetHardMinVcn1;
1196                 msg_set_max = SMU_MSG_SetSoftMaxVcn1;
1197                 break;
1198         default:
1199                 return -EINVAL;
1200         }
1201
1202         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
1203         if (ret)
1204                 return ret;
1205
1206         return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
1207                                                max, NULL);
1208 }
1209
1210 static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
1211                                         enum smu_clk_type clk_type,
1212                                         uint32_t mask)
1213 {
1214         uint32_t soft_min_level = 0, soft_max_level = 0;
1215         uint32_t min_freq = 0, max_freq = 0;
1216         int ret = 0;
1217
1218         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1219         soft_max_level = mask ? (fls(mask) - 1) : 0;
1220
1221         switch (clk_type) {
1222         case SMU_SOCCLK:
1223         case SMU_FCLK:
1224         case SMU_VCLK:
1225         case SMU_DCLK:
1226                 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1227                 if (ret)
1228                         break;
1229
1230                 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1231                 if (ret)
1232                         break;
1233
1234                 ret = smu_v14_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1235                 break;
1236         default:
1237                 ret = -EINVAL;
1238                 break;
1239         }
1240
1241         return ret;
1242 }
1243
1244 static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
1245                                              enum amd_dpm_forced_level level)
1246 {
1247         struct amdgpu_device *adev = smu->adev;
1248         uint32_t sclk_min = 0, sclk_max = 0;
1249         uint32_t fclk_min = 0, fclk_max = 0;
1250         uint32_t socclk_min = 0, socclk_max = 0;
1251         int ret = 0;
1252
1253         switch (level) {
1254         case AMD_DPM_FORCED_LEVEL_HIGH:
1255                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1256                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
1257                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1258                 sclk_min = sclk_max;
1259                 fclk_min = fclk_max;
1260                 socclk_min = socclk_max;
1261                 break;
1262         case AMD_DPM_FORCED_LEVEL_LOW:
1263                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1264                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1265                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1266                 sclk_max = sclk_min;
1267                 fclk_max = fclk_min;
1268                 socclk_max = socclk_min;
1269                 break;
1270         case AMD_DPM_FORCED_LEVEL_AUTO:
1271                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1272                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1273                 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1274                 break;
1275         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1276         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1277         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1278         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1279                 /* Temporarily do nothing since the optimal clocks haven't been provided yet */
1280                 break;
1281         case AMD_DPM_FORCED_LEVEL_MANUAL:
1282         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1283                 return 0;
1284         default:
1285                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1286                 return -EINVAL;
1287         }
1288
1289         if (sclk_min && sclk_max) {
1290                 ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1291                                                               SMU_SCLK,
1292                                                               sclk_min,
1293                                                               sclk_max);
1294                 if (ret)
1295                         return ret;
1296
1297                 smu->gfx_actual_hard_min_freq = sclk_min;
1298                 smu->gfx_actual_soft_max_freq = sclk_max;
1299         }
1300
1301         if (fclk_min && fclk_max) {
1302                 ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1303                                                               SMU_FCLK,
1304                                                               fclk_min,
1305                                                               fclk_max);
1306                 if (ret)
1307                         return ret;
1308         }
1309
1310         if (socclk_min && socclk_max) {
1311                 ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1312                                                               SMU_SOCCLK,
1313                                                               socclk_min,
1314                                                               socclk_max);
1315                 if (ret)
1316                         return ret;
1317         }
1318
1319         return ret;
1320 }
1321
1322 static int smu_v14_0_1_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1323 {
1324         DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
1325
1326         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1327         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1328         smu->gfx_actual_hard_min_freq = 0;
1329         smu->gfx_actual_soft_max_freq = 0;
1330
1331         return 0;
1332 }
1333
1334 static int smu_v14_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1335 {
1336         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1337
1338         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1339         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1340         smu->gfx_actual_hard_min_freq = 0;
1341         smu->gfx_actual_soft_max_freq = 0;
1342
1343         return 0;
1344 }
1345
1346 static int smu_v14_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1347 {
1348         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1349                 smu_v14_0_0_set_fine_grain_gfx_freq_parameters(smu);
1350         else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1351                 smu_v14_0_1_set_fine_grain_gfx_freq_parameters(smu);
1352
1353         return 0;
1354 }
1355
1356 static int smu_v14_0_0_set_vpe_enable(struct smu_context *smu,
1357                                       bool enable)
1358 {
1359         return smu_cmn_send_smc_msg_with_param(smu, enable ?
1360                                                SMU_MSG_PowerUpVpe : SMU_MSG_PowerDownVpe,
1361                                                0, NULL);
1362 }
1363
1364 static int smu_v14_0_0_set_umsch_mm_enable(struct smu_context *smu,
1365                               bool enable)
1366 {
1367         return smu_cmn_send_smc_msg_with_param(smu, enable ?
1368                                                SMU_MSG_PowerUpUmsch : SMU_MSG_PowerDownUmsch,
1369                                                0, NULL);
1370 }
1371
1372 static int smu_14_0_1_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1373 {
1374         DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
1375         uint8_t idx;
1376
1377         /* Only the Clock information of SOC and VPE is copied to provide VPE DPM settings for use. */
1378         for (idx = 0; idx < NUM_SOCCLK_DPM_LEVELS; idx++) {
1379                 clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClocks[idx]:0;
1380                 clock_table->SocClocks[idx].Vol = 0;
1381         }
1382
1383         for (idx = 0; idx < NUM_VPE_DPM_LEVELS; idx++) {
1384                 clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[idx]:0;
1385                 clock_table->VPEClocks[idx].Vol = 0;
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1392 {
1393         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1394         uint8_t idx;
1395
1396         /* Only the Clock information of SOC and VPE is copied to provide VPE DPM settings for use. */
1397         for (idx = 0; idx < NUM_SOCCLK_DPM_LEVELS; idx++) {
1398                 clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClocks[idx]:0;
1399                 clock_table->SocClocks[idx].Vol = 0;
1400         }
1401
1402         for (idx = 0; idx < NUM_VPE_DPM_LEVELS; idx++) {
1403                 clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[idx]:0;
1404                 clock_table->VPEClocks[idx].Vol = 0;
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1411 {
1412         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1413                 smu_14_0_0_get_dpm_table(smu, clock_table);
1414         else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1415                 smu_14_0_1_get_dpm_table(smu, clock_table);
1416
1417         return 0;
1418 }
1419
1420 static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {
1421         .check_fw_status = smu_v14_0_check_fw_status,
1422         .check_fw_version = smu_v14_0_check_fw_version,
1423         .init_smc_tables = smu_v14_0_0_init_smc_tables,
1424         .fini_smc_tables = smu_v14_0_0_fini_smc_tables,
1425         .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values,
1426         .system_features_control = smu_v14_0_0_system_features_control,
1427         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1428         .send_smc_msg = smu_cmn_send_smc_msg,
1429         .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable,
1430         .dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable,
1431         .set_default_dpm_table = smu_v14_0_set_default_dpm_tables,
1432         .read_sensor = smu_v14_0_0_read_sensor,
1433         .is_dpm_running = smu_v14_0_0_is_dpm_running,
1434         .set_watermarks_table = smu_v14_0_0_set_watermarks_table,
1435         .get_gpu_metrics = smu_v14_0_0_get_gpu_metrics,
1436         .get_enabled_mask = smu_cmn_get_enabled_mask,
1437         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1438         .set_driver_table_location = smu_v14_0_set_driver_table_location,
1439         .gfx_off_control = smu_v14_0_gfx_off_control,
1440         .mode2_reset = smu_v14_0_0_mode2_reset,
1441         .get_dpm_ultimate_freq = smu_v14_0_common_get_dpm_ultimate_freq,
1442         .od_edit_dpm_table = smu_v14_0_od_edit_dpm_table,
1443         .print_clk_levels = smu_v14_0_0_print_clk_levels,
1444         .force_clk_levels = smu_v14_0_0_force_clk_levels,
1445         .set_performance_level = smu_v14_0_0_set_performance_level,
1446         .set_fine_grain_gfx_freq_parameters = smu_v14_0_common_set_fine_grain_gfx_freq_parameters,
1447         .set_gfx_power_up_by_imu = smu_v14_0_set_gfx_power_up_by_imu,
1448         .dpm_set_vpe_enable = smu_v14_0_0_set_vpe_enable,
1449         .dpm_set_umsch_mm_enable = smu_v14_0_0_set_umsch_mm_enable,
1450         .get_dpm_clock_table = smu_v14_0_common_get_dpm_table,
1451 };
1452
1453 static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)
1454 {
1455         struct amdgpu_device *adev = smu->adev;
1456
1457         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1458         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1459         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1460 }
1461
1462 void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu)
1463 {
1464
1465         smu->ppt_funcs = &smu_v14_0_0_ppt_funcs;
1466         smu->message_map = smu_v14_0_0_message_map;
1467         smu->feature_map = smu_v14_0_0_feature_mask_map;
1468         smu->table_map = smu_v14_0_0_table_map;
1469         smu->is_apu = true;
1470
1471         smu_v14_0_0_set_smu_mailbox_registers(smu);
1472 }