2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define SWSMU_CODE_LAYER_L1
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27 #include <linux/power_supply.h>
28 #include <linux/reboot.h>
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
34 #include "arcturus_ppt.h"
35 #include "navi10_ppt.h"
36 #include "sienna_cichlid_ppt.h"
37 #include "renoir_ppt.h"
38 #include "vangogh_ppt.h"
39 #include "aldebaran_ppt.h"
40 #include "yellow_carp_ppt.h"
41 #include "cyan_skillfish_ppt.h"
42 #include "smu_v13_0_0_ppt.h"
43 #include "smu_v13_0_4_ppt.h"
44 #include "smu_v13_0_5_ppt.h"
45 #include "smu_v13_0_6_ppt.h"
46 #include "smu_v13_0_7_ppt.h"
47 #include "smu_v14_0_0_ppt.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 static const struct amd_pm_funcs swsmu_pm_funcs;
61 static int smu_force_smuclk_levels(struct smu_context *smu,
62 enum smu_clk_type clk_type,
64 static int smu_handle_task(struct smu_context *smu,
65 enum amd_dpm_forced_level level,
66 enum amd_pp_task task_id);
67 static int smu_reset(struct smu_context *smu);
68 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
69 static int smu_set_fan_control_mode(void *handle, u32 value);
70 static int smu_set_power_limit(void *handle, uint32_t limit);
71 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
72 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
73 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
75 static int smu_sys_get_pp_feature_mask(void *handle,
78 struct smu_context *smu = handle;
80 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
83 return smu_get_pp_feature_mask(smu, buf);
86 static int smu_sys_set_pp_feature_mask(void *handle,
89 struct smu_context *smu = handle;
91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
94 return smu_set_pp_feature_mask(smu, new_mask);
97 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
99 if (!smu->ppt_funcs->set_gfx_off_residency)
102 return smu_set_gfx_off_residency(smu, value);
105 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
107 if (!smu->ppt_funcs->get_gfx_off_residency)
110 return smu_get_gfx_off_residency(smu, value);
113 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
115 if (!smu->ppt_funcs->get_gfx_off_entrycount)
118 return smu_get_gfx_off_entrycount(smu, value);
121 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
123 if (!smu->ppt_funcs->get_gfx_off_status)
126 *value = smu_get_gfx_off_status(smu);
131 int smu_set_soft_freq_range(struct smu_context *smu,
132 enum smu_clk_type clk_type,
138 if (smu->ppt_funcs->set_soft_freq_limited_range)
139 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
147 int smu_get_dpm_freq_range(struct smu_context *smu,
148 enum smu_clk_type clk_type,
157 if (smu->ppt_funcs->get_dpm_ultimate_freq)
158 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
166 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
169 struct amdgpu_device *adev = smu->adev;
171 if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
172 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
174 dev_err(adev->dev, "Failed to enable gfx imu!\n");
179 static u32 smu_get_mclk(void *handle, bool low)
181 struct smu_context *smu = handle;
185 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
186 low ? &clk_freq : NULL,
187 !low ? &clk_freq : NULL);
190 return clk_freq * 100;
193 static u32 smu_get_sclk(void *handle, bool low)
195 struct smu_context *smu = handle;
199 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
200 low ? &clk_freq : NULL,
201 !low ? &clk_freq : NULL);
204 return clk_freq * 100;
207 static int smu_set_gfx_imu_enable(struct smu_context *smu)
209 struct amdgpu_device *adev = smu->adev;
211 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
214 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
217 return smu_set_gfx_power_up_by_imu(smu);
220 static bool is_vcn_enabled(struct amdgpu_device *adev)
224 for (i = 0; i < adev->num_ip_blocks; i++) {
225 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
226 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) &&
227 !adev->ip_blocks[i].status.valid)
234 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
237 struct smu_power_context *smu_power = &smu->smu_power;
238 struct smu_power_gate *power_gate = &smu_power->power_gate;
242 * don't poweron vcn/jpeg when they are skipped.
244 if (!is_vcn_enabled(smu->adev))
247 if (!smu->ppt_funcs->dpm_set_vcn_enable)
250 if (atomic_read(&power_gate->vcn_gated) ^ enable)
253 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
255 atomic_set(&power_gate->vcn_gated, !enable);
260 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
263 struct smu_power_context *smu_power = &smu->smu_power;
264 struct smu_power_gate *power_gate = &smu_power->power_gate;
267 if (!is_vcn_enabled(smu->adev))
270 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
273 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
276 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
278 atomic_set(&power_gate->jpeg_gated, !enable);
283 static int smu_dpm_set_vpe_enable(struct smu_context *smu,
286 struct smu_power_context *smu_power = &smu->smu_power;
287 struct smu_power_gate *power_gate = &smu_power->power_gate;
290 if (!smu->ppt_funcs->dpm_set_vpe_enable)
293 if (atomic_read(&power_gate->vpe_gated) ^ enable)
296 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable);
298 atomic_set(&power_gate->vpe_gated, !enable);
303 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu,
306 struct smu_power_context *smu_power = &smu->smu_power;
307 struct smu_power_gate *power_gate = &smu_power->power_gate;
310 if (!smu->adev->enable_umsch_mm)
313 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable)
316 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable)
319 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable);
321 atomic_set(&power_gate->umsch_mm_gated, !enable);
327 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
329 * @handle: smu_context pointer
330 * @block_type: the IP block to power gate/ungate
331 * @gate: to power gate if true, ungate otherwise
333 * This API uses no smu->mutex lock protection due to:
334 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
335 * This is guarded to be race condition free by the caller.
336 * 2. Or get called on user setting request of power_dpm_force_performance_level.
337 * Under this case, the smu->mutex lock protection is already enforced on
338 * the parent API smu_force_performance_level of the call path.
340 static int smu_dpm_set_power_gate(void *handle,
344 struct smu_context *smu = handle;
347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
348 dev_WARN(smu->adev->dev,
349 "SMU uninitialized but power %s requested for %u!\n",
350 gate ? "gate" : "ungate", block_type);
354 switch (block_type) {
356 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
357 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
359 case AMD_IP_BLOCK_TYPE_UVD:
360 case AMD_IP_BLOCK_TYPE_VCN:
361 ret = smu_dpm_set_vcn_enable(smu, !gate);
363 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
364 gate ? "gate" : "ungate");
366 case AMD_IP_BLOCK_TYPE_GFX:
367 ret = smu_gfx_off_control(smu, gate);
369 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
370 gate ? "enable" : "disable");
372 case AMD_IP_BLOCK_TYPE_SDMA:
373 ret = smu_powergate_sdma(smu, gate);
375 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
376 gate ? "gate" : "ungate");
378 case AMD_IP_BLOCK_TYPE_JPEG:
379 ret = smu_dpm_set_jpeg_enable(smu, !gate);
381 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
382 gate ? "gate" : "ungate");
384 case AMD_IP_BLOCK_TYPE_VPE:
385 ret = smu_dpm_set_vpe_enable(smu, !gate);
387 dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
388 gate ? "gate" : "ungate");
391 dev_err(smu->adev->dev, "Unsupported block type!\n");
399 * smu_set_user_clk_dependencies - set user profile clock dependencies
401 * @smu: smu_context pointer
402 * @clk: enum smu_clk_type type
404 * Enable/Disable the clock dependency for the @clk type.
406 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
408 if (smu->adev->in_suspend)
411 if (clk == SMU_MCLK) {
412 smu->user_dpm_profile.clk_dependency = 0;
413 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
414 } else if (clk == SMU_FCLK) {
415 /* MCLK takes precedence over FCLK */
416 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
419 smu->user_dpm_profile.clk_dependency = 0;
420 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
421 } else if (clk == SMU_SOCCLK) {
422 /* MCLK takes precedence over SOCCLK */
423 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
426 smu->user_dpm_profile.clk_dependency = 0;
427 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
429 /* Add clk dependencies here, if any */
434 * smu_restore_dpm_user_profile - reinstate user dpm profile
436 * @smu: smu_context pointer
438 * Restore the saved user power configurations include power limit,
439 * clock frequencies, fan control mode and fan speed.
441 static void smu_restore_dpm_user_profile(struct smu_context *smu)
443 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
446 if (!smu->adev->in_suspend)
449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
452 /* Enable restore flag */
453 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
455 /* set the user dpm power limit */
456 if (smu->user_dpm_profile.power_limit) {
457 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
459 dev_err(smu->adev->dev, "Failed to set power limit value\n");
462 /* set the user dpm clock configurations */
463 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
464 enum smu_clk_type clk_type;
466 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
468 * Iterate over smu clk type and force the saved user clk
469 * configs, skip if clock dependency is enabled
471 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
472 smu->user_dpm_profile.clk_mask[clk_type]) {
473 ret = smu_force_smuclk_levels(smu, clk_type,
474 smu->user_dpm_profile.clk_mask[clk_type]);
476 dev_err(smu->adev->dev,
477 "Failed to set clock type = %d\n", clk_type);
482 /* set the user dpm fan configurations */
483 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
484 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
485 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
486 if (ret != -EOPNOTSUPP) {
487 smu->user_dpm_profile.fan_speed_pwm = 0;
488 smu->user_dpm_profile.fan_speed_rpm = 0;
489 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
490 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
493 if (smu->user_dpm_profile.fan_speed_pwm) {
494 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
495 if (ret != -EOPNOTSUPP)
496 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
499 if (smu->user_dpm_profile.fan_speed_rpm) {
500 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
501 if (ret != -EOPNOTSUPP)
502 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
506 /* Restore user customized OD settings */
507 if (smu->user_dpm_profile.user_od) {
508 if (smu->ppt_funcs->restore_user_od_settings) {
509 ret = smu->ppt_funcs->restore_user_od_settings(smu);
511 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
515 /* Disable restore flag */
516 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
519 static int smu_get_power_num_states(void *handle,
520 struct pp_states_info *state_info)
525 /* not support power state */
526 memset(state_info, 0, sizeof(struct pp_states_info));
527 state_info->nums = 1;
528 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
533 bool is_support_sw_smu(struct amdgpu_device *adev)
535 /* vega20 is 11.0.2, but it's supported via the powerplay code */
536 if (adev->asic_type == CHIP_VEGA20)
539 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0))
545 bool is_support_cclk_dpm(struct amdgpu_device *adev)
547 struct smu_context *smu = adev->powerplay.pp_handle;
549 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
556 static int smu_sys_get_pp_table(void *handle,
559 struct smu_context *smu = handle;
560 struct smu_table_context *smu_table = &smu->smu_table;
562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
565 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
568 if (smu_table->hardcode_pptable)
569 *table = smu_table->hardcode_pptable;
571 *table = smu_table->power_play_table;
573 return smu_table->power_play_table_size;
576 static int smu_sys_set_pp_table(void *handle,
580 struct smu_context *smu = handle;
581 struct smu_table_context *smu_table = &smu->smu_table;
582 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
588 if (header->usStructureSize != size) {
589 dev_err(smu->adev->dev, "pp table size not matched !\n");
593 if (!smu_table->hardcode_pptable) {
594 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
595 if (!smu_table->hardcode_pptable)
599 memcpy(smu_table->hardcode_pptable, buf, size);
600 smu_table->power_play_table = smu_table->hardcode_pptable;
601 smu_table->power_play_table_size = size;
604 * Special hw_fini action(for Navi1x, the DPMs disablement will be
605 * skipped) may be needed for custom pptable uploading.
607 smu->uploading_custom_pp_table = true;
609 ret = smu_reset(smu);
611 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
613 smu->uploading_custom_pp_table = false;
618 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
620 struct smu_feature *feature = &smu->smu_feature;
621 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
625 * With SCPM enabled, the allowed featuremasks setting(via
626 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
627 * That means there is no way to let PMFW knows the settings below.
628 * Thus, we just assume all the features are allowed under
631 if (smu->adev->scpm_enabled) {
632 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
636 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
638 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
643 bitmap_or(feature->allowed, feature->allowed,
644 (unsigned long *)allowed_feature_mask,
645 feature->feature_num);
650 static int smu_set_funcs(struct amdgpu_device *adev)
652 struct smu_context *smu = adev->powerplay.pp_handle;
654 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
655 smu->od_enabled = true;
657 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
658 case IP_VERSION(11, 0, 0):
659 case IP_VERSION(11, 0, 5):
660 case IP_VERSION(11, 0, 9):
661 navi10_set_ppt_funcs(smu);
663 case IP_VERSION(11, 0, 7):
664 case IP_VERSION(11, 0, 11):
665 case IP_VERSION(11, 0, 12):
666 case IP_VERSION(11, 0, 13):
667 sienna_cichlid_set_ppt_funcs(smu);
669 case IP_VERSION(12, 0, 0):
670 case IP_VERSION(12, 0, 1):
671 renoir_set_ppt_funcs(smu);
673 case IP_VERSION(11, 5, 0):
674 vangogh_set_ppt_funcs(smu);
676 case IP_VERSION(13, 0, 1):
677 case IP_VERSION(13, 0, 3):
678 case IP_VERSION(13, 0, 8):
679 yellow_carp_set_ppt_funcs(smu);
681 case IP_VERSION(13, 0, 4):
682 case IP_VERSION(13, 0, 11):
683 smu_v13_0_4_set_ppt_funcs(smu);
685 case IP_VERSION(13, 0, 5):
686 smu_v13_0_5_set_ppt_funcs(smu);
688 case IP_VERSION(11, 0, 8):
689 cyan_skillfish_set_ppt_funcs(smu);
691 case IP_VERSION(11, 0, 2):
692 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
693 arcturus_set_ppt_funcs(smu);
694 /* OD is not supported on Arcturus */
695 smu->od_enabled = false;
697 case IP_VERSION(13, 0, 2):
698 aldebaran_set_ppt_funcs(smu);
699 /* Enable pp_od_clk_voltage node */
700 smu->od_enabled = true;
702 case IP_VERSION(13, 0, 0):
703 case IP_VERSION(13, 0, 10):
704 smu_v13_0_0_set_ppt_funcs(smu);
706 case IP_VERSION(13, 0, 6):
707 smu_v13_0_6_set_ppt_funcs(smu);
708 /* Enable pp_od_clk_voltage node */
709 smu->od_enabled = true;
711 case IP_VERSION(13, 0, 7):
712 smu_v13_0_7_set_ppt_funcs(smu);
714 case IP_VERSION(14, 0, 0):
715 case IP_VERSION(14, 0, 1):
716 smu_v14_0_0_set_ppt_funcs(smu);
725 static int smu_early_init(void *handle)
727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
728 struct smu_context *smu;
731 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
736 smu->pm_enabled = !!amdgpu_dpm;
738 smu->smu_baco.state = SMU_BACO_STATE_NONE;
739 smu->smu_baco.platform_support = false;
740 smu->user_dpm_profile.fan_mode = -1;
742 mutex_init(&smu->message_lock);
744 adev->powerplay.pp_handle = smu;
745 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
747 r = smu_set_funcs(adev);
750 return smu_init_microcode(smu);
753 static int smu_set_default_dpm_table(struct smu_context *smu)
755 struct amdgpu_device *adev = smu->adev;
756 struct smu_power_context *smu_power = &smu->smu_power;
757 struct smu_power_gate *power_gate = &smu_power->power_gate;
758 int vcn_gate, jpeg_gate;
761 if (!smu->ppt_funcs->set_default_dpm_table)
764 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
765 vcn_gate = atomic_read(&power_gate->vcn_gated);
766 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
767 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
769 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
770 ret = smu_dpm_set_vcn_enable(smu, true);
775 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
776 ret = smu_dpm_set_jpeg_enable(smu, true);
781 ret = smu->ppt_funcs->set_default_dpm_table(smu);
783 dev_err(smu->adev->dev,
784 "Failed to setup default dpm clock tables!\n");
786 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
787 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
789 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
790 smu_dpm_set_vcn_enable(smu, !vcn_gate);
795 static int smu_apply_default_config_table_settings(struct smu_context *smu)
797 struct amdgpu_device *adev = smu->adev;
800 ret = smu_get_default_config_table_settings(smu,
801 &adev->pm.config_table);
805 return smu_set_config_table(smu, &adev->pm.config_table);
808 static int smu_late_init(void *handle)
810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
811 struct smu_context *smu = adev->powerplay.pp_handle;
814 smu_set_fine_grain_gfx_freq_parameters(smu);
816 if (!smu->pm_enabled)
819 ret = smu_post_init(smu);
821 dev_err(adev->dev, "Failed to post smu init!\n");
826 * Explicitly notify PMFW the power mode the system in. Since
827 * the PMFW may boot the ASIC with a different mode.
828 * For those supporting ACDC switch via gpio, PMFW will
829 * handle the switch automatically. Driver involvement
832 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
835 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) ||
836 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3)))
839 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
840 ret = smu_set_default_od_settings(smu);
842 dev_err(adev->dev, "Failed to setup default OD settings!\n");
847 ret = smu_populate_umd_state_clk(smu);
849 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
853 ret = smu_get_asic_power_limits(smu,
854 &smu->current_power_limit,
855 &smu->default_power_limit,
856 &smu->max_power_limit,
857 &smu->min_power_limit);
859 dev_err(adev->dev, "Failed to get asic power limits!\n");
863 if (!amdgpu_sriov_vf(adev))
864 smu_get_unique_id(smu);
866 smu_get_fan_parameters(smu);
869 smu->smu_dpm.dpm_level,
870 AMD_PP_TASK_COMPLETE_INIT);
872 ret = smu_apply_default_config_table_settings(smu);
873 if (ret && (ret != -EOPNOTSUPP)) {
874 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
878 smu_restore_dpm_user_profile(smu);
883 static int smu_init_fb_allocations(struct smu_context *smu)
885 struct amdgpu_device *adev = smu->adev;
886 struct smu_table_context *smu_table = &smu->smu_table;
887 struct smu_table *tables = smu_table->tables;
888 struct smu_table *driver_table = &(smu_table->driver_table);
889 uint32_t max_table_size = 0;
892 /* VRAM allocation for tool table */
893 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
894 ret = amdgpu_bo_create_kernel(adev,
895 tables[SMU_TABLE_PMSTATUSLOG].size,
896 tables[SMU_TABLE_PMSTATUSLOG].align,
897 tables[SMU_TABLE_PMSTATUSLOG].domain,
898 &tables[SMU_TABLE_PMSTATUSLOG].bo,
899 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
900 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
902 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
907 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT;
908 /* VRAM allocation for driver table */
909 for (i = 0; i < SMU_TABLE_COUNT; i++) {
910 if (tables[i].size == 0)
913 /* If one of the tables has VRAM domain restriction, keep it in
916 if ((tables[i].domain &
917 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) ==
918 AMDGPU_GEM_DOMAIN_VRAM)
919 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
921 if (i == SMU_TABLE_PMSTATUSLOG)
924 if (max_table_size < tables[i].size)
925 max_table_size = tables[i].size;
928 driver_table->size = max_table_size;
929 driver_table->align = PAGE_SIZE;
931 ret = amdgpu_bo_create_kernel(adev,
934 driver_table->domain,
936 &driver_table->mc_address,
937 &driver_table->cpu_addr);
939 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
940 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
941 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
942 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
943 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
949 static int smu_fini_fb_allocations(struct smu_context *smu)
951 struct smu_table_context *smu_table = &smu->smu_table;
952 struct smu_table *tables = smu_table->tables;
953 struct smu_table *driver_table = &(smu_table->driver_table);
955 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
956 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
957 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
958 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
960 amdgpu_bo_free_kernel(&driver_table->bo,
961 &driver_table->mc_address,
962 &driver_table->cpu_addr);
968 * smu_alloc_memory_pool - allocate memory pool in the system memory
970 * @smu: amdgpu_device pointer
972 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
973 * and DramLogSetDramAddr can notify it changed.
975 * Returns 0 on success, error on failure.
977 static int smu_alloc_memory_pool(struct smu_context *smu)
979 struct amdgpu_device *adev = smu->adev;
980 struct smu_table_context *smu_table = &smu->smu_table;
981 struct smu_table *memory_pool = &smu_table->memory_pool;
982 uint64_t pool_size = smu->pool_size;
985 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
988 memory_pool->size = pool_size;
989 memory_pool->align = PAGE_SIZE;
990 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
993 case SMU_MEMORY_POOL_SIZE_256_MB:
994 case SMU_MEMORY_POOL_SIZE_512_MB:
995 case SMU_MEMORY_POOL_SIZE_1_GB:
996 case SMU_MEMORY_POOL_SIZE_2_GB:
997 ret = amdgpu_bo_create_kernel(adev,
1000 memory_pool->domain,
1002 &memory_pool->mc_address,
1003 &memory_pool->cpu_addr);
1005 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
1014 static int smu_free_memory_pool(struct smu_context *smu)
1016 struct smu_table_context *smu_table = &smu->smu_table;
1017 struct smu_table *memory_pool = &smu_table->memory_pool;
1019 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1022 amdgpu_bo_free_kernel(&memory_pool->bo,
1023 &memory_pool->mc_address,
1024 &memory_pool->cpu_addr);
1026 memset(memory_pool, 0, sizeof(struct smu_table));
1031 static int smu_alloc_dummy_read_table(struct smu_context *smu)
1033 struct smu_table_context *smu_table = &smu->smu_table;
1034 struct smu_table *dummy_read_1_table =
1035 &smu_table->dummy_read_1_table;
1036 struct amdgpu_device *adev = smu->adev;
1039 if (!dummy_read_1_table->size)
1042 ret = amdgpu_bo_create_kernel(adev,
1043 dummy_read_1_table->size,
1044 dummy_read_1_table->align,
1045 dummy_read_1_table->domain,
1046 &dummy_read_1_table->bo,
1047 &dummy_read_1_table->mc_address,
1048 &dummy_read_1_table->cpu_addr);
1050 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
1055 static void smu_free_dummy_read_table(struct smu_context *smu)
1057 struct smu_table_context *smu_table = &smu->smu_table;
1058 struct smu_table *dummy_read_1_table =
1059 &smu_table->dummy_read_1_table;
1062 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
1063 &dummy_read_1_table->mc_address,
1064 &dummy_read_1_table->cpu_addr);
1066 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
1069 static int smu_smc_table_sw_init(struct smu_context *smu)
1074 * Create smu_table structure, and init smc tables such as
1075 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
1077 ret = smu_init_smc_tables(smu);
1079 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
1084 * Create smu_power_context structure, and allocate smu_dpm_context and
1085 * context size to fill the smu_power_context data.
1087 ret = smu_init_power(smu);
1089 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1094 * allocate vram bos to store smc table contents.
1096 ret = smu_init_fb_allocations(smu);
1100 ret = smu_alloc_memory_pool(smu);
1104 ret = smu_alloc_dummy_read_table(smu);
1108 ret = smu_i2c_init(smu);
1115 static int smu_smc_table_sw_fini(struct smu_context *smu)
1121 smu_free_dummy_read_table(smu);
1123 ret = smu_free_memory_pool(smu);
1127 ret = smu_fini_fb_allocations(smu);
1131 ret = smu_fini_power(smu);
1133 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1137 ret = smu_fini_smc_tables(smu);
1139 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1146 static void smu_throttling_logging_work_fn(struct work_struct *work)
1148 struct smu_context *smu = container_of(work, struct smu_context,
1149 throttling_logging_work);
1151 smu_log_thermal_throttling(smu);
1154 static void smu_interrupt_work_fn(struct work_struct *work)
1156 struct smu_context *smu = container_of(work, struct smu_context,
1159 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1160 smu->ppt_funcs->interrupt_work(smu);
1163 static void smu_swctf_delayed_work_handler(struct work_struct *work)
1165 struct smu_context *smu =
1166 container_of(work, struct smu_context, swctf_delayed_work.work);
1167 struct smu_temperature_range *range =
1168 &smu->thermal_range;
1169 struct amdgpu_device *adev = smu->adev;
1170 uint32_t hotspot_tmp, size;
1173 * If the hotspot temperature is confirmed as below SW CTF setting point
1174 * after the delay enforced, nothing will be done.
1175 * Otherwise, a graceful shutdown will be performed to prevent further damage.
1177 if (range->software_shutdown_temp &&
1178 smu->ppt_funcs->read_sensor &&
1179 !smu->ppt_funcs->read_sensor(smu,
1180 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1183 hotspot_tmp / 1000 < range->software_shutdown_temp)
1186 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1187 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1188 orderly_poweroff(true);
1191 static void smu_init_xgmi_plpd_mode(struct smu_context *smu)
1193 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1194 smu->plpd_mode = XGMI_PLPD_DEFAULT;
1198 /* PMFW put PLPD into default policy after enabling the feature */
1199 if (smu_feature_is_enabled(smu,
1200 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT))
1201 smu->plpd_mode = XGMI_PLPD_DEFAULT;
1203 smu->plpd_mode = XGMI_PLPD_NONE;
1206 static int smu_sw_init(void *handle)
1208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209 struct smu_context *smu = adev->powerplay.pp_handle;
1212 smu->pool_size = adev->pm.smu_prv_buffer_size;
1213 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1214 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1215 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1217 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1218 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1219 atomic64_set(&smu->throttle_int_counter, 0);
1220 smu->watermarks_bitmap = 0;
1221 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1222 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1224 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1225 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1226 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
1227 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
1229 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1230 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1231 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1232 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1233 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1234 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1235 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1236 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1238 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1239 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1240 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1241 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1242 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1243 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1244 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1245 smu->display_config = &adev->pm.pm_display_cfg;
1247 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1248 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1250 INIT_DELAYED_WORK(&smu->swctf_delayed_work,
1251 smu_swctf_delayed_work_handler);
1253 ret = smu_smc_table_sw_init(smu);
1255 dev_err(adev->dev, "Failed to sw init smc table!\n");
1259 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1260 ret = smu_get_vbios_bootup_values(smu);
1262 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1266 ret = smu_init_pptable_microcode(smu);
1268 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1272 ret = smu_register_irq_handler(smu);
1274 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1278 /* If there is no way to query fan control mode, fan control is not supported */
1279 if (!smu->ppt_funcs->get_fan_control_mode)
1280 smu->adev->pm.no_fan = true;
1285 static int smu_sw_fini(void *handle)
1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288 struct smu_context *smu = adev->powerplay.pp_handle;
1291 ret = smu_smc_table_sw_fini(smu);
1293 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1297 smu_fini_microcode(smu);
1302 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1304 struct amdgpu_device *adev = smu->adev;
1305 struct smu_temperature_range *range =
1306 &smu->thermal_range;
1309 if (!smu->ppt_funcs->get_thermal_temperature_range)
1312 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1316 adev->pm.dpm.thermal.min_temp = range->min;
1317 adev->pm.dpm.thermal.max_temp = range->max;
1318 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1319 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1320 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1321 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1322 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1323 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1324 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1330 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges
1332 * @smu: smu_context pointer
1334 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling.
1335 * Returns 0 on success, error on failure.
1337 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
1339 struct wbrf_ranges_in_out wbrf_exclusion = {0};
1340 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list;
1341 struct amdgpu_device *adev = smu->adev;
1342 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;
1343 uint64_t start, end;
1346 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion);
1348 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n");
1353 * The exclusion ranges array we got might be filled with holes and duplicate
1354 * entries. For example:
1355 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...}
1356 * We need to do some sortups to eliminate those holes and duplicate entries.
1357 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...}
1359 for (i = 0; i < num_of_wbrf_ranges; i++) {
1360 start = wifi_bands[i].start;
1361 end = wifi_bands[i].end;
1363 /* get the last valid entry to fill the intermediate hole */
1364 if (!start && !end) {
1365 for (j = num_of_wbrf_ranges - 1; j > i; j--)
1366 if (wifi_bands[j].start && wifi_bands[j].end)
1369 /* no valid entry left */
1373 start = wifi_bands[i].start = wifi_bands[j].start;
1374 end = wifi_bands[i].end = wifi_bands[j].end;
1375 wifi_bands[j].start = 0;
1376 wifi_bands[j].end = 0;
1377 num_of_wbrf_ranges = j;
1380 /* eliminate duplicate entries */
1381 for (j = i + 1; j < num_of_wbrf_ranges; j++) {
1382 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) {
1383 wifi_bands[j].start = 0;
1384 wifi_bands[j].end = 0;
1389 /* Send the sorted wifi_bands to PMFW */
1390 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1391 /* Try to set the wifi_bands again */
1392 if (unlikely(ret == -EBUSY)) {
1394 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1401 * smu_wbrf_event_handler - handle notify events
1403 * @nb: notifier block
1404 * @action: event type
1407 * Calls relevant amdgpu function in response to wbrf event
1408 * notification from kernel.
1410 static int smu_wbrf_event_handler(struct notifier_block *nb,
1411 unsigned long action, void *_arg)
1413 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier);
1417 schedule_delayed_work(&smu->wbrf_delayed_work,
1418 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1428 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired
1430 * @work: struct work_struct pointer
1432 * Flood is over and driver will consume the latest exclusion ranges.
1434 static void smu_wbrf_delayed_work_handler(struct work_struct *work)
1436 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work);
1438 smu_wbrf_handle_exclusion_ranges(smu);
1442 * smu_wbrf_support_check - check wbrf support
1444 * @smu: smu_context pointer
1446 * Verifies the ACPI interface whether wbrf is supported.
1448 static void smu_wbrf_support_check(struct smu_context *smu)
1450 struct amdgpu_device *adev = smu->adev;
1452 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf &&
1453 acpi_amd_wbrf_supported_consumer(adev->dev);
1455 if (smu->wbrf_supported)
1456 dev_info(adev->dev, "RF interference mitigation is supported\n");
1460 * smu_wbrf_init - init driver wbrf support
1462 * @smu: smu_context pointer
1464 * Verifies the AMD ACPI interfaces and registers with the wbrf
1465 * notifier chain if wbrf feature is supported.
1466 * Returns 0 on success, error on failure.
1468 static int smu_wbrf_init(struct smu_context *smu)
1472 if (!smu->wbrf_supported)
1475 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler);
1477 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler;
1478 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier);
1483 * Some wifiband exclusion ranges may be already there
1484 * before our driver loaded. To make sure our driver
1485 * is awared of those exclusion ranges.
1487 schedule_delayed_work(&smu->wbrf_delayed_work,
1488 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1494 * smu_wbrf_fini - tear down driver wbrf support
1496 * @smu: smu_context pointer
1498 * Unregisters with the wbrf notifier chain.
1500 static void smu_wbrf_fini(struct smu_context *smu)
1502 if (!smu->wbrf_supported)
1505 amd_wbrf_unregister_notifier(&smu->wbrf_notifier);
1507 cancel_delayed_work_sync(&smu->wbrf_delayed_work);
1510 static int smu_smc_hw_setup(struct smu_context *smu)
1512 struct smu_feature *feature = &smu->smu_feature;
1513 struct amdgpu_device *adev = smu->adev;
1514 uint8_t pcie_gen = 0, pcie_width = 0;
1515 uint64_t features_supported;
1518 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1519 case IP_VERSION(11, 0, 7):
1520 case IP_VERSION(11, 0, 11):
1521 case IP_VERSION(11, 5, 0):
1522 case IP_VERSION(11, 0, 12):
1523 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1524 dev_info(adev->dev, "dpm has been enabled\n");
1525 ret = smu_system_features_control(smu, true);
1527 dev_err(adev->dev, "Failed system features control!\n");
1535 ret = smu_init_display_count(smu, 0);
1537 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1541 ret = smu_set_driver_table_location(smu);
1543 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1548 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1550 ret = smu_set_tool_table_location(smu);
1552 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1557 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1560 ret = smu_notify_memory_pool_location(smu);
1562 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1567 * It is assumed the pptable used before runpm is same as
1568 * the one used afterwards. Thus, we can reuse the stored
1569 * copy and do not need to resetup the pptable again.
1571 if (!adev->in_runpm) {
1572 ret = smu_setup_pptable(smu);
1574 dev_err(adev->dev, "Failed to setup pptable!\n");
1579 /* smu_dump_pptable(smu); */
1582 * With SCPM enabled, PSP is responsible for the PPTable transferring
1583 * (to SMU). Driver involvement is not needed and permitted.
1585 if (!adev->scpm_enabled) {
1587 * Copy pptable bo in the vram to smc with SMU MSGs such as
1588 * SetDriverDramAddr and TransferTableDram2Smu.
1590 ret = smu_write_pptable(smu);
1592 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1597 /* issue Run*Btc msg */
1598 ret = smu_run_btc(smu);
1602 /* Enable UclkShadow on wbrf supported */
1603 if (smu->wbrf_supported) {
1604 ret = smu_enable_uclk_shadow(smu, true);
1606 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n");
1612 * With SCPM enabled, these actions(and relevant messages) are
1613 * not needed and permitted.
1615 if (!adev->scpm_enabled) {
1616 ret = smu_feature_set_allowed_mask(smu);
1618 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1623 ret = smu_system_features_control(smu, true);
1625 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1629 smu_init_xgmi_plpd_mode(smu);
1631 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1633 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1636 bitmap_copy(feature->supported,
1637 (unsigned long *)&features_supported,
1638 feature->feature_num);
1640 if (!smu_is_dpm_running(smu))
1641 dev_info(adev->dev, "dpm has been disabled\n");
1644 * Set initialized values (get from vbios) to dpm tables context such as
1645 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1648 ret = smu_set_default_dpm_table(smu);
1650 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1654 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1656 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1658 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1660 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1663 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1664 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1665 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1667 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1669 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1671 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1673 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1675 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1677 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1679 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1681 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1685 ret = smu_get_thermal_temperature_range(smu);
1687 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1691 ret = smu_enable_thermal_alert(smu);
1693 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1697 ret = smu_notify_display_change(smu);
1699 dev_err(adev->dev, "Failed to notify display change!\n");
1704 * Set min deep sleep dce fclk with bootup value from vbios via
1705 * SetMinDeepSleepDcefclk MSG.
1707 ret = smu_set_min_dcef_deep_sleep(smu,
1708 smu->smu_table.boot_values.dcefclk / 100);
1710 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n");
1714 /* Init wbrf support. Properly setup the notifier */
1715 ret = smu_wbrf_init(smu);
1717 dev_err(adev->dev, "Error during wbrf init call\n");
1722 static int smu_start_smc_engine(struct smu_context *smu)
1724 struct amdgpu_device *adev = smu->adev;
1727 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1728 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) {
1729 if (smu->ppt_funcs->load_microcode) {
1730 ret = smu->ppt_funcs->load_microcode(smu);
1737 if (smu->ppt_funcs->check_fw_status) {
1738 ret = smu->ppt_funcs->check_fw_status(smu);
1740 dev_err(adev->dev, "SMC is not ready\n");
1746 * Send msg GetDriverIfVersion to check if the return value is equal
1747 * with DRIVER_IF_VERSION of smc header.
1749 ret = smu_check_fw_version(smu);
1756 static int smu_hw_init(void *handle)
1759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1760 struct smu_context *smu = adev->powerplay.pp_handle;
1762 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1763 smu->pm_enabled = false;
1767 ret = smu_start_smc_engine(smu);
1769 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1774 * Check whether wbrf is supported. This needs to be done
1775 * before SMU setup starts since part of SMU configuration
1778 smu_wbrf_support_check(smu);
1781 ret = smu_set_gfx_imu_enable(smu);
1784 smu_dpm_set_vcn_enable(smu, true);
1785 smu_dpm_set_jpeg_enable(smu, true);
1786 smu_dpm_set_vpe_enable(smu, true);
1787 smu_dpm_set_umsch_mm_enable(smu, true);
1788 smu_set_gfx_cgpg(smu, true);
1791 if (!smu->pm_enabled)
1794 ret = smu_get_driver_allowed_feature_mask(smu);
1798 ret = smu_smc_hw_setup(smu);
1800 dev_err(adev->dev, "Failed to setup smc hw!\n");
1805 * Move maximum sustainable clock retrieving here considering
1806 * 1. It is not needed on resume(from S3).
1807 * 2. DAL settings come between .hw_init and .late_init of SMU.
1808 * And DAL needs to know the maximum sustainable clocks. Thus
1809 * it cannot be put in .late_init().
1811 ret = smu_init_max_sustainable_clocks(smu);
1813 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1817 adev->pm.dpm_enabled = true;
1819 dev_info(adev->dev, "SMU is initialized successfully!\n");
1824 static int smu_disable_dpms(struct smu_context *smu)
1826 struct amdgpu_device *adev = smu->adev;
1828 bool use_baco = !smu->is_apu &&
1829 ((amdgpu_in_reset(adev) &&
1830 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1831 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1834 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1835 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1837 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1838 case IP_VERSION(13, 0, 0):
1839 case IP_VERSION(13, 0, 7):
1840 case IP_VERSION(13, 0, 10):
1847 * For custom pptable uploading, skip the DPM features
1848 * disable process on Navi1x ASICs.
1849 * - As the gfx related features are under control of
1850 * RLC on those ASICs. RLC reinitialization will be
1851 * needed to reenable them. That will cost much more
1854 * - SMU firmware can handle the DPM reenablement
1857 if (smu->uploading_custom_pp_table) {
1858 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1859 case IP_VERSION(11, 0, 0):
1860 case IP_VERSION(11, 0, 5):
1861 case IP_VERSION(11, 0, 9):
1862 case IP_VERSION(11, 0, 7):
1863 case IP_VERSION(11, 0, 11):
1864 case IP_VERSION(11, 5, 0):
1865 case IP_VERSION(11, 0, 12):
1866 case IP_VERSION(11, 0, 13):
1874 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1875 * on BACO in. Driver involvement is unnecessary.
1878 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1879 case IP_VERSION(11, 0, 7):
1880 case IP_VERSION(11, 0, 0):
1881 case IP_VERSION(11, 0, 5):
1882 case IP_VERSION(11, 0, 9):
1883 case IP_VERSION(13, 0, 7):
1891 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly
1892 * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
1894 if (amdgpu_in_reset(adev) || adev->in_s0ix) {
1895 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1896 case IP_VERSION(13, 0, 4):
1897 case IP_VERSION(13, 0, 11):
1898 case IP_VERSION(14, 0, 0):
1899 case IP_VERSION(14, 0, 1):
1907 * For gpu reset, runpm and hibernation through BACO,
1908 * BACO feature has to be kept enabled.
1910 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1911 ret = smu_disable_all_features_with_exception(smu,
1912 SMU_FEATURE_BACO_BIT);
1914 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1916 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1917 if (!adev->scpm_enabled) {
1918 ret = smu_system_features_control(smu, false);
1920 dev_err(adev->dev, "Failed to disable smu features.\n");
1924 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction.
1925 * otherwise SMU will hang while interacting with RLC if RLC is halted
1926 * this is a WA for Vangogh asic which fix the SMU hang issue.
1928 ret = smu_notify_rlc_state(smu, false);
1930 dev_err(adev->dev, "Fail to notify rlc status!\n");
1934 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&
1935 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&
1936 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
1937 adev->gfx.rlc.funcs->stop(adev);
1942 static int smu_smc_hw_cleanup(struct smu_context *smu)
1944 struct amdgpu_device *adev = smu->adev;
1949 cancel_work_sync(&smu->throttling_logging_work);
1950 cancel_work_sync(&smu->interrupt_work);
1952 ret = smu_disable_thermal_alert(smu);
1954 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1958 cancel_delayed_work_sync(&smu->swctf_delayed_work);
1960 ret = smu_disable_dpms(smu);
1962 dev_err(adev->dev, "Fail to disable dpm features!\n");
1969 static int smu_reset_mp1_state(struct smu_context *smu)
1971 struct amdgpu_device *adev = smu->adev;
1974 if ((!adev->in_runpm) && (!adev->in_suspend) &&
1975 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1976 IP_VERSION(13, 0, 10) &&
1977 !amdgpu_device_has_display_hardware(adev))
1978 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
1983 static int smu_hw_fini(void *handle)
1985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1986 struct smu_context *smu = adev->powerplay.pp_handle;
1989 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1992 smu_dpm_set_vcn_enable(smu, false);
1993 smu_dpm_set_jpeg_enable(smu, false);
1994 smu_dpm_set_vpe_enable(smu, false);
1995 smu_dpm_set_umsch_mm_enable(smu, false);
1997 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1998 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
2000 if (!smu->pm_enabled)
2003 adev->pm.dpm_enabled = false;
2005 ret = smu_smc_hw_cleanup(smu);
2009 ret = smu_reset_mp1_state(smu);
2016 static void smu_late_fini(void *handle)
2018 struct amdgpu_device *adev = handle;
2019 struct smu_context *smu = adev->powerplay.pp_handle;
2024 static int smu_reset(struct smu_context *smu)
2026 struct amdgpu_device *adev = smu->adev;
2029 ret = smu_hw_fini(adev);
2033 ret = smu_hw_init(adev);
2037 ret = smu_late_init(adev);
2044 static int smu_suspend(void *handle)
2046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2047 struct smu_context *smu = adev->powerplay.pp_handle;
2051 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2054 if (!smu->pm_enabled)
2057 adev->pm.dpm_enabled = false;
2059 ret = smu_smc_hw_cleanup(smu);
2063 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
2065 smu_set_gfx_cgpg(smu, false);
2068 * pwfw resets entrycount when device is suspended, so we save the
2069 * last value to be used when we resume to keep it consistent
2071 ret = smu_get_entrycount_gfxoff(smu, &count);
2073 adev->gfx.gfx_off_entrycount = count;
2078 static int smu_resume(void *handle)
2081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2082 struct smu_context *smu = adev->powerplay.pp_handle;
2084 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
2087 if (!smu->pm_enabled)
2090 dev_info(adev->dev, "SMU is resuming...\n");
2092 ret = smu_start_smc_engine(smu);
2094 dev_err(adev->dev, "SMC engine is not correctly up!\n");
2098 ret = smu_smc_hw_setup(smu);
2100 dev_err(adev->dev, "Failed to setup smc hw!\n");
2104 ret = smu_set_gfx_imu_enable(smu);
2108 smu_set_gfx_cgpg(smu, true);
2110 smu->disable_uclk_switch = 0;
2112 adev->pm.dpm_enabled = true;
2114 dev_info(adev->dev, "SMU is resumed successfully!\n");
2119 static int smu_display_configuration_change(void *handle,
2120 const struct amd_pp_display_configuration *display_config)
2122 struct smu_context *smu = handle;
2124 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2127 if (!display_config)
2130 smu_set_min_dcef_deep_sleep(smu,
2131 display_config->min_dcef_deep_sleep_set_clk / 100);
2136 static int smu_set_clockgating_state(void *handle,
2137 enum amd_clockgating_state state)
2142 static int smu_set_powergating_state(void *handle,
2143 enum amd_powergating_state state)
2148 static int smu_enable_umd_pstate(void *handle,
2149 enum amd_dpm_forced_level *level)
2151 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
2152 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
2153 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
2154 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
2156 struct smu_context *smu = (struct smu_context*)(handle);
2157 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2159 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2162 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
2163 /* enter umd pstate, save current level, disable gfx cg*/
2164 if (*level & profile_mode_mask) {
2165 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
2166 smu_gpo_control(smu, false);
2167 smu_gfx_ulv_control(smu, false);
2168 smu_deep_sleep_control(smu, false);
2169 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
2172 /* exit umd pstate, restore level, enable gfx cg*/
2173 if (!(*level & profile_mode_mask)) {
2174 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
2175 *level = smu_dpm_ctx->saved_dpm_level;
2176 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
2177 smu_deep_sleep_control(smu, true);
2178 smu_gfx_ulv_control(smu, true);
2179 smu_gpo_control(smu, true);
2186 static int smu_bump_power_profile_mode(struct smu_context *smu,
2188 uint32_t param_size)
2192 if (smu->ppt_funcs->set_power_profile_mode)
2193 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2198 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
2199 enum amd_dpm_forced_level level,
2200 bool skip_display_settings)
2205 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2207 if (!skip_display_settings) {
2208 ret = smu_display_config_changed(smu);
2210 dev_err(smu->adev->dev, "Failed to change display config!");
2215 ret = smu_apply_clocks_adjust_rules(smu);
2217 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
2221 if (!skip_display_settings) {
2222 ret = smu_notify_smc_display_config(smu);
2224 dev_err(smu->adev->dev, "Failed to notify smc display config!");
2229 if (smu_dpm_ctx->dpm_level != level) {
2230 ret = smu_asic_set_performance_level(smu, level);
2232 dev_err(smu->adev->dev, "Failed to set performance level!");
2236 /* update the saved copy */
2237 smu_dpm_ctx->dpm_level = level;
2240 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2241 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2242 index = fls(smu->workload_mask);
2243 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2244 workload = smu->workload_setting[index];
2246 if (smu->power_profile_mode != workload)
2247 smu_bump_power_profile_mode(smu, &workload, 0);
2253 static int smu_handle_task(struct smu_context *smu,
2254 enum amd_dpm_forced_level level,
2255 enum amd_pp_task task_id)
2259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2263 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
2264 ret = smu_pre_display_config_changed(smu);
2267 ret = smu_adjust_power_state_dynamic(smu, level, false);
2269 case AMD_PP_TASK_COMPLETE_INIT:
2270 case AMD_PP_TASK_READJUST_POWER_STATE:
2271 ret = smu_adjust_power_state_dynamic(smu, level, true);
2280 static int smu_handle_dpm_task(void *handle,
2281 enum amd_pp_task task_id,
2282 enum amd_pm_state_type *user_state)
2284 struct smu_context *smu = handle;
2285 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2287 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
2291 static int smu_switch_power_profile(void *handle,
2292 enum PP_SMC_POWER_PROFILE type,
2295 struct smu_context *smu = handle;
2296 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2300 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2303 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
2307 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
2308 index = fls(smu->workload_mask);
2309 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2310 workload = smu->workload_setting[index];
2312 smu->workload_mask |= (1 << smu->workload_prority[type]);
2313 index = fls(smu->workload_mask);
2314 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2315 workload = smu->workload_setting[index];
2318 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2319 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2320 smu_bump_power_profile_mode(smu, &workload, 0);
2325 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
2327 struct smu_context *smu = handle;
2328 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2330 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2333 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2336 return smu_dpm_ctx->dpm_level;
2339 static int smu_force_performance_level(void *handle,
2340 enum amd_dpm_forced_level level)
2342 struct smu_context *smu = handle;
2343 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2346 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2349 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2352 ret = smu_enable_umd_pstate(smu, &level);
2356 ret = smu_handle_task(smu, level,
2357 AMD_PP_TASK_READJUST_POWER_STATE);
2359 /* reset user dpm clock state */
2360 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2361 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
2362 smu->user_dpm_profile.clk_dependency = 0;
2368 static int smu_set_display_count(void *handle, uint32_t count)
2370 struct smu_context *smu = handle;
2372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2375 return smu_init_display_count(smu, count);
2378 static int smu_force_smuclk_levels(struct smu_context *smu,
2379 enum smu_clk_type clk_type,
2382 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2385 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2388 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2389 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
2393 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
2394 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
2395 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2396 smu->user_dpm_profile.clk_mask[clk_type] = mask;
2397 smu_set_user_clk_dependencies(smu, clk_type);
2404 static int smu_force_ppclk_levels(void *handle,
2405 enum pp_clock_type type,
2408 struct smu_context *smu = handle;
2409 enum smu_clk_type clk_type;
2413 clk_type = SMU_SCLK; break;
2415 clk_type = SMU_MCLK; break;
2417 clk_type = SMU_PCIE; break;
2419 clk_type = SMU_SOCCLK; break;
2421 clk_type = SMU_FCLK; break;
2423 clk_type = SMU_DCEFCLK; break;
2425 clk_type = SMU_VCLK; break;
2427 clk_type = SMU_VCLK1; break;
2429 clk_type = SMU_DCLK; break;
2431 clk_type = SMU_DCLK1; break;
2433 clk_type = SMU_OD_SCLK; break;
2435 clk_type = SMU_OD_MCLK; break;
2437 clk_type = SMU_OD_VDDC_CURVE; break;
2439 clk_type = SMU_OD_RANGE; break;
2444 return smu_force_smuclk_levels(smu, clk_type, mask);
2448 * On system suspending or resetting, the dpm_enabled
2449 * flag will be cleared. So that those SMU services which
2450 * are not supported will be gated.
2451 * However, the mp1 state setting should still be granted
2452 * even if the dpm_enabled cleared.
2454 static int smu_set_mp1_state(void *handle,
2455 enum pp_mp1_state mp1_state)
2457 struct smu_context *smu = handle;
2460 if (!smu->pm_enabled)
2463 if (smu->ppt_funcs &&
2464 smu->ppt_funcs->set_mp1_state)
2465 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2470 static int smu_set_df_cstate(void *handle,
2471 enum pp_df_cstate state)
2473 struct smu_context *smu = handle;
2476 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2479 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2482 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2484 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2489 int smu_write_watermarks_table(struct smu_context *smu)
2491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2494 return smu_set_watermarks_table(smu, NULL);
2497 static int smu_set_watermarks_for_clock_ranges(void *handle,
2498 struct pp_smu_wm_range_sets *clock_ranges)
2500 struct smu_context *smu = handle;
2502 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2505 if (smu->disable_watermark)
2508 return smu_set_watermarks_table(smu, clock_ranges);
2511 int smu_set_ac_dc(struct smu_context *smu)
2515 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2518 /* controlled by firmware */
2519 if (smu->dc_controlled_by_gpio)
2522 ret = smu_set_power_source(smu,
2523 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2524 SMU_POWER_SOURCE_DC);
2526 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2527 smu->adev->pm.ac_power ? "AC" : "DC");
2532 const struct amd_ip_funcs smu_ip_funcs = {
2534 .early_init = smu_early_init,
2535 .late_init = smu_late_init,
2536 .sw_init = smu_sw_init,
2537 .sw_fini = smu_sw_fini,
2538 .hw_init = smu_hw_init,
2539 .hw_fini = smu_hw_fini,
2540 .late_fini = smu_late_fini,
2541 .suspend = smu_suspend,
2542 .resume = smu_resume,
2544 .check_soft_reset = NULL,
2545 .wait_for_idle = NULL,
2547 .set_clockgating_state = smu_set_clockgating_state,
2548 .set_powergating_state = smu_set_powergating_state,
2551 const struct amdgpu_ip_block_version smu_v11_0_ip_block = {
2552 .type = AMD_IP_BLOCK_TYPE_SMC,
2556 .funcs = &smu_ip_funcs,
2559 const struct amdgpu_ip_block_version smu_v12_0_ip_block = {
2560 .type = AMD_IP_BLOCK_TYPE_SMC,
2564 .funcs = &smu_ip_funcs,
2567 const struct amdgpu_ip_block_version smu_v13_0_ip_block = {
2568 .type = AMD_IP_BLOCK_TYPE_SMC,
2572 .funcs = &smu_ip_funcs,
2575 const struct amdgpu_ip_block_version smu_v14_0_ip_block = {
2576 .type = AMD_IP_BLOCK_TYPE_SMC,
2580 .funcs = &smu_ip_funcs,
2583 static int smu_load_microcode(void *handle)
2585 struct smu_context *smu = handle;
2586 struct amdgpu_device *adev = smu->adev;
2589 if (!smu->pm_enabled)
2592 /* This should be used for non PSP loading */
2593 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2596 if (smu->ppt_funcs->load_microcode) {
2597 ret = smu->ppt_funcs->load_microcode(smu);
2599 dev_err(adev->dev, "Load microcode failed\n");
2604 if (smu->ppt_funcs->check_fw_status) {
2605 ret = smu->ppt_funcs->check_fw_status(smu);
2607 dev_err(adev->dev, "SMC is not ready\n");
2615 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2619 if (smu->ppt_funcs->set_gfx_cgpg)
2620 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2625 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2627 struct smu_context *smu = handle;
2630 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2633 if (!smu->ppt_funcs->set_fan_speed_rpm)
2636 if (speed == U32_MAX)
2639 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2640 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2641 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2642 smu->user_dpm_profile.fan_speed_rpm = speed;
2644 /* Override custom PWM setting as they cannot co-exist */
2645 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2646 smu->user_dpm_profile.fan_speed_pwm = 0;
2653 * smu_get_power_limit - Request one of the SMU Power Limits
2655 * @handle: pointer to smu context
2656 * @limit: requested limit is written back to this variable
2657 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2658 * @pp_power_type: &pp_power_type type of power
2659 * Return: 0 on success, <0 on error
2662 int smu_get_power_limit(void *handle,
2664 enum pp_power_limit_level pp_limit_level,
2665 enum pp_power_type pp_power_type)
2667 struct smu_context *smu = handle;
2668 struct amdgpu_device *adev = smu->adev;
2669 enum smu_ppt_limit_level limit_level;
2670 uint32_t limit_type;
2673 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2676 switch (pp_power_type) {
2677 case PP_PWR_TYPE_SUSTAINED:
2678 limit_type = SMU_DEFAULT_PPT_LIMIT;
2680 case PP_PWR_TYPE_FAST:
2681 limit_type = SMU_FAST_PPT_LIMIT;
2687 switch (pp_limit_level) {
2688 case PP_PWR_LIMIT_CURRENT:
2689 limit_level = SMU_PPT_LIMIT_CURRENT;
2691 case PP_PWR_LIMIT_DEFAULT:
2692 limit_level = SMU_PPT_LIMIT_DEFAULT;
2694 case PP_PWR_LIMIT_MAX:
2695 limit_level = SMU_PPT_LIMIT_MAX;
2697 case PP_PWR_LIMIT_MIN:
2698 limit_level = SMU_PPT_LIMIT_MIN;
2704 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2705 if (smu->ppt_funcs->get_ppt_limit)
2706 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2708 switch (limit_level) {
2709 case SMU_PPT_LIMIT_CURRENT:
2710 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2711 case IP_VERSION(13, 0, 2):
2712 case IP_VERSION(13, 0, 6):
2713 case IP_VERSION(11, 0, 7):
2714 case IP_VERSION(11, 0, 11):
2715 case IP_VERSION(11, 0, 12):
2716 case IP_VERSION(11, 0, 13):
2717 ret = smu_get_asic_power_limits(smu,
2718 &smu->current_power_limit,
2724 *limit = smu->current_power_limit;
2726 case SMU_PPT_LIMIT_DEFAULT:
2727 *limit = smu->default_power_limit;
2729 case SMU_PPT_LIMIT_MAX:
2730 *limit = smu->max_power_limit;
2732 case SMU_PPT_LIMIT_MIN:
2733 *limit = smu->min_power_limit;
2743 static int smu_set_power_limit(void *handle, uint32_t limit)
2745 struct smu_context *smu = handle;
2746 uint32_t limit_type = limit >> 24;
2749 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2753 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2754 if (smu->ppt_funcs->set_power_limit)
2755 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2757 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) {
2758 dev_err(smu->adev->dev,
2759 "New power limit (%d) is out of range [%d,%d]\n",
2760 limit, smu->min_power_limit, smu->max_power_limit);
2765 limit = smu->current_power_limit;
2767 if (smu->ppt_funcs->set_power_limit) {
2768 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2769 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2770 smu->user_dpm_profile.power_limit = limit;
2776 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2780 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2783 if (smu->ppt_funcs->print_clk_levels)
2784 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2789 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2791 enum smu_clk_type clk_type;
2795 clk_type = SMU_SCLK; break;
2797 clk_type = SMU_MCLK; break;
2799 clk_type = SMU_PCIE; break;
2801 clk_type = SMU_SOCCLK; break;
2803 clk_type = SMU_FCLK; break;
2805 clk_type = SMU_DCEFCLK; break;
2807 clk_type = SMU_VCLK; break;
2809 clk_type = SMU_VCLK1; break;
2811 clk_type = SMU_DCLK; break;
2813 clk_type = SMU_DCLK1; break;
2815 clk_type = SMU_OD_SCLK; break;
2817 clk_type = SMU_OD_MCLK; break;
2819 clk_type = SMU_OD_VDDC_CURVE; break;
2821 clk_type = SMU_OD_RANGE; break;
2822 case OD_VDDGFX_OFFSET:
2823 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2825 clk_type = SMU_OD_CCLK; break;
2827 clk_type = SMU_OD_FAN_CURVE; break;
2828 case OD_ACOUSTIC_LIMIT:
2829 clk_type = SMU_OD_ACOUSTIC_LIMIT; break;
2830 case OD_ACOUSTIC_TARGET:
2831 clk_type = SMU_OD_ACOUSTIC_TARGET; break;
2832 case OD_FAN_TARGET_TEMPERATURE:
2833 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break;
2834 case OD_FAN_MINIMUM_PWM:
2835 clk_type = SMU_OD_FAN_MINIMUM_PWM; break;
2837 clk_type = SMU_CLK_COUNT; break;
2843 static int smu_print_ppclk_levels(void *handle,
2844 enum pp_clock_type type,
2847 struct smu_context *smu = handle;
2848 enum smu_clk_type clk_type;
2850 clk_type = smu_convert_to_smuclk(type);
2851 if (clk_type == SMU_CLK_COUNT)
2854 return smu_print_smuclk_levels(smu, clk_type, buf);
2857 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2859 struct smu_context *smu = handle;
2860 enum smu_clk_type clk_type;
2862 clk_type = smu_convert_to_smuclk(type);
2863 if (clk_type == SMU_CLK_COUNT)
2866 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2869 if (!smu->ppt_funcs->emit_clk_levels)
2872 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2876 static int smu_od_edit_dpm_table(void *handle,
2877 enum PP_OD_DPM_TABLE_COMMAND type,
2878 long *input, uint32_t size)
2880 struct smu_context *smu = handle;
2883 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2886 if (smu->ppt_funcs->od_edit_dpm_table) {
2887 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2893 static int smu_read_sensor(void *handle,
2898 struct smu_context *smu = handle;
2899 struct smu_umd_pstate_table *pstate_table =
2902 uint32_t *size, size_val;
2904 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2907 if (!data || !size_arg)
2910 size_val = *size_arg;
2913 if (smu->ppt_funcs->read_sensor)
2914 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2918 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2919 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2922 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2923 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2926 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
2927 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
2930 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
2931 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
2934 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2935 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2938 case AMDGPU_PP_SENSOR_UVD_POWER:
2939 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2942 case AMDGPU_PP_SENSOR_VCE_POWER:
2943 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2946 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2947 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
2950 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2951 *(uint32_t *)data = 0;
2961 // assign uint32_t to int
2962 *size_arg = size_val;
2967 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)
2969 int ret = -EOPNOTSUPP;
2970 struct smu_context *smu = handle;
2972 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit)
2973 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit);
2978 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)
2980 int ret = -EOPNOTSUPP;
2981 struct smu_context *smu = handle;
2983 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)
2984 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit);
2989 static int smu_get_power_profile_mode(void *handle, char *buf)
2991 struct smu_context *smu = handle;
2993 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2994 !smu->ppt_funcs->get_power_profile_mode)
2999 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
3002 static int smu_set_power_profile_mode(void *handle,
3004 uint32_t param_size)
3006 struct smu_context *smu = handle;
3008 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3009 !smu->ppt_funcs->set_power_profile_mode)
3012 return smu_bump_power_profile_mode(smu, param, param_size);
3015 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
3017 struct smu_context *smu = handle;
3019 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3022 if (!smu->ppt_funcs->get_fan_control_mode)
3028 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
3033 static int smu_set_fan_control_mode(void *handle, u32 value)
3035 struct smu_context *smu = handle;
3038 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3041 if (!smu->ppt_funcs->set_fan_control_mode)
3044 if (value == U32_MAX)
3047 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
3051 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3052 smu->user_dpm_profile.fan_mode = value;
3054 /* reset user dpm fan speed */
3055 if (value != AMD_FAN_CTRL_MANUAL) {
3056 smu->user_dpm_profile.fan_speed_pwm = 0;
3057 smu->user_dpm_profile.fan_speed_rpm = 0;
3058 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
3066 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
3068 struct smu_context *smu = handle;
3071 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3074 if (!smu->ppt_funcs->get_fan_speed_pwm)
3080 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
3085 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
3087 struct smu_context *smu = handle;
3090 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3093 if (!smu->ppt_funcs->set_fan_speed_pwm)
3096 if (speed == U32_MAX)
3099 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
3100 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3101 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
3102 smu->user_dpm_profile.fan_speed_pwm = speed;
3104 /* Override custom RPM setting as they cannot co-exist */
3105 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
3106 smu->user_dpm_profile.fan_speed_rpm = 0;
3112 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
3114 struct smu_context *smu = handle;
3117 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3120 if (!smu->ppt_funcs->get_fan_speed_rpm)
3126 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
3131 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
3133 struct smu_context *smu = handle;
3135 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3138 return smu_set_min_dcef_deep_sleep(smu, clk);
3141 static int smu_get_clock_by_type_with_latency(void *handle,
3142 enum amd_pp_clock_type type,
3143 struct pp_clock_levels_with_latency *clocks)
3145 struct smu_context *smu = handle;
3146 enum smu_clk_type clk_type;
3149 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3152 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
3154 case amd_pp_sys_clock:
3155 clk_type = SMU_GFXCLK;
3157 case amd_pp_mem_clock:
3158 clk_type = SMU_MCLK;
3160 case amd_pp_dcef_clock:
3161 clk_type = SMU_DCEFCLK;
3163 case amd_pp_disp_clock:
3164 clk_type = SMU_DISPCLK;
3167 dev_err(smu->adev->dev, "Invalid clock type!\n");
3171 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
3177 static int smu_display_clock_voltage_request(void *handle,
3178 struct pp_display_clock_request *clock_req)
3180 struct smu_context *smu = handle;
3183 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3186 if (smu->ppt_funcs->display_clock_voltage_request)
3187 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
3193 static int smu_display_disable_memory_clock_switch(void *handle,
3194 bool disable_memory_clock_switch)
3196 struct smu_context *smu = handle;
3199 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3202 if (smu->ppt_funcs->display_disable_memory_clock_switch)
3203 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
3208 static int smu_set_xgmi_pstate(void *handle,
3211 struct smu_context *smu = handle;
3214 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3217 if (smu->ppt_funcs->set_xgmi_pstate)
3218 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
3221 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
3226 static bool smu_get_baco_capability(void *handle)
3228 struct smu_context *smu = handle;
3230 if (!smu->pm_enabled)
3233 if (!smu->ppt_funcs || !smu->ppt_funcs->baco_is_support)
3236 return smu->ppt_funcs->baco_is_support(smu);
3239 static int smu_baco_set_state(void *handle, int state)
3241 struct smu_context *smu = handle;
3244 if (!smu->pm_enabled)
3248 if (smu->ppt_funcs->baco_exit)
3249 ret = smu->ppt_funcs->baco_exit(smu);
3250 } else if (state == 1) {
3251 if (smu->ppt_funcs->baco_enter)
3252 ret = smu->ppt_funcs->baco_enter(smu);
3258 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
3259 (state)?"enter":"exit");
3264 bool smu_mode1_reset_is_support(struct smu_context *smu)
3268 if (!smu->pm_enabled)
3271 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
3272 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
3277 bool smu_mode2_reset_is_support(struct smu_context *smu)
3281 if (!smu->pm_enabled)
3284 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
3285 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
3290 int smu_mode1_reset(struct smu_context *smu)
3294 if (!smu->pm_enabled)
3297 if (smu->ppt_funcs->mode1_reset)
3298 ret = smu->ppt_funcs->mode1_reset(smu);
3303 static int smu_mode2_reset(void *handle)
3305 struct smu_context *smu = handle;
3308 if (!smu->pm_enabled)
3311 if (smu->ppt_funcs->mode2_reset)
3312 ret = smu->ppt_funcs->mode2_reset(smu);
3315 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
3320 static int smu_enable_gfx_features(void *handle)
3322 struct smu_context *smu = handle;
3325 if (!smu->pm_enabled)
3328 if (smu->ppt_funcs->enable_gfx_features)
3329 ret = smu->ppt_funcs->enable_gfx_features(smu);
3332 dev_err(smu->adev->dev, "enable gfx features failed!\n");
3337 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
3338 struct pp_smu_nv_clock_table *max_clocks)
3340 struct smu_context *smu = handle;
3343 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3346 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
3347 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
3352 static int smu_get_uclk_dpm_states(void *handle,
3353 unsigned int *clock_values_in_khz,
3354 unsigned int *num_states)
3356 struct smu_context *smu = handle;
3359 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3362 if (smu->ppt_funcs->get_uclk_dpm_states)
3363 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
3368 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
3370 struct smu_context *smu = handle;
3371 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
3373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3376 if (smu->ppt_funcs->get_current_power_state)
3377 pm_state = smu->ppt_funcs->get_current_power_state(smu);
3382 static int smu_get_dpm_clock_table(void *handle,
3383 struct dpm_clocks *clock_table)
3385 struct smu_context *smu = handle;
3388 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3391 if (smu->ppt_funcs->get_dpm_clock_table)
3392 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3397 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3399 struct smu_context *smu = handle;
3401 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3404 if (!smu->ppt_funcs->get_gpu_metrics)
3407 return smu->ppt_funcs->get_gpu_metrics(smu, table);
3410 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics,
3413 struct smu_context *smu = handle;
3415 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3418 if (!smu->ppt_funcs->get_pm_metrics)
3421 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size);
3424 static int smu_enable_mgpu_fan_boost(void *handle)
3426 struct smu_context *smu = handle;
3429 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3432 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3433 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3438 static int smu_gfx_state_change_set(void *handle,
3441 struct smu_context *smu = handle;
3444 if (smu->ppt_funcs->gfx_state_change_set)
3445 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3450 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
3454 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3455 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
3460 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
3462 int ret = -EOPNOTSUPP;
3464 if (smu->ppt_funcs &&
3465 smu->ppt_funcs->get_ecc_info)
3466 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3472 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3474 struct smu_context *smu = handle;
3475 struct smu_table_context *smu_table = &smu->smu_table;
3476 struct smu_table *memory_pool = &smu_table->memory_pool;
3483 if (memory_pool->bo) {
3484 *addr = memory_pool->cpu_addr;
3485 *size = memory_pool->size;
3491 int smu_set_xgmi_plpd_mode(struct smu_context *smu,
3492 enum pp_xgmi_plpd_mode mode)
3494 int ret = -EOPNOTSUPP;
3496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3499 /* PLPD policy is not supported if it's NONE */
3500 if (smu->plpd_mode == XGMI_PLPD_NONE)
3503 if (smu->plpd_mode == mode)
3506 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy)
3507 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode);
3510 smu->plpd_mode = mode;
3515 static const struct amd_pm_funcs swsmu_pm_funcs = {
3516 /* export for sysfs */
3517 .set_fan_control_mode = smu_set_fan_control_mode,
3518 .get_fan_control_mode = smu_get_fan_control_mode,
3519 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3520 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3521 .force_clock_level = smu_force_ppclk_levels,
3522 .print_clock_levels = smu_print_ppclk_levels,
3523 .emit_clock_levels = smu_emit_ppclk_levels,
3524 .force_performance_level = smu_force_performance_level,
3525 .read_sensor = smu_read_sensor,
3526 .get_apu_thermal_limit = smu_get_apu_thermal_limit,
3527 .set_apu_thermal_limit = smu_set_apu_thermal_limit,
3528 .get_performance_level = smu_get_performance_level,
3529 .get_current_power_state = smu_get_current_power_state,
3530 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3531 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3532 .get_pp_num_states = smu_get_power_num_states,
3533 .get_pp_table = smu_sys_get_pp_table,
3534 .set_pp_table = smu_sys_set_pp_table,
3535 .switch_power_profile = smu_switch_power_profile,
3536 /* export to amdgpu */
3537 .dispatch_tasks = smu_handle_dpm_task,
3538 .load_firmware = smu_load_microcode,
3539 .set_powergating_by_smu = smu_dpm_set_power_gate,
3540 .set_power_limit = smu_set_power_limit,
3541 .get_power_limit = smu_get_power_limit,
3542 .get_power_profile_mode = smu_get_power_profile_mode,
3543 .set_power_profile_mode = smu_set_power_profile_mode,
3544 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3545 .set_mp1_state = smu_set_mp1_state,
3546 .gfx_state_change_set = smu_gfx_state_change_set,
3548 .get_sclk = smu_get_sclk,
3549 .get_mclk = smu_get_mclk,
3550 .display_configuration_change = smu_display_configuration_change,
3551 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3552 .display_clock_voltage_request = smu_display_clock_voltage_request,
3553 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3554 .set_active_display_count = smu_set_display_count,
3555 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3556 .get_asic_baco_capability = smu_get_baco_capability,
3557 .set_asic_baco_state = smu_baco_set_state,
3558 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3559 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3560 .asic_reset_mode_2 = smu_mode2_reset,
3561 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3562 .set_df_cstate = smu_set_df_cstate,
3563 .set_xgmi_pstate = smu_set_xgmi_pstate,
3564 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3565 .get_pm_metrics = smu_sys_get_pm_metrics,
3566 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3567 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3568 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3569 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3570 .get_dpm_clock_table = smu_get_dpm_clock_table,
3571 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3574 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3579 if (smu->ppt_funcs->wait_for_event)
3580 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3585 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3588 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3591 /* Confirm the buffer allocated is of correct size */
3592 if (size != smu->stb_context.stb_buf_size)
3596 * No need to lock smu mutex as we access STB directly through MMIO
3597 * and not going through SMU messaging route (for now at least).
3598 * For registers access rely on implementation internal locking.
3600 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3603 #if defined(CONFIG_DEBUG_FS)
3605 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3607 struct amdgpu_device *adev = filp->f_inode->i_private;
3608 struct smu_context *smu = adev->powerplay.pp_handle;
3612 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3616 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3620 filp->private_data = buf;
3629 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3632 struct amdgpu_device *adev = filp->f_inode->i_private;
3633 struct smu_context *smu = adev->powerplay.pp_handle;
3636 if (!filp->private_data)
3639 return simple_read_from_buffer(buf,
3641 pos, filp->private_data,
3642 smu->stb_context.stb_buf_size);
3645 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3647 kvfree(filp->private_data);
3648 filp->private_data = NULL;
3654 * We have to define not only read method but also
3655 * open and release because .read takes up to PAGE_SIZE
3656 * data each time so and so is invoked multiple times.
3657 * We allocate the STB buffer in .open and release it
3660 static const struct file_operations smu_stb_debugfs_fops = {
3661 .owner = THIS_MODULE,
3662 .open = smu_stb_debugfs_open,
3663 .read = smu_stb_debugfs_read,
3664 .release = smu_stb_debugfs_release,
3665 .llseek = default_llseek,
3670 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3672 #if defined(CONFIG_DEBUG_FS)
3674 struct smu_context *smu = adev->powerplay.pp_handle;
3676 if (!smu || (!smu->stb_context.stb_buf_size))
3679 debugfs_create_file_size("amdgpu_smu_stb_dump",
3681 adev_to_drm(adev)->primary->debugfs_root,
3683 &smu_stb_debugfs_fops,
3684 smu->stb_context.stb_buf_size);
3688 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3692 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3693 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3698 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3702 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3703 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3708 int smu_send_rma_reason(struct smu_context *smu)
3712 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
3713 ret = smu->ppt_funcs->send_rma_reason(smu);