1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/stackprotector.h>
28 #include <linux/utsname.h>
30 #include <asm/alternative.h>
31 #include <asm/cmdline.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
49 #include <asm/fpu/api.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
59 #include <asm/cacheinfo.h>
60 #include <asm/memtype.h>
61 #include <asm/microcode.h>
62 #include <asm/intel-family.h>
63 #include <asm/cpu_device_id.h>
65 #include <asm/uv/uv.h>
67 #include <asm/set_memory.h>
68 #include <asm/traps.h>
74 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
75 EXPORT_PER_CPU_SYMBOL(cpu_info);
77 u32 elf_hwcap2 __read_mostly;
79 /* Number of siblings per CPU package */
80 unsigned int __max_threads_per_core __ro_after_init = 1;
81 EXPORT_SYMBOL(__max_threads_per_core);
83 unsigned int __max_dies_per_package __ro_after_init = 1;
84 EXPORT_SYMBOL(__max_dies_per_package);
86 unsigned int __max_logical_packages __ro_after_init = 1;
87 EXPORT_SYMBOL(__max_logical_packages);
89 unsigned int __num_cores_per_package __ro_after_init = 1;
90 EXPORT_SYMBOL(__num_cores_per_package);
92 unsigned int __num_threads_per_package __ro_after_init = 1;
93 EXPORT_SYMBOL(__num_threads_per_package);
95 static struct ppin_info {
100 [X86_VENDOR_INTEL] = {
101 .feature = X86_FEATURE_INTEL_PPIN,
102 .msr_ppin_ctl = MSR_PPIN_CTL,
106 .feature = X86_FEATURE_AMD_PPIN,
107 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
108 .msr_ppin = MSR_AMD_PPIN
112 static const struct x86_cpu_id ppin_cpuids[] = {
113 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
114 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
116 /* Legacy models without CPUID enumeration */
117 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
118 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
119 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
120 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
121 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
122 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
123 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
124 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
125 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
126 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
127 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
132 static void ppin_init(struct cpuinfo_x86 *c)
134 const struct x86_cpu_id *id;
135 unsigned long long val;
136 struct ppin_info *info;
138 id = x86_match_cpu(ppin_cpuids);
143 * Testing the presence of the MSR is not enough. Need to check
144 * that the PPIN_CTL allows reading of the PPIN.
146 info = (struct ppin_info *)id->driver_data;
148 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
151 if ((val & 3UL) == 1UL) {
152 /* PPIN locked in disabled mode */
156 /* If PPIN is disabled, try to enable */
158 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
159 rdmsrl_safe(info->msr_ppin_ctl, &val);
162 /* Is the enable bit set? */
164 c->ppin = __rdmsr(info->msr_ppin);
165 set_cpu_cap(c, info->feature);
170 clear_cpu_cap(c, info->feature);
173 static void default_init(struct cpuinfo_x86 *c)
176 cpu_detect_cache_sizes(c);
178 /* Not much we can do here... */
179 /* Check if at least it has cpuid */
180 if (c->cpuid_level == -1) {
181 /* No cpuid. It must be an ancient CPU */
183 strcpy(c->x86_model_id, "486");
184 else if (c->x86 == 3)
185 strcpy(c->x86_model_id, "386");
190 static const struct cpu_dev default_cpu = {
191 .c_init = default_init,
192 .c_vendor = "Unknown",
193 .c_x86_vendor = X86_VENDOR_UNKNOWN,
196 static const struct cpu_dev *this_cpu = &default_cpu;
198 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
201 * We need valid kernel segments for data and code in long mode too
202 * IRET will check the segment types kkeil 2000/10/28
203 * Also sysret mandates a special GDT layout
205 * TLS descriptors are currently at a different place compared to i386.
206 * Hopefully nobody expects them at a fixed place (Wine?)
208 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
209 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
210 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff),
211 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
212 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff),
213 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff),
215 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
216 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
217 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
218 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff),
220 * Segments used for calling PnP BIOS have byte granularity.
221 * They code segments and data segments have fixed 64k limits,
222 * the transfer segment sizes are set at run time.
224 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
225 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
226 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff),
227 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
228 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
230 * The APM segments have byte granularity and their bases
231 * are set at run time. All have 64k limits.
233 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
234 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
235 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff),
237 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
238 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
241 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
244 static int __init x86_nopcid_setup(char *s)
246 /* nopcid doesn't accept parameters */
250 /* do not emit a message if the feature is not present */
251 if (!boot_cpu_has(X86_FEATURE_PCID))
254 setup_clear_cpu_cap(X86_FEATURE_PCID);
255 pr_info("nopcid: PCID feature disabled\n");
258 early_param("nopcid", x86_nopcid_setup);
261 static int __init x86_noinvpcid_setup(char *s)
263 /* noinvpcid doesn't accept parameters */
267 /* do not emit a message if the feature is not present */
268 if (!boot_cpu_has(X86_FEATURE_INVPCID))
271 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
272 pr_info("noinvpcid: INVPCID feature disabled\n");
275 early_param("noinvpcid", x86_noinvpcid_setup);
278 static int cachesize_override = -1;
279 static int disable_x86_serial_nr = 1;
281 static int __init cachesize_setup(char *str)
283 get_option(&str, &cachesize_override);
286 __setup("cachesize=", cachesize_setup);
288 /* Standard macro to see if a specific flag is changeable */
289 static inline int flag_is_changeable_p(u32 flag)
294 * Cyrix and IDT cpus allow disabling of CPUID
295 * so the code below may return different results
296 * when it is executed before and after enabling
297 * the CPUID. Add "volatile" to not allow gcc to
298 * optimize the subsequent calls to this function.
300 asm volatile ("pushfl \n\t"
311 : "=&r" (f1), "=&r" (f2)
314 return ((f1^f2) & flag) != 0;
317 /* Probe for the CPUID instruction */
318 int have_cpuid_p(void)
320 return flag_is_changeable_p(X86_EFLAGS_ID);
323 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
325 unsigned long lo, hi;
327 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
330 /* Disable processor serial number: */
332 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
334 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
336 pr_notice("CPU serial number disabled.\n");
337 clear_cpu_cap(c, X86_FEATURE_PN);
339 /* Disabling the serial number may affect the cpuid level */
340 c->cpuid_level = cpuid_eax(0);
343 static int __init x86_serial_nr_setup(char *s)
345 disable_x86_serial_nr = 0;
348 __setup("serialnumber", x86_serial_nr_setup);
350 static inline int flag_is_changeable_p(u32 flag)
354 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
359 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
361 if (cpu_has(c, X86_FEATURE_SMEP))
362 cr4_set_bits(X86_CR4_SMEP);
365 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
367 unsigned long eflags = native_save_fl();
369 /* This should have been cleared long ago */
370 BUG_ON(eflags & X86_EFLAGS_AC);
372 if (cpu_has(c, X86_FEATURE_SMAP))
373 cr4_set_bits(X86_CR4_SMAP);
376 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
378 /* Check the boot processor, plus build option for UMIP. */
379 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
382 /* Check the current processor's cpuid bits. */
383 if (!cpu_has(c, X86_FEATURE_UMIP))
386 cr4_set_bits(X86_CR4_UMIP);
388 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
394 * Make sure UMIP is disabled in case it was enabled in a
395 * previous boot (e.g., via kexec).
397 cr4_clear_bits(X86_CR4_UMIP);
400 /* These bits should not change their value after CPU init is finished. */
401 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
402 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED;
403 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
404 static unsigned long cr4_pinned_bits __ro_after_init;
406 void native_write_cr0(unsigned long val)
408 unsigned long bits_missing = 0;
411 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
413 if (static_branch_likely(&cr_pinning)) {
414 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
415 bits_missing = X86_CR0_WP;
419 /* Warn after we've set the missing bits. */
420 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
423 EXPORT_SYMBOL(native_write_cr0);
425 void __no_profile native_write_cr4(unsigned long val)
427 unsigned long bits_changed = 0;
430 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
432 if (static_branch_likely(&cr_pinning)) {
433 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
434 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
435 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
438 /* Warn after we've corrected the changed bits. */
439 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
443 #if IS_MODULE(CONFIG_LKDTM)
444 EXPORT_SYMBOL_GPL(native_write_cr4);
447 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
449 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
451 lockdep_assert_irqs_disabled();
453 newval = (cr4 & ~clear) | set;
455 this_cpu_write(cpu_tlbstate.cr4, newval);
459 EXPORT_SYMBOL(cr4_update_irqsoff);
461 /* Read the CR4 shadow. */
462 unsigned long cr4_read_shadow(void)
464 return this_cpu_read(cpu_tlbstate.cr4);
466 EXPORT_SYMBOL_GPL(cr4_read_shadow);
470 unsigned long cr4 = __read_cr4();
472 if (boot_cpu_has(X86_FEATURE_PCID))
473 cr4 |= X86_CR4_PCIDE;
474 if (static_branch_likely(&cr_pinning))
475 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
479 /* Initialize cr4 shadow for this CPU. */
480 this_cpu_write(cpu_tlbstate.cr4, cr4);
484 * Once CPU feature detection is finished (and boot params have been
485 * parsed), record any of the sensitive CR bits that are set, and
488 static void __init setup_cr_pinning(void)
490 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
491 static_key_enable(&cr_pinning.key);
494 static __init int x86_nofsgsbase_setup(char *arg)
496 /* Require an exact match without trailing characters. */
500 /* Do not emit a message if the feature is not present. */
501 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
504 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
505 pr_info("FSGSBASE disabled via kernel command line\n");
508 __setup("nofsgsbase", x86_nofsgsbase_setup);
511 * Protection Keys are not available in 32-bit mode.
513 static bool pku_disabled;
515 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
517 if (c == &boot_cpu_data) {
518 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
521 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
522 * bit to be set. Enforce it.
524 setup_force_cpu_cap(X86_FEATURE_OSPKE);
526 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
530 cr4_set_bits(X86_CR4_PKE);
531 /* Load the default PKRU value */
532 pkru_write_default();
535 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
536 static __init int setup_disable_pku(char *arg)
539 * Do not clear the X86_FEATURE_PKU bit. All of the
540 * runtime checks are against OSPKE so clearing the
543 * This way, we will see "pku" in cpuinfo, but not
544 * "ospke", which is exactly what we want. It shows
545 * that the CPU has PKU, but the OS has not enabled it.
546 * This happens to be exactly how a system would look
547 * if we disabled the config option.
549 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
553 __setup("nopku", setup_disable_pku);
556 #ifdef CONFIG_X86_KERNEL_IBT
558 __noendbr u64 ibt_save(bool disable)
562 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
563 rdmsrl(MSR_IA32_S_CET, msr);
565 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
571 __noendbr void ibt_restore(u64 save)
575 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
576 rdmsrl(MSR_IA32_S_CET, msr);
577 msr &= ~CET_ENDBR_EN;
578 msr |= (save & CET_ENDBR_EN);
579 wrmsrl(MSR_IA32_S_CET, msr);
585 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
587 bool user_shstk, kernel_ibt;
589 if (!IS_ENABLED(CONFIG_X86_CET))
592 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
593 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
594 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
596 if (!kernel_ibt && !user_shstk)
600 set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
603 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN);
605 wrmsrl(MSR_IA32_S_CET, 0);
607 cr4_set_bits(X86_CR4_CET);
609 if (kernel_ibt && ibt_selftest()) {
610 pr_err("IBT selftest: Failed!\n");
611 wrmsrl(MSR_IA32_S_CET, 0);
612 setup_clear_cpu_cap(X86_FEATURE_IBT);
616 __noendbr void cet_disable(void)
618 if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
619 cpu_feature_enabled(X86_FEATURE_SHSTK)))
622 wrmsrl(MSR_IA32_S_CET, 0);
623 wrmsrl(MSR_IA32_U_CET, 0);
627 * Some CPU features depend on higher CPUID levels, which may not always
628 * be available due to CPUID level capping or broken virtualization
629 * software. Add those features to this table to auto-disable them.
631 struct cpuid_dependent_feature {
636 static const struct cpuid_dependent_feature
637 cpuid_dependent_features[] = {
638 { X86_FEATURE_MWAIT, 0x00000005 },
639 { X86_FEATURE_DCA, 0x00000009 },
640 { X86_FEATURE_XSAVE, 0x0000000d },
644 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
646 const struct cpuid_dependent_feature *df;
648 for (df = cpuid_dependent_features; df->feature; df++) {
650 if (!cpu_has(c, df->feature))
653 * Note: cpuid_level is set to -1 if unavailable, but
654 * extended_extended_level is set to 0 if unavailable
655 * and the legitimate extended levels are all negative
656 * when signed; hence the weird messing around with
659 if (!((s32)df->level < 0 ?
660 (u32)df->level > (u32)c->extended_cpuid_level :
661 (s32)df->level > (s32)c->cpuid_level))
664 clear_cpu_cap(c, df->feature);
668 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
669 x86_cap_flag(df->feature), df->level);
674 * Naming convention should be: <Name> [(<Codename>)]
675 * This table only is used unless init_<vendor>() below doesn't set it;
676 * in particular, if CPUID levels 0x80000002..4 are supported, this
680 /* Look up CPU names by table lookup. */
681 static const char *table_lookup_model(struct cpuinfo_x86 *c)
684 const struct legacy_cpu_model_info *info;
686 if (c->x86_model >= 16)
687 return NULL; /* Range check */
692 info = this_cpu->legacy_models;
694 while (info->family) {
695 if (info->family == c->x86)
696 return info->model_names[c->x86_model];
700 return NULL; /* Not found */
703 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
704 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
705 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
708 /* The 32-bit entry code needs to find cpu_entry_area. */
709 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
712 /* Load the original GDT from the per-cpu structure */
713 void load_direct_gdt(int cpu)
715 struct desc_ptr gdt_descr;
717 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
718 gdt_descr.size = GDT_SIZE - 1;
719 load_gdt(&gdt_descr);
721 EXPORT_SYMBOL_GPL(load_direct_gdt);
723 /* Load a fixmap remapping of the per-cpu GDT */
724 void load_fixmap_gdt(int cpu)
726 struct desc_ptr gdt_descr;
728 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
729 gdt_descr.size = GDT_SIZE - 1;
730 load_gdt(&gdt_descr);
732 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
735 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
736 * @cpu: The CPU number for which this is invoked
738 * Invoked during early boot to switch from early GDT and early per CPU to
739 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
740 * switch is implicit by loading the direct GDT. On 64bit this requires
743 void __init switch_gdt_and_percpu_base(int cpu)
745 load_direct_gdt(cpu);
749 * No need to load %gs. It is already correct.
751 * Writing %gs on 64bit would zero GSBASE which would make any per
752 * CPU operation up to the point of the wrmsrl() fault.
754 * Set GSBASE to the new offset. Until the wrmsrl() happens the
755 * early mapping is still valid. That means the GSBASE update will
756 * lose any prior per CPU data which was not copied over in
757 * setup_per_cpu_areas().
759 * This works even with stackprotector enabled because the
760 * per CPU stack canary is 0 in both per CPU areas.
762 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
765 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
766 * it is required to load FS again so that the 'hidden' part is
767 * updated from the new GDT. Up to this point the early per CPU
768 * translation is active. Any content of the early per CPU data
769 * which was not copied over in setup_per_cpu_areas() is lost.
771 loadsegment(fs, __KERNEL_PERCPU);
775 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
777 static void get_model_name(struct cpuinfo_x86 *c)
782 if (c->extended_cpuid_level < 0x80000004)
785 v = (unsigned int *)c->x86_model_id;
786 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
787 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
788 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
789 c->x86_model_id[48] = 0;
791 /* Trim whitespace */
792 p = q = s = &c->x86_model_id[0];
798 /* Note the last non-whitespace index */
808 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
810 unsigned int n, dummy, ebx, ecx, edx, l2size;
812 n = c->extended_cpuid_level;
814 if (n >= 0x80000005) {
815 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
816 c->x86_cache_size = (ecx>>24) + (edx>>24);
818 /* On K8 L1 TLB is inclusive, so don't count it */
823 if (n < 0x80000006) /* Some chips just has a large L1. */
826 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
830 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
832 /* do processor-specific cache resizing */
833 if (this_cpu->legacy_cache_size)
834 l2size = this_cpu->legacy_cache_size(c, l2size);
836 /* Allow user to override all this if necessary. */
837 if (cachesize_override != -1)
838 l2size = cachesize_override;
841 return; /* Again, no L2 cache is possible */
844 c->x86_cache_size = l2size;
847 u16 __read_mostly tlb_lli_4k[NR_INFO];
848 u16 __read_mostly tlb_lli_2m[NR_INFO];
849 u16 __read_mostly tlb_lli_4m[NR_INFO];
850 u16 __read_mostly tlb_lld_4k[NR_INFO];
851 u16 __read_mostly tlb_lld_2m[NR_INFO];
852 u16 __read_mostly tlb_lld_4m[NR_INFO];
853 u16 __read_mostly tlb_lld_1g[NR_INFO];
855 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
857 if (this_cpu->c_detect_tlb)
858 this_cpu->c_detect_tlb(c);
860 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
861 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
862 tlb_lli_4m[ENTRIES]);
864 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
865 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
866 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
869 static void get_cpu_vendor(struct cpuinfo_x86 *c)
871 char *v = c->x86_vendor_id;
874 for (i = 0; i < X86_VENDOR_NUM; i++) {
878 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
879 (cpu_devs[i]->c_ident[1] &&
880 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
882 this_cpu = cpu_devs[i];
883 c->x86_vendor = this_cpu->c_x86_vendor;
888 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
889 "CPU: Your system may be unstable.\n", v);
891 c->x86_vendor = X86_VENDOR_UNKNOWN;
892 this_cpu = &default_cpu;
895 void cpu_detect(struct cpuinfo_x86 *c)
897 /* Get vendor name */
898 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
899 (unsigned int *)&c->x86_vendor_id[0],
900 (unsigned int *)&c->x86_vendor_id[8],
901 (unsigned int *)&c->x86_vendor_id[4]);
904 /* Intel-defined flags: level 0x00000001 */
905 if (c->cpuid_level >= 0x00000001) {
906 u32 junk, tfms, cap0, misc;
908 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
909 c->x86 = x86_family(tfms);
910 c->x86_model = x86_model(tfms);
911 c->x86_stepping = x86_stepping(tfms);
913 if (cap0 & (1<<19)) {
914 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
915 c->x86_cache_alignment = c->x86_clflush_size;
920 static void apply_forced_caps(struct cpuinfo_x86 *c)
924 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
925 c->x86_capability[i] &= ~cpu_caps_cleared[i];
926 c->x86_capability[i] |= cpu_caps_set[i];
930 static void init_speculation_control(struct cpuinfo_x86 *c)
933 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
934 * and they also have a different bit for STIBP support. Also,
935 * a hypervisor might have set the individual AMD bits even on
936 * Intel CPUs, for finer-grained selection of what's available.
938 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
939 set_cpu_cap(c, X86_FEATURE_IBRS);
940 set_cpu_cap(c, X86_FEATURE_IBPB);
941 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
944 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
945 set_cpu_cap(c, X86_FEATURE_STIBP);
947 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
948 cpu_has(c, X86_FEATURE_VIRT_SSBD))
949 set_cpu_cap(c, X86_FEATURE_SSBD);
951 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
952 set_cpu_cap(c, X86_FEATURE_IBRS);
953 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
956 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
957 set_cpu_cap(c, X86_FEATURE_IBPB);
959 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
960 set_cpu_cap(c, X86_FEATURE_STIBP);
961 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
964 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
965 set_cpu_cap(c, X86_FEATURE_SSBD);
966 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
967 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
971 void get_cpu_cap(struct cpuinfo_x86 *c)
973 u32 eax, ebx, ecx, edx;
975 /* Intel-defined flags: level 0x00000001 */
976 if (c->cpuid_level >= 0x00000001) {
977 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
979 c->x86_capability[CPUID_1_ECX] = ecx;
980 c->x86_capability[CPUID_1_EDX] = edx;
983 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
984 if (c->cpuid_level >= 0x00000006)
985 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
987 /* Additional Intel-defined flags: level 0x00000007 */
988 if (c->cpuid_level >= 0x00000007) {
989 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
990 c->x86_capability[CPUID_7_0_EBX] = ebx;
991 c->x86_capability[CPUID_7_ECX] = ecx;
992 c->x86_capability[CPUID_7_EDX] = edx;
994 /* Check valid sub-leaf index before accessing it */
996 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
997 c->x86_capability[CPUID_7_1_EAX] = eax;
1001 /* Extended state features: level 0x0000000d */
1002 if (c->cpuid_level >= 0x0000000d) {
1003 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1005 c->x86_capability[CPUID_D_1_EAX] = eax;
1008 /* AMD-defined flags: level 0x80000001 */
1009 eax = cpuid_eax(0x80000000);
1010 c->extended_cpuid_level = eax;
1012 if ((eax & 0xffff0000) == 0x80000000) {
1013 if (eax >= 0x80000001) {
1014 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1016 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1017 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1021 if (c->extended_cpuid_level >= 0x80000007) {
1022 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1024 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1028 if (c->extended_cpuid_level >= 0x80000008) {
1029 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1030 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1033 if (c->extended_cpuid_level >= 0x8000000a)
1034 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1036 if (c->extended_cpuid_level >= 0x8000001f)
1037 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1039 if (c->extended_cpuid_level >= 0x80000021)
1040 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1042 init_scattered_cpuid_features(c);
1043 init_speculation_control(c);
1046 * Clear/Set all flags overridden by options, after probe.
1047 * This needs to happen each time we re-probe, which may happen
1048 * several times during CPU initialization.
1050 apply_forced_caps(c);
1053 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1055 u32 eax, ebx, ecx, edx;
1056 bool vp_bits_from_cpuid = true;
1058 if (!cpu_has(c, X86_FEATURE_CPUID) ||
1059 (c->extended_cpuid_level < 0x80000008))
1060 vp_bits_from_cpuid = false;
1062 if (vp_bits_from_cpuid) {
1063 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1065 c->x86_virt_bits = (eax >> 8) & 0xff;
1066 c->x86_phys_bits = eax & 0xff;
1068 if (IS_ENABLED(CONFIG_X86_64)) {
1069 c->x86_clflush_size = 64;
1070 c->x86_phys_bits = 36;
1071 c->x86_virt_bits = 48;
1073 c->x86_clflush_size = 32;
1074 c->x86_virt_bits = 32;
1075 c->x86_phys_bits = 32;
1077 if (cpu_has(c, X86_FEATURE_PAE) ||
1078 cpu_has(c, X86_FEATURE_PSE36))
1079 c->x86_phys_bits = 36;
1082 c->x86_cache_bits = c->x86_phys_bits;
1083 c->x86_cache_alignment = c->x86_clflush_size;
1086 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1088 #ifdef CONFIG_X86_32
1092 * First of all, decide if this is a 486 or higher
1093 * It's a 486 if we can modify the AC flag
1095 if (flag_is_changeable_p(X86_EFLAGS_AC))
1100 for (i = 0; i < X86_VENDOR_NUM; i++)
1101 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1102 c->x86_vendor_id[0] = 0;
1103 cpu_devs[i]->c_identify(c);
1104 if (c->x86_vendor_id[0]) {
1112 #define NO_SPECULATION BIT(0)
1113 #define NO_MELTDOWN BIT(1)
1114 #define NO_SSB BIT(2)
1115 #define NO_L1TF BIT(3)
1116 #define NO_MDS BIT(4)
1117 #define MSBDS_ONLY BIT(5)
1118 #define NO_SWAPGS BIT(6)
1119 #define NO_ITLB_MULTIHIT BIT(7)
1120 #define NO_SPECTRE_V2 BIT(8)
1121 #define NO_MMIO BIT(9)
1122 #define NO_EIBRS_PBRSB BIT(10)
1123 #define NO_BHI BIT(11)
1125 #define VULNWL(vendor, family, model, whitelist) \
1126 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1128 #define VULNWL_INTEL(model, whitelist) \
1129 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1131 #define VULNWL_AMD(family, whitelist) \
1132 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1134 #define VULNWL_HYGON(family, whitelist) \
1135 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1137 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1138 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1139 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1140 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1141 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1142 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1143 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1145 /* Intel Family 6 */
1146 VULNWL_INTEL(TIGERLAKE, NO_MMIO),
1147 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
1148 VULNWL_INTEL(ALDERLAKE, NO_MMIO),
1149 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
1151 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1152 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1153 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1154 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1155 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1157 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1158 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1159 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1160 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1161 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1162 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1164 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1166 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1167 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1169 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1170 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1171 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1174 * Technically, swapgs isn't serializing on AMD (despite it previously
1175 * being documented as such in the APM). But according to AMD, %gs is
1176 * updated non-speculatively, and the issuing of %gs-relative memory
1177 * operands will be blocked until the %gs update completes, which is
1178 * good enough for our purposes.
1181 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB),
1182 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1183 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1185 /* AMD Family 0xf - 0x12 */
1186 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1187 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1188 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1189 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1191 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1192 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1193 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1195 /* Zhaoxin Family 7 */
1196 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1197 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1201 #define VULNBL(vendor, family, model, blacklist) \
1202 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1204 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1205 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1206 INTEL_FAM6_##model, steppings, \
1207 X86_FEATURE_ANY, issues)
1209 #define VULNBL_AMD(family, blacklist) \
1210 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1212 #define VULNBL_HYGON(family, blacklist) \
1213 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1215 #define SRBDS BIT(0)
1216 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1218 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1219 #define MMIO_SBDS BIT(2)
1220 /* CPU is affected by RETbleed, speculating where you would not expect it */
1221 #define RETBLEED BIT(3)
1222 /* CPU is affected by SMT (cross-thread) return predictions */
1223 #define SMT_RSB BIT(4)
1224 /* CPU is affected by SRSO */
1226 /* CPU is affected by GDS */
1228 /* CPU is affected by Register File Data Sampling */
1231 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1232 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1233 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1234 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1235 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1236 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1237 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1238 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1239 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1240 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1241 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1242 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1243 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1244 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1245 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1246 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1247 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1248 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1249 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1250 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1251 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1252 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1253 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1254 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS),
1255 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1256 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1257 VULNBL_INTEL_STEPPINGS(ALDERLAKE, X86_STEPPING_ANY, RFDS),
1258 VULNBL_INTEL_STEPPINGS(ALDERLAKE_L, X86_STEPPING_ANY, RFDS),
1259 VULNBL_INTEL_STEPPINGS(RAPTORLAKE, X86_STEPPING_ANY, RFDS),
1260 VULNBL_INTEL_STEPPINGS(RAPTORLAKE_P, X86_STEPPING_ANY, RFDS),
1261 VULNBL_INTEL_STEPPINGS(RAPTORLAKE_S, X86_STEPPING_ANY, RFDS),
1262 VULNBL_INTEL_STEPPINGS(ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS),
1263 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
1264 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS),
1265 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
1266 VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS),
1267 VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS),
1268 VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS),
1270 VULNBL_AMD(0x15, RETBLEED),
1271 VULNBL_AMD(0x16, RETBLEED),
1272 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1273 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
1274 VULNBL_AMD(0x19, SRSO),
1278 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1280 const struct x86_cpu_id *m = x86_match_cpu(table);
1282 return m && !!(m->driver_data & which);
1285 u64 x86_read_arch_cap_msr(void)
1287 u64 x86_arch_cap_msr = 0;
1289 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1290 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr);
1292 return x86_arch_cap_msr;
1295 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr)
1297 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO &&
1298 x86_arch_cap_msr & ARCH_CAP_PSDP_NO &&
1299 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO);
1302 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr)
1304 /* The "immunity" bit trumps everything else: */
1305 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO)
1309 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to
1310 * indicate that mitigation is needed because guest is running on a
1311 * vulnerable hardware or may migrate to such hardware:
1313 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)
1316 /* Only consult the blacklist when there is no enumeration: */
1317 return cpu_matches(cpu_vuln_blacklist, RFDS);
1320 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1322 u64 x86_arch_cap_msr = x86_read_arch_cap_msr();
1324 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1325 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1326 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO))
1327 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1329 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1332 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1334 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1335 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1337 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1338 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) &&
1339 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1340 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1343 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1344 * flag and protect from vendor-specific bugs via the whitelist.
1346 * Don't use AutoIBRS when SNP is enabled because it degrades host
1347 * userspace indirect branch performance.
1349 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) ||
1350 (cpu_has(c, X86_FEATURE_AUTOIBRS) &&
1351 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) {
1352 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1353 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1354 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO))
1355 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1358 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1359 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) {
1360 setup_force_cpu_bug(X86_BUG_MDS);
1361 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1362 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1365 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1366 setup_force_cpu_bug(X86_BUG_SWAPGS);
1369 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1370 * - TSX is supported or
1371 * - TSX_CTRL is present
1373 * TSX_CTRL check is needed for cases when TSX could be disabled before
1374 * the kernel boot e.g. kexec.
1375 * TSX_CTRL check alone is not sufficient for cases when the microcode
1376 * update is not present or running as guest that don't get TSX_CTRL.
1378 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) &&
1379 (cpu_has(c, X86_FEATURE_RTM) ||
1380 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)))
1381 setup_force_cpu_bug(X86_BUG_TAA);
1384 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1385 * in the vulnerability blacklist.
1387 * Some of the implications and mitigation of Shared Buffers Data
1388 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1391 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1392 cpu_has(c, X86_FEATURE_RDSEED)) &&
1393 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1394 setup_force_cpu_bug(X86_BUG_SRBDS);
1397 * Processor MMIO Stale Data bug enumeration
1399 * Affected CPU list is generally enough to enumerate the vulnerability,
1400 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1401 * not want the guest to enumerate the bug.
1403 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1404 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1406 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) {
1407 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1408 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1409 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1410 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1413 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1414 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA))
1415 setup_force_cpu_bug(X86_BUG_RETBLEED);
1418 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1419 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1421 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1422 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1423 setup_force_cpu_bug(X86_BUG_SRSO);
1427 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1428 * an affected processor, the VMM may have disabled the use of GATHER by
1429 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1430 * which means that AVX will be disabled.
1432 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) &&
1433 boot_cpu_has(X86_FEATURE_AVX))
1434 setup_force_cpu_bug(X86_BUG_GDS);
1436 if (vulnerable_to_rfds(x86_arch_cap_msr))
1437 setup_force_cpu_bug(X86_BUG_RFDS);
1439 /* When virtualized, eIBRS could be hidden, assume vulnerable */
1440 if (!(x86_arch_cap_msr & ARCH_CAP_BHI_NO) &&
1441 !cpu_matches(cpu_vuln_whitelist, NO_BHI) &&
1442 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) ||
1443 boot_cpu_has(X86_FEATURE_HYPERVISOR)))
1444 setup_force_cpu_bug(X86_BUG_BHI);
1446 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1449 /* Rogue Data Cache Load? No! */
1450 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO)
1453 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1455 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1458 setup_force_cpu_bug(X86_BUG_L1TF);
1462 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1463 * unfortunately, that's not true in practice because of early VIA
1464 * chips and (more importantly) broken virtualizers that are not easy
1465 * to detect. In the latter case it doesn't even *fail* reliably, so
1466 * probing for it doesn't even work. Disable it completely on 32-bit
1467 * unless we can find a reliable way to detect all the broken cases.
1468 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1470 static void detect_nopl(void)
1472 #ifdef CONFIG_X86_32
1473 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1475 setup_force_cpu_cap(X86_FEATURE_NOPL);
1480 * We parse cpu parameters early because fpu__init_system() is executed
1481 * before parse_early_param().
1483 static void __init cpu_parse_early_param(void)
1486 char *argptr = arg, *opt;
1487 int arglen, taint = 0;
1489 #ifdef CONFIG_X86_32
1490 if (cmdline_find_option_bool(boot_command_line, "no387"))
1491 #ifdef CONFIG_MATH_EMULATION
1492 setup_clear_cpu_cap(X86_FEATURE_FPU);
1494 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1497 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1498 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1501 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1502 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1504 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1505 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1507 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1508 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1510 if (cmdline_find_option_bool(boot_command_line, "nousershstk"))
1511 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1513 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1517 pr_info("Clearing CPUID bits:");
1520 bool found __maybe_unused = false;
1523 opt = strsep(&argptr, ",");
1526 * Handle naked numbers first for feature flags which don't
1529 if (!kstrtouint(opt, 10, &bit)) {
1530 if (bit < NCAPINTS * 32) {
1532 /* empty-string, i.e., ""-defined feature flags */
1533 if (!x86_cap_flags[bit])
1534 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1536 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1538 setup_clear_cpu_cap(bit);
1542 * The assumption is that there are no feature names with only
1543 * numbers in the name thus go to the next argument.
1548 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1549 if (!x86_cap_flag(bit))
1552 if (strcmp(x86_cap_flag(bit), opt))
1555 pr_cont(" %s", opt);
1556 setup_clear_cpu_cap(bit);
1563 pr_cont(" (unknown: %s)", opt);
1568 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1572 * Do minimum CPU detection early.
1573 * Fields really needed: vendor, cpuid_level, family, model, mask,
1575 * The others are not touched to avoid unwanted side effects.
1577 * WARNING: this function is only called on the boot CPU. Don't add code
1578 * here that is supposed to run on all CPUs.
1580 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1582 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1583 c->extended_cpuid_level = 0;
1585 if (!have_cpuid_p())
1586 identify_cpu_without_cpuid(c);
1588 /* cyrix could have cpuid enabled via c_identify()*/
1589 if (have_cpuid_p()) {
1593 setup_force_cpu_cap(X86_FEATURE_CPUID);
1594 get_cpu_address_sizes(c);
1595 cpu_parse_early_param();
1597 cpu_init_topology(c);
1599 if (this_cpu->c_early_init)
1600 this_cpu->c_early_init(c);
1603 filter_cpuid_features(c, false);
1605 if (this_cpu->c_bsp_init)
1606 this_cpu->c_bsp_init(c);
1608 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1609 get_cpu_address_sizes(c);
1610 cpu_init_topology(c);
1613 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1615 cpu_set_bug_bits(c);
1619 #ifdef CONFIG_X86_32
1621 * Regardless of whether PCID is enumerated, the SDM says
1622 * that it can't be enabled in 32-bit mode.
1624 setup_clear_cpu_cap(X86_FEATURE_PCID);
1628 * Later in the boot process pgtable_l5_enabled() relies on
1629 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1630 * enabled by this point we need to clear the feature bit to avoid
1631 * false-positives at the later stage.
1633 * pgtable_l5_enabled() can be false here for several reasons:
1634 * - 5-level paging is disabled compile-time;
1635 * - it's 32-bit kernel;
1636 * - machine doesn't support 5-level paging;
1637 * - user specified 'no5lvl' in kernel command line.
1639 if (!pgtable_l5_enabled())
1640 setup_clear_cpu_cap(X86_FEATURE_LA57);
1645 void __init early_cpu_init(void)
1647 const struct cpu_dev *const *cdev;
1650 #ifdef CONFIG_PROCESSOR_SELECT
1651 pr_info("KERNEL supported cpus:\n");
1654 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1655 const struct cpu_dev *cpudev = *cdev;
1657 if (count >= X86_VENDOR_NUM)
1659 cpu_devs[count] = cpudev;
1662 #ifdef CONFIG_PROCESSOR_SELECT
1666 for (j = 0; j < 2; j++) {
1667 if (!cpudev->c_ident[j])
1669 pr_info(" %s %s\n", cpudev->c_vendor,
1670 cpudev->c_ident[j]);
1675 early_identify_cpu(&boot_cpu_data);
1678 static bool detect_null_seg_behavior(void)
1681 * Empirically, writing zero to a segment selector on AMD does
1682 * not clear the base, whereas writing zero to a segment
1683 * selector on Intel does clear the base. Intel's behavior
1684 * allows slightly faster context switches in the common case
1685 * where GS is unused by the prev and next threads.
1687 * Since neither vendor documents this anywhere that I can see,
1688 * detect it directly instead of hard-coding the choice by
1691 * I've designated AMD's behavior as the "bug" because it's
1692 * counterintuitive and less friendly.
1695 unsigned long old_base, tmp;
1696 rdmsrl(MSR_FS_BASE, old_base);
1697 wrmsrl(MSR_FS_BASE, 1);
1699 rdmsrl(MSR_FS_BASE, tmp);
1700 wrmsrl(MSR_FS_BASE, old_base);
1704 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1706 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1707 if (!IS_ENABLED(CONFIG_X86_64))
1710 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1714 * CPUID bit above wasn't set. If this kernel is still running
1715 * as a HV guest, then the HV has decided not to advertize
1716 * that CPUID bit for whatever reason. For example, one
1717 * member of the migration pool might be vulnerable. Which
1718 * means, the bug is present: set the BUG flag and return.
1720 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1721 set_cpu_bug(c, X86_BUG_NULL_SEG);
1726 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1727 * 0x18 is the respective family for Hygon.
1729 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1730 detect_null_seg_behavior())
1733 /* All the remaining ones are affected */
1734 set_cpu_bug(c, X86_BUG_NULL_SEG);
1737 static void generic_identify(struct cpuinfo_x86 *c)
1739 c->extended_cpuid_level = 0;
1741 if (!have_cpuid_p())
1742 identify_cpu_without_cpuid(c);
1744 /* cyrix could have cpuid enabled via c_identify()*/
1745 if (!have_cpuid_p())
1754 get_cpu_address_sizes(c);
1756 get_model_name(c); /* Default name */
1759 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1760 * systems that run Linux at CPL > 0 may or may not have the
1761 * issue, but, even if they have the issue, there's absolutely
1762 * nothing we can do about it because we can't use the real IRET
1765 * NB: For the time being, only 32-bit kernels support
1766 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1767 * whether to apply espfix using paravirt hooks. If any
1768 * non-paravirt system ever shows up that does *not* have the
1769 * ESPFIX issue, we can change this.
1771 #ifdef CONFIG_X86_32
1772 set_cpu_bug(c, X86_BUG_ESPFIX);
1777 * This does the hard work of actually picking apart the CPU stuff...
1779 static void identify_cpu(struct cpuinfo_x86 *c)
1783 c->loops_per_jiffy = loops_per_jiffy;
1784 c->x86_cache_size = 0;
1785 c->x86_vendor = X86_VENDOR_UNKNOWN;
1786 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1787 c->x86_vendor_id[0] = '\0'; /* Unset */
1788 c->x86_model_id[0] = '\0'; /* Unset */
1789 #ifdef CONFIG_X86_64
1790 c->x86_clflush_size = 64;
1791 c->x86_phys_bits = 36;
1792 c->x86_virt_bits = 48;
1794 c->cpuid_level = -1; /* CPUID not detected */
1795 c->x86_clflush_size = 32;
1796 c->x86_phys_bits = 32;
1797 c->x86_virt_bits = 32;
1799 c->x86_cache_alignment = c->x86_clflush_size;
1800 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1801 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1802 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1805 generic_identify(c);
1807 cpu_parse_topology(c);
1809 if (this_cpu->c_identify)
1810 this_cpu->c_identify(c);
1812 /* Clear/Set all flags overridden by options, after probe */
1813 apply_forced_caps(c);
1816 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and
1817 * Hygon will clear it in ->c_init() below.
1819 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1822 * Vendor-specific initialization. In this section we
1823 * canonicalize the feature flags, meaning if there are
1824 * features a certain CPU supports which CPUID doesn't
1825 * tell us, CPUID claiming incorrect flags, or other bugs,
1826 * we handle them here.
1828 * At the end of this section, c->x86_capability better
1829 * indicate the features this CPU genuinely supports!
1831 if (this_cpu->c_init)
1832 this_cpu->c_init(c);
1834 /* Disable the PN if appropriate */
1835 squash_the_stupid_serial_number(c);
1837 /* Set up SMEP/SMAP/UMIP */
1842 /* Enable FSGSBASE instructions if available. */
1843 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1844 cr4_set_bits(X86_CR4_FSGSBASE);
1845 elf_hwcap2 |= HWCAP2_FSGSBASE;
1849 * The vendor-specific functions might have changed features.
1850 * Now we do "generic changes."
1853 /* Filter out anything that depends on CPUID levels we don't have */
1854 filter_cpuid_features(c, true);
1856 /* If the model name is still unset, do table lookup. */
1857 if (!c->x86_model_id[0]) {
1859 p = table_lookup_model(c);
1861 strcpy(c->x86_model_id, p);
1863 /* Last resort... */
1864 sprintf(c->x86_model_id, "%02x/%02x",
1865 c->x86, c->x86_model);
1873 * Clear/Set all flags overridden by options, need do it
1874 * before following smp all cpus cap AND.
1876 apply_forced_caps(c);
1879 * On SMP, boot_cpu_data holds the common feature set between
1880 * all CPUs; so make sure that we indicate which features are
1881 * common between the CPUs. The first time this routine gets
1882 * executed, c == &boot_cpu_data.
1884 if (c != &boot_cpu_data) {
1885 /* AND the already accumulated flags with these */
1886 for (i = 0; i < NCAPINTS; i++)
1887 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1889 /* OR, i.e. replicate the bug flags */
1890 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1891 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1896 /* Init Machine Check Exception if available. */
1900 numa_add_cpu(smp_processor_id());
1905 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1906 * on 32-bit kernels:
1908 #ifdef CONFIG_X86_32
1909 void enable_sep_cpu(void)
1911 struct tss_struct *tss;
1914 if (!boot_cpu_has(X86_FEATURE_SEP))
1918 tss = &per_cpu(cpu_tss_rw, cpu);
1921 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1922 * see the big comment in struct x86_hw_tss's definition.
1925 tss->x86_tss.ss1 = __KERNEL_CS;
1926 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1927 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1928 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1934 static __init void identify_boot_cpu(void)
1936 identify_cpu(&boot_cpu_data);
1937 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1938 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1939 #ifdef CONFIG_X86_32
1942 cpu_detect_tlb(&boot_cpu_data);
1950 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1952 BUG_ON(c == &boot_cpu_data);
1954 #ifdef CONFIG_X86_32
1957 x86_spec_ctrl_setup_ap();
1959 if (boot_cpu_has_bug(X86_BUG_GDS))
1965 void print_cpu_info(struct cpuinfo_x86 *c)
1967 const char *vendor = NULL;
1969 if (c->x86_vendor < X86_VENDOR_NUM) {
1970 vendor = this_cpu->c_vendor;
1972 if (c->cpuid_level >= 0)
1973 vendor = c->x86_vendor_id;
1976 if (vendor && !strstr(c->x86_model_id, vendor))
1977 pr_cont("%s ", vendor);
1979 if (c->x86_model_id[0])
1980 pr_cont("%s", c->x86_model_id);
1982 pr_cont("%d86", c->x86);
1984 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1986 if (c->x86_stepping || c->cpuid_level >= 0)
1987 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1993 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
1994 * function prevents it from becoming an environment variable for init.
1996 static __init int setup_clearcpuid(char *arg)
2000 __setup("clearcpuid=", setup_clearcpuid);
2002 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
2003 .current_task = &init_task,
2004 .preempt_count = INIT_PREEMPT_COUNT,
2005 .top_of_stack = TOP_OF_INIT_STACK,
2007 EXPORT_PER_CPU_SYMBOL(pcpu_hot);
2008 EXPORT_PER_CPU_SYMBOL(const_pcpu_hot);
2010 #ifdef CONFIG_X86_64
2011 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
2012 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
2013 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
2015 static void wrmsrl_cstar(unsigned long val)
2018 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2019 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2020 * guest. Avoid the pointless write on all Intel CPUs.
2022 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2023 wrmsrl(MSR_CSTAR, val);
2026 static inline void idt_syscall_init(void)
2028 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
2030 if (ia32_enabled()) {
2031 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2033 * This only works on Intel CPUs.
2034 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2035 * This does not cause SYSENTER to jump to the wrong location, because
2036 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2038 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2039 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2040 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2041 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2043 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore);
2044 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2045 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2046 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2050 * Flags to clear on syscall; clear as much as possible
2051 * to minimize user space-kernel interference.
2053 wrmsrl(MSR_SYSCALL_MASK,
2054 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2055 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2056 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2057 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2058 X86_EFLAGS_AC|X86_EFLAGS_ID);
2061 /* May not be marked __init: used by software suspend */
2062 void syscall_init(void)
2064 /* The default user and kernel segments */
2065 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
2068 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
2069 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED
2070 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit
2071 * instruction to return to ring 3 (both sysexit and sysret cause
2072 * #UD when FRED is enabled).
2074 if (!cpu_feature_enabled(X86_FEATURE_FRED))
2078 #else /* CONFIG_X86_64 */
2080 #ifdef CONFIG_STACKPROTECTOR
2081 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2082 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2085 #endif /* CONFIG_X86_64 */
2088 * Clear all 6 debug registers:
2090 static void clear_all_debug_regs(void)
2094 for (i = 0; i < 8; i++) {
2095 /* Ignore db4, db5 */
2096 if ((i == 4) || (i == 5))
2105 * Restore debug regs if using kgdbwait and you have a kernel debugger
2106 * connection established.
2108 static void dbg_restore_debug_regs(void)
2110 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2111 arch_kgdb_ops.correct_hw_break();
2113 #else /* ! CONFIG_KGDB */
2114 #define dbg_restore_debug_regs()
2115 #endif /* ! CONFIG_KGDB */
2117 static inline void setup_getcpu(int cpu)
2119 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2120 struct desc_struct d = { };
2122 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2123 wrmsr(MSR_TSC_AUX, cpudata, 0);
2125 /* Store CPU and node number in limit. */
2127 d.limit1 = cpudata >> 16;
2129 d.type = 5; /* RO data, expand down, accessed */
2130 d.dpl = 3; /* Visible to user code */
2131 d.s = 1; /* Not a system segment */
2132 d.p = 1; /* Present */
2133 d.d = 1; /* 32-bit */
2135 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2138 #ifdef CONFIG_X86_64
2139 static inline void tss_setup_ist(struct tss_struct *tss)
2141 /* Set up the per-CPU TSS IST stacks */
2142 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2143 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2144 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2145 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2146 /* Only mapped when SEV-ES is active */
2147 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2149 #else /* CONFIG_X86_64 */
2150 static inline void tss_setup_ist(struct tss_struct *tss) { }
2151 #endif /* !CONFIG_X86_64 */
2153 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2155 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2157 #ifdef CONFIG_X86_IOPL_IOPERM
2158 tss->io_bitmap.prev_max = 0;
2159 tss->io_bitmap.prev_sequence = 0;
2160 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2162 * Invalidate the extra array entry past the end of the all
2163 * permission bitmap as required by the hardware.
2165 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2170 * Setup everything needed to handle exceptions from the IDT, including the IST
2171 * exceptions which use paranoid_entry().
2173 void cpu_init_exception_handling(void)
2175 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2176 int cpu = raw_smp_processor_id();
2178 /* paranoid_entry() gets the CPU number from the GDT */
2181 /* For IDT mode, IST vectors need to be set in TSS. */
2182 if (!cpu_feature_enabled(X86_FEATURE_FRED))
2184 tss_setup_io_bitmap(tss);
2185 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2189 /* GHCB needs to be setup to handle #VC. */
2192 if (cpu_feature_enabled(X86_FEATURE_FRED))
2193 cpu_init_fred_exceptions();
2199 * cpu_init() initializes state that is per-CPU. Some data is already
2200 * initialized (naturally) in the bootstrap process, such as the GDT. We
2201 * reload it nevertheless, this function acts as a 'CPU state barrier',
2202 * nothing should get across.
2206 struct task_struct *cur = current;
2207 int cpu = raw_smp_processor_id();
2210 if (this_cpu_read(numa_node) == 0 &&
2211 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2212 set_numa_node(early_cpu_to_node(cpu));
2214 pr_debug("Initializing CPU#%d\n", cpu);
2216 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2217 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2218 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2220 if (IS_ENABLED(CONFIG_X86_64)) {
2222 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2225 wrmsrl(MSR_FS_BASE, 0);
2226 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2233 cur->active_mm = &init_mm;
2235 initialize_tlbstate_and_flush();
2236 enter_lazy_tlb(&init_mm, cur);
2239 * sp0 points to the entry trampoline stack regardless of what task
2242 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2244 load_mm_ldt(&init_mm);
2246 clear_all_debug_regs();
2247 dbg_restore_debug_regs();
2249 doublefault_init_cpu_tss();
2254 load_fixmap_gdt(cpu);
2257 #ifdef CONFIG_MICROCODE_LATE_LOADING
2259 * store_cpu_caps() - Store a snapshot of CPU capabilities
2260 * @curr_info: Pointer where to store it
2264 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2266 /* Reload CPUID max function as it might've changed. */
2267 curr_info->cpuid_level = cpuid_eax(0);
2269 /* Copy all capability leafs and pick up the synthetic ones. */
2270 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2271 sizeof(curr_info->x86_capability));
2273 /* Get the hardware CPUID leafs */
2274 get_cpu_cap(curr_info);
2278 * microcode_check() - Check if any CPU capabilities changed after an update.
2279 * @prev_info: CPU capabilities stored before an update.
2281 * The microcode loader calls this upon late microcode load to recheck features,
2282 * only when microcode has been updated. Caller holds and CPU hotplug lock.
2286 void microcode_check(struct cpuinfo_x86 *prev_info)
2288 struct cpuinfo_x86 curr_info;
2290 perf_check_microcode();
2292 amd_check_microcode();
2294 store_cpu_caps(&curr_info);
2296 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2297 sizeof(prev_info->x86_capability)))
2300 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2301 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2306 * Invoked from core CPU hotplug code after hotplug operations
2308 void arch_smt_update(void)
2310 /* Handle the speculative execution misfeatures */
2311 cpu_bugs_smt_update();
2312 /* Check whether IPI broadcasting can be enabled */
2316 void __init arch_cpu_finalize_init(void)
2318 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);
2320 identify_boot_cpu();
2322 select_idle_routine();
2325 * identify_boot_cpu() initialized SMT support information, let the
2328 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core);
2330 if (!IS_ENABLED(CONFIG_SMP)) {
2332 print_cpu_info(&boot_cpu_data);
2335 cpu_select_mitigations();
2339 if (IS_ENABLED(CONFIG_X86_32)) {
2341 * Check whether this is a real i386 which is not longer
2342 * supported and fixup the utsname.
2344 if (boot_cpu_data.x86 < 4)
2345 panic("Kernel requires i486+ for 'invlpg' and other features");
2347 init_utsname()->machine[1] =
2348 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2352 * Must be before alternatives because it might set or clear
2359 * Ensure that access to the per CPU representation has the initial
2360 * boot CPU configuration.
2363 c->initialized = true;
2365 alternative_instructions();
2367 if (IS_ENABLED(CONFIG_X86_64)) {
2369 * Make sure the first 2MB area is not mapped by huge pages
2370 * There are typically fixed size MTRRs in there and overlapping
2371 * MTRRs into large pages causes slow downs.
2373 * Right now we don't do that with gbpages because there seems
2374 * very little benefit for that case.
2376 if (!direct_gbpages)
2377 set_memory_4k((unsigned long)__va(0), 1);
2379 fpu__init_check_bugs();
2383 * This needs to be called before any devices perform DMA
2384 * operations that might use the SWIOTLB bounce buffers. It will
2385 * mark the bounce buffers as decrypted so that their usage will
2386 * not cause "plain-text" data to be decrypted when accessed. It
2387 * must be called after late_time_init() so that Hyper-V x86/x64
2388 * hypercalls work when the SWIOTLB bounce buffers are decrypted.